Date: 7/29/04

SP503 Multiprotocol Transceiver

Single Chip Programmable Serial

Transceiver

Seven (7) Drivers and Seven (7)

Receivers

Software-Selectable Industry Standard

Protocols:
-- RS-232 (V.28)
-- EIA-530
-- RS-449
-- RS-422A (V.11, X.27)
-- RS-485
-- V.35

Independant Driver and Receiver Mode

Selection

+5V Single Power Supply Operation
Surface Mount Packaging

SP503

Charge

Pump

Receiver

Decode

Driver

Decode

Receivers

Drivers

DESCRIPTION

The SP503 is a highly integrated serial transceiver that allows software control of its interface
modes. It offers hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS-485,
V.35, and EIA-530. The SP503 is fabricated using lowpower BiCMOS process technology, and
incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation.

SP503

Multiprotocol Transceiver

Now Available in Lead Free Packaging

RxD 1

RDEC

TTEN 6

SCTEN 7

TDEC

DTR 13

TxD 14

TxC 15

RTS 16

RL 17

NC 18

DCD 19

RxC 20

RI 21

ST 22

STEN 23

LL 24

GND 29

GND 34

RR(a) 35

RR(b) 36

RT(a) 37

RT(b) 38

IC(a) 39

IC(b) 40

60 GND

59 SD(b)

58 TR(a)

57 GND

56 TR(b)

55 V

54 RS(a)

53 GND

52 RS(b)

51 LL(a)

50 GND

49 LL(b)

48 V

47 RL(a)

46 GND

45 RL(b)

44 ST(b)

43 GND

42 ST(a)

41 V

80 CTS

79 SCT

78 DSR

SCT(b)

76 SCT(a)

75 GND

74 V

73 V

72 GND

71 RD(b)

70 RD(a)

69 DM(b)

68 DM(a)

67 CS(b)

66 CS(a)

65 TT(b)

64 GND

63 TT(a)

62 V

61 SD(a)

SP503

Date: 7/29/04

SP503 Multiprotocol Transceiver

ELECTRICAL CHARACTERISTICS

MIN

to T

MAX

@ Vcc = +5V ±5% unless otherwise noted.

MIN.

TYP.

MAX.

UNITS

CONDITIONS

LOGIC INPUTS
V

0.8

Volts

2.0

Volts

LOGIC OUTPUTS
V

0.4

Volts

OUT

= -3.2mA

2.4

Volts

OUT

= 1.0mA

RS-485 DRIVER
TTL Input Levels

0.8

Volts

2.0

Volts

Outputs

HIGH Level Output

+6.0

Volts

LOW level Output

0.3

Volts

Differential Output

±1.5

±5.0

Volts

=54, C

=50pF

Balance

±0.2

Volts

| - |V

Open Circuit Voltage

±6.0

Volts

Output Current

28.0

=54

Short Circuit Current

±250

Terminated in 7V to +12V

Transition Time

120

Rise/fall time, 10%90%

Maximum Transmission Rate

Mbps

=54

Propagation Delay
t

PHL

200

=54

PLH

200

=54

RS-485 RECEIVER
TTL Output Levels

0.4

Volts

2.4

Volts

Input

HIGH Threshold

+0.2

+12.0

Volts

(a)-(b)

LOW Threshold

7.0

0.2

Volts

(a)-(b)

Common Mode Range

7.0

+12.0

Volts

HIGH Input Current

Refer to graph

LOW Input Current

Refer to graph

Receiver Sensitivity

±0.2

Volts

Over 7V to +12V common
mode range

Input Impedance

Maximum Transmission Rate

Mbps

Propagation Delay
t

PHL

200

PLH

200

V.35 DRIVER
TTL Input Levels

0.8

Volts

2.0

Volts

Outputs

Differential Output

±0.44

±0.66

Volts

With termination network in
Figure 6; R

=100

Output Impedance

150

With termination network in
Figure 6.

Short Circuit Impedance

135

150

165

With termination network
in Figure 6.

Transition Time

Maximum Transmission Rate

Mbps

=100

Propagation Delay
t

PHL

200

=100

PLH

200

=100

Date: 7/29/04

SP503 Multiprotocol Transceiver

ELECTRICAL CHARACTERISTICS

MIN

to T

MAX

@ Vcc = +5V ±5% unless otherwise noted.

MIN.

TYP.

MAX.

UNITS

CONDITIONS

V.35 RECEIVER
TTL Output Levels

0.4

Volts

2.4

Volts

Input
Receiver Sensitivity

±0.2

Volts

Input Impedance

100

110

With termination network
in Figure 6.

Short Circuit Impedance

135

150

165

With termination network
in Figure 6.

Maximum Transmission Rate

Mbps

Propagation Delay
t

PHL

200

PLH

200

RS-422 DRIVER
TTL Input Levels

0.8

Volts

2.0

Volts

Outputs

Differential Output

±2.0

±5.0

Volts

=100

Open Circuit Voltage,V

±6.0

Volts

Balance

±0.4

Volts

| |V

Offset

+3.0

Volts

Short Circuit Current

±150

OUT

=0V

Power Off Current

±100

µA

= 0V, V

out

= ±0.25V

Transition Time

Rise/fall time, 10%-90%

Maximum Transmission Rate

Mbps

=100

Propagation Delay
t

PHL

200

=100

PLH

200

=100

RS-422 RECEIVER
TTL Output Levels

0.4

Volts

2.4

Volts

Input

HIGH Threshold

+0.2

+6.0

Volts

(a)-(b)

LOW Threshold

6.0

0.2

Volts

(a)-(b)

Common Mode Range

7.0

+7.0

Volts

HIGH Input Current

Refer to graph

LOW Input Current

Refer to graph

Receiver Sensitivity

±0.2

Volts

=+7V to -7V

Input Impedance

=+10V to -10V

Maximum Transmission Rate

Mbps

Propagation Delay
t

PHL

200

PLH

200

RS-232 DRIVER
TTL Input Level

0.8

Volts

2.0

Volts

Outputs

HIGH Level Output

+5.0

+15

Volts

=3k, V

=0.8V, V

= 5V

LOW Level Output

15.0

5.0

Volts

=3k, V

=2.0V, V

= 5V

Open Circuit Voltage

+15

Volts

Short Circuit Current

±100

OUT

=0V

Power Off Impedance

300

= 0V, V

out

= ±2.0V

Date: 7/29/04

SP503 Multiprotocol Transceiver

ELECTRICAL CHARACTERISTICS

MIN

to T

MAX

@ Vcc = +5V ±5% unless otherwise noted.

MIN.

TYP.

MAX.

UNITS

CONDITIONS

Slew Rate

V/µs

=3k, C

=15pF

Transition Time

1.56

µs

=3k, C

=2500pF

Maximum Transmission Rate

120

kbps

=3k, C

=2500pF

Propagation Delay
t

PHL

µs

=3k

PLH

µs

=3k

RS-232 RECEIVER
TTL Output Levels

0.4

Volts

2.4

Volts

Input

HIGH Threshold

1.7

2.4

Volts

LOW Threshold

0.8

1.2

Volts

Receiver Open Circuit Bias

+2.0

Volts

Input Impedance

=+15V to -15V

Maximum Transmission Rate

120

kbps

Propagation Delay
t

PHL

µs

PLH

µs

RS-423 DRIVER
TTL Input Levels

0.8

Volts

2.0

Volts

Output

Open Circuit Voltage

±4.0

±10.0

Volts

HIGH Level Output

+3.6

+6.0

Volts

=550

LOW Level Output

6.0

3.6

Volts

=550

Short Circuit Current

±150

OUT

=0V

Power Off Current

±100

µA

= 0V, V

out

= ±0.25V

Transition Time

0.8

2.4

µs

Rise/fall time, 10-90%

Maximum Transmission Rate

120

kbps

=550

Propagation Delay
t

PHL

µs

=550

PLH

µs

=550

RS-423 RECEIVER
TTL Output Levels

0.4

Volts

2.4

Volts

Input

HIGH Threshold

+0.2

+7.0

Volts

LOW Threshold

7.0

0.2

Volts

HIGH Input Current

Refer to graph

LOW Input Current

Refer to graph

Receiver Sensitivity

±0.2

Volts

= +7V to -7V

Input Impedance

= +10V to -10V

Maximum Transmission Rate

120

kbps

Propagation Delay
t

PHL

µs

PLH

µs

POWER REQUIREMENTS
V

4.75

5.25

Volts

=5V; no interface selected

ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range

+70

°C

Storage Temperature Range

+150

°C

Package

80pin QFP

Date: 7/29/04

SP503 Multiprotocol Transceiver

V.35

47.0mA

48.8mA

47.3mA

54.5mA 104.2mA

100.9mA

RS-232

35.4mA

37.8mA

35.2mA

43.6mA

54.1mA

57.1mA

55.9mA

RS-422

25.8mA

31.4mA

25.8mA

27.5mA

140.2mA

135.9mA

145.2mA

RS-485

33.4mA

37.91mA

33.51mA

34.81mA

200.3mA

194.8mA

203.3mA

RS-449

37.8mA

40.3mA

41.1mA

42.9mA

142.3mA

138.8mA

147.4mA

EIA-530

45.2mA

48.1mA

44.4mA

50.3mA

148.9mA

145.7mA

147.3mA

+1.0mA

0.6mA

+12V

+6V

1 Unit Load
Maximum Input Current
versus Voltage

RS-485 RECEIVER

+3.25mA

3.25mA

+10V

+3V

10V

Maximum Input Current
versus Voltage

RS-422 RECEIVER

+3.25mA

3.25mA

+10V

+3V

10V

Maximum Input Current
versus Voltage

RS-423 RECEIVER

RECEIVER INPUT GRAPHS

POWER MATRIX

Mode Open Input Input to 5V Input to GND AC Signal Input to 5V Input to GND AC Signal

Conditions

to Input with Load with Load with Load

With external termination resistor network;
Input @ 60kHz, Load is 3k & 2500pF for
RS-232 and 100 for V.35

Input @ 60kHz
Load is 100 for RS-422

450 for RS-423

Input @ 60kHz
Load is 100 for RS-422

450 for RS-423

Input @ 2.5MHz
Load is 54.

Input @ 2.5MHz
Load is 100.

Input @ 60kHz
Load is 3k & 2500pF for RS-232.

Typical @ 25°C and V

= +5V unless otherwise noted. Input is applied to one driver.

Date: 7/29/04

SP503 Multiprotocol Transceiver

OTHER AC CHARACTERISTICS

(Typical @ 25°C and nominal supply voltages unless otherwise noted)

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

DELAY TIME FROM ENABLE MODE TO TRISTATE MODE

SINGLEENDED MODE (RS-232, RS-423)

PZL

; Enable to Output LOW

190

3k pullup to output

PZH

; Enable to Output HIGH

130

3k pulldown to output

PLZ

; Disable from Output LOW

270

5V to input

PHZ

; Disable from Output HIGH

400

GND to input

DIFFERENTIAL MODE (RS-422, RS-485, V.35)

PZL

; Enable to Output LOW

100

3k pullup to output

PZH

; Enable to Output HIGH

100

3k pulldown to output

PLZ

; Disable from Output LOW

130

5V to input

PHZ

; Disable from Output HIGH

140

GND to input

Notes:
1.

Measured from 2.5V of R

to 2.5V of R

OUT

Measured from onehalf of R

to 2.5V of R

OUT

Measured from 1.5V of T

to onehalf of T

OUT

Measured from 2.5V of R

to 0V of A and B.

PINOUT...

RxD 1

RDEC

TTEN 6

SCTEN 7

TDEC

DTR 13

TxD 14

TxC 15

RTS 16

RL 17

NC 18

DCD 19

RxC 20

RI 21

ST 22

STEN 23

LL 24

GND 29

GND 34

RR(a) 35

RR(b) 36

RT(a) 37

RT(b) 38

IC(a) 39

IC(b) 40

60 GND

59 SD(b)

58 TR(a)

57 GND

56 TR(b)

55 V

54 RS(a)

53 GND

52 RS(b)

51 LL(a)

50 GND

49 LL(b)

48 V

47 RL(a)

46 GND

45 RL(b)

44 ST(b)

43 GND

42 ST(a)

41 V

80 CTS

79 SCT

78 DSR

SCT(b)

76 SCT(a)

75 GND

74 V

73 V

72 GND

71 RD(b)

70 RD(a)

69 DM(b)

68 DM(a)

67 CS(b)

66 CS(a)

65 TT(b)

64 GND

63 TT(a)

62 V

61 SD(a)

SP503

PIN ASSIGNMENTS...
CLOCK AND DATA GROUP
Pin 1 -- RxD -- Receive Data; TTL output,
sourced from RD(a) and RD(b) inputs.

Pin 14 -- TxD -- TTL input ; transmit data
source for SD(a) and SD(b) outputs.

Pin 15 -- TxC -- Transmit Clock; TTL input for
TT driver outputs.

Pin 20 -- RxC -- Receive Clock; TTL output
sourced from RT(a) and RT(b) inputs.

Pin 22 -- ST -- Send Timing; TTL input; source
for ST(a) and ST(b) outputs.

Pin 37 -- RT(a) -- Receive Timing; analog
input, inverted; source for RxC.

Pin 38 -- RT(b) -- Receive Timing; analog
input, non-inverted; source for RxC.

Pin 42 -- ST(a) -- Send Timing; analog output,
inverted; sourced from ST.

Pin 44 -- ST(b) -- Send Timing; analog output,
non-inverted; sourced from ST.

Pin 59 -- SD(b) -- Analog Out -- Send data,
non-inverted; sourced from TxD.

Pin 61 -- SD(a) -- Analog Out -- Send data,
inverted; sourced from TxD.

Pin 63 -- TT(a) -- Analog Out -- Terminal
Timing, inverted; sourced from TxC

Pin 65 -- TT(b) -- Analog Out -- Terminal
Timing, noninverted; sourced from TxC.

Pin 70 -- RD(a) -- Receive Data, analog input;
inverted; source for RxD.

Date: 7/29/04

SP503 Multiprotocol Transceiver

Pin 71 -- RD(b) -- Receive Data; analog input;
non-inverted; source for RxD.

Pin 76 -- SCT(a) -- Serial Clock Transmit;
analog input, inverted; source for SCT.

Pin 77 -- SCT(b) -- Serial Clock Transmit:
analog input, noninverted; source for SCT

Pin 79 -- SCT -- Serial Clock Transmit; TTL
output; sources from SCT(a) and SCT(b) inputs.

CONTROL LINE GROUP
Pin 13 -- DTR -- Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.

Pin 16 -- RTS -- Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.

Pin 17 -- RL -- Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.

Pin 19 -- DCD-- Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b) inputs.

Pin 21 -- RI -- Ring In; TTL output; sourced
from IC(a) and IC(b) inputs.

Pin 24 -- LL -- Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.

Pin 35 -- RR(a)-- Receiver Ready; analog
input, inverted; source for DCD.

Pin 36 -- RR(b)-- Receiver Ready; analog
input, non-inverted; source for DCD.

Pin 39 -- IC(a)-- Incoming Call; analog input,
inverted; source for RI.

Pin 40 -- IC(b)-- Incoming Call; analog input,
non-inverted; source for RI.

Pin 45 -- RL(b) -- Remote Loopback; analog
output, non-inverted; sourced from RL.

Pin 47 -- RL(a) -- Remote Loopback; analog
output inverted; sourced from RL.

Pin 49-- LL(b) -- Local Loopback; analog
output, non-inverted; sourced from LL.

Pin 51 -- LL(a) -- Local Loopback; analog
output, inverted; sourced from LL.

Pin 52 -- RS(b) -- Ready To Send; analog
output, non-inverted; sourced from RTS.

Pin 54 -- RS(a) -- Ready To Send; analog
output, inverted; sourced from RTS.

Pin 56 -- TR(b) -- Terminal Ready; analog
output, non-inverted; sourced from DTR.

Pin 58 -- TR(a) -- Terminal Ready; analog
output, inverted; sourced from DTR.

Pin 66 -- CS(a)-- Clear To Send; analog input,
inverted; source for CTS.

Pin 67 -- CS(b)-- Clear To Send; analog input,
non-inverted; source for CTS.

Pin 68 -- DM(a)-- Data Mode; analog input,
inverted; source for DSR.

Pin 69 -- DM(b)-- Data Mode; analog input,
non-inverted; source for DSR

Pin 78 -- DSR-- Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.

Pin 80 -- CTS-- Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.

CONTROL REGISTERS
Pins 25 -- RDEC

RDEC

-- Receiver

decode register; configures receiver modes; TTL
inputs.

Pin 6 -- TTEN -- Enables TT driver, active
low; TTL input.

Pin 7 -- SCTEN -- Enables SCT receiver;
active high; TTL input.

Pins 129 -- TDEC

TDEC

-- Transmitter

decode register; configures transmitter modes;
TTL inputs.

Pin 23 -- STEN -- Enables ST driver; active
low; TTL input.

POWER SUPPLIES
Pins 8, 25, 33, 41, 48, 55, 62, 73, 74 -- V

+5V input.

Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 --
GND -- Ground.

Pin 27 -- V

+10V Charge Pump Capacitor --

Connects from V

to V

. Suggested capaci-

tor size is 22

µF, 16V.

Date: 7/29/04

SP503 Multiprotocol Transceiver

Pin 32 -- V

10V Charge Pump Capacitor --

Connects from ground to V

. Suggested ca-

pacitor size is 22

µF, 16V.

Pins 26 and 30 -- C

and C

-- Charge Pump

Capacitor -- Connects from C

to C

. Sug-

gested capacitor size is 22

µF, 16V.

Pins 28 and 31 -- C

and C

-- Charge Pump

Capacitor -- Connects from C

to C

. Sug-

gested capacitor size is 22

µF, 16V.

NOTE: NC pins should be left floating; internal
signals may be present.

pared to older lessefficient designs. The charge
pump still requires four external capacitors, but
uses a fourphase voltage shifting technique to
attain symmetrical 10V power supplies. Figure
3(a) shows the waveform found on the positive
side of capcitor C2, and Figure 3(b) shows the
negative side of capcitor C2. There is a free
running oscillator that controls the four phases
of the voltage shifting. A description of each
phase follows.

Phase 1
-- V

charge storage --During this phase of

the clock cycle, the positive side of capacitors
C

and C

are initially charged to +5V. C

then switched to ground and the charge on C

transferred to C

. Since C

is connected to

+5V, the voltage potential across capacitor C

is now 10V.

Phase 2
-- V

transfer -- Phase two of the clock con-

nects the negative terminal of C

to the V

storage capacitor and the positive terminal of C

to ground, and transfers the generated l0V to
C

. Simultaneously, the positive side of capaci-

tor C

is switched to +5V and the negative side

is connected to ground.

Phase 3
-- V

charge storage -- The third phase of the

clock is identical to the first phase -- the charge
transferred in C

produces 5V in the negative

terminal of C

, which is applied to the negative

side of capacitor C

. Since C

is at +5V, the

voltage potential across C

is l0V.

Phase 4
-- V

transfer -- The fourth phase of the

clock connects the negative terminal of C

ground and transfers the generated l0V across
C

to C

, the V

storage capacitor. Again,

FEATURES...
The SP503 is a highly integrated serial trans-
ceiver that allows software control of its inter-
face modes. The SP503 offers hardware inter-
face modes for RS-232 (V.28), RS-422A (V.11),
RS-449, RS-485, V.35, and EIA-530. The inter-
face mode selection is done via an 8bit switch;
four (4) bits control the drivers and four (4) bits
control the receivers. The SP503 is fabricated
using lowpower BiCMOS process technology,
and incorporates a Sipex patented (5,306,954)
charge pump allowing +5V only operation. Each
device is packaged in an 80pin Quad FlatPack
package.

The SP503 is ideally suited for wide area net-
work connectivity based on the interface modes
offered and the driver and receiver
configurations. The SP503 has seven (7)
independent drivers and seven (7) independent
receivers. The seventh driver of the SP503
allows it to support applications which require
two separate clock outputs making it ideal for
DCE applications.

THEORY OF OPERATION
The SP503 is made up of four separate circuit
blocks -- the charge pump, drivers, receivers,
and decoder. Each of these circuit blocks is
described in more detail below.

ChargePump
The charge pump is a Sipex patented design
(5,306,954) and uses a unique approach com-

= +5V

+5V

Storage Capacitor

Figure 1. Charge Pump Phase 1.

Date: 7/29/04

SP503 Multiprotocol Transceiver

Figure 3. Charge Pump Waveforms

+10V

GND

10V

= +5V

10V

Storage Capacitor

Figure 2. Charge Pump Phase 2.

and RS-423 drivers. For the RS-232 driver, the
current requirement will be 3.5mA per driver,
and for the RS-423 driver, the worst case current
drain will be 11mA per driver. The external
power supplies should provide a power supply
sequence of : +l0V, then +5V, followed by l0V.

Drivers
The SP503 has seven (7) independent drivers,
two of which have separate activelow tristate
controls. If a half-duplex channel is required,
this can be achieved with external connections.

Control for the mode selection is done via a
fourbit control word. The SP503 does not have
a latch; the control word must be externally
latched either high or low to write the appropri-
ate code into the SP503. The drivers are pre-
arranged such that for each mode of operation
the relative position and functionality of the
drivers are set up to accommodate the selected
interface mode. As the mode of the drivers is
changed, the electrical characteristics will change
to support the requirements of clock, data, and
control line signal levels. Table 1 shows a sum-
mary of the electrical characteristics of the driv-
ers in the different interface modes. Unused
driver inputs can be left floating; however, to
ensure a desired state with no input signal, pull
up resistors to +5V or pulldown resistors to
ground are suggested. Since the driver inputs
are both TTL or CMOS compatible, any value
resistor less than 100k

will suffice.

simultaneously with this, the positive side of
capacitor C

is switched to +5V and the negative

side is connected to ground, and the cycle begins
again.

Since both V+ and V

are separately generated

from V

in a noload condition, V+ and V

will

be symmetrical. Older charge pump approaches
that generate V

from V+ will show a decrease

in the magnitude of V

compared to V+ due to

the inherent inefficiencies in the design.

The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be 22

µF with a 16V breakdown rating.

External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V

pins. The value of the external supply volt-

ages must be no greater than

±l0V. The current

drain for the

±10V supplies is used for RS-232,

Date: 7/29/04

SP503 Multiprotocol Transceiver

= +5V

+5V

Storage Capacitor

Figure 4. Charge Pump Phase 3.

= +5V

+10V

Storage Capacitor

Figure 5. Charge Pump Phase 4.

There are three basic types of driver circuits --
RS-232, RS-423, and RS-485. The RS-232 driv-
ers output a minimum of

±5V level single

ended signals (with 3k

and 2500pF loading),

and can operate up to 120kbps. The RS-232
drivers are used in RS-232 mode for all signals,
and also in V.35 mode where they are used as the
control line signals.

The RS-423 drivers output a minimum of

±3.6V

level singleended signals (with 450

loading)

and can operate up to 120kbps. Open circuit V

and V

measurements may exceed the

±6V

limitation of RS-423. The RS-423 drivers are
used in RS-449 and EIA-530 modes as RL and
LL outputs.

The third type of driver supports RS-485, which
is a differential signal that can maintain

±1.5V

differential output levels with a worst case load
of 54

. The signal levels and drive capability of

the RS-485 drivers allow the drivers to also
support RS-422 requirements of

±2V differen-

tial output levels with 100

loads. The RS-422

drivers are used in RS-449 and EIA-530 modes
as clock, data, and some control line signals.

The RS-485type drivers are also used in the
V.35 mode. V.35 levels require

±0.55V signals

with a load of 100

. In order to meet the voltage

requirements of V.35, external series resistors
with source impedance termination resistors
must be implemented to voltage divide the driver
outputs from 0 to +5V to 0 to +0.55V. Figure 6
shows the values of the resistor network and
how to connect them. The termination network
also achieves the 50

to 150 source imped-

ance for V.35. For applications that require
V.11 signals for clock and data instead of V.35
levels, omit the external termination networks.
All of the differential drivers, RS-485, RS-422,
and V.35 can operate up to 5Mbps.

Table 1. SP503 Drivers

Pin Label

Mode:

RS-232

V.35

RS-422

RS-485

RS-449

EIA-530

TDEC

0000

0010

1110

0100

0101

1100

1101

SD(a)

tristate

RS-232

V.35

RS-422

RS-485

RS-422

SD(b)

tristate

V.35+

RS-422+

RS-485+

RS-422+

TR(a)

tristate

RS-232

RS-422

RS-485

RS-422

TR(b)

tristate

RS-422+

RS-485+

RS-422+

RS(a)

tristate

RS-232

RS-422

RS-485

RS-422

RS(b)

tristate

RS-422+

RS-485+

RS-422+

RL(a)

tristate

RS-232

RS-422

RS-485

RS-423

RL(b)

tristate

RS-422+

RS-485+

tristate

LL(a)

tristate

RS-232

RS-422

RS-485

RS-423

LL(b)

tristate

RS-422+

RS-485+

tristate

ST(a)

tristate

RS-232

V.35

RS-422

RS-485

RS-422

ST(b)

tristate

V.35+

RS-422+

RS-485+

RS-422+

TT(a)

tristate

RS-232

V.35

RS-422

RS-485

RS-422

TT(b)

tristate

V.35+

RS-422+

RS-485+

RS-422+

Date: 7/29/04

SP503 Multiprotocol Transceiver

SP503

22µF, 16V

22µF (V

decoupling)

+5V, ±5%

22µF

16V

22µF

16V

22µF, 16V

GND

Charge

Pump

V.35 External
Driver Output

Termination Resistors

All V

connections can be tied

together. Charge pump capacitors must
be placed as close to the package as
possible.

107

-5V

232

107

-5V

232

120

V.35 External

Receiver Input

Termination Resistors

Receiver

Decode

Driver

Decode

Ext.

Latch

V.35 MODE Control Word

Note: An external voltage of -5V, ±5% is needed for the driver output termination resistors.
These V.35 termination resistors comply with all the parameters specified in CCITT
Recommendation V.35. For other termination configurations, please consult factory.

IN5819

200

107

-5V

232

200

120

Figure 6. Typical Operating Circuit

Date: 7/29/04

SP503 Multiprotocol Transceiver

There are three basic types of receivers --
RS-232, RS-423, and RS-485. The RS-232
receiver is a singleended input with a threshold
of 0.8V to 2.4V. The RS-232 receiver has an
operating voltage range of

±15V and can re-

ceive signals up to 120kbps. RS-232 receivers
are used in RS-232 mode for all signal types, and
in V.35 mode for control line signals.

The RS-423 receivers are also singleended but
have an input threshold as low as

±200mV. The

input impedance is guaranteed to be greater than
4k

, with an operating voltage range of ±7V.

The RS-423 receivers can operate up to 120kbps.
RS-423 receivers are used for the IC signal in
RS-449 and EIA-530 modes, as shown in Table 2.

The third type of receiver supports RS-485,
which is a differential interface mode. The
RS-485 receiver has an input impedance of
15k

and a differential threshold of ±200mV.

Since the characteristics of an RS-422 receiver
are actually subsets of RS-485, the receivers for
RS-422 requirements are identical to the
RS-485 receivers. RS-422 receivers are used in
RS-449 and EIA-530 for receiving clock, data,
and some control line signals. The RS-485
receivers are also used for the V.35 mode. V.35
levels require the

±0.55V signals with a load of

100

. In order to meet the V.35 input imped-

ance of 100

, the external termination network

of Figure 6 must be applied. The threshold of the
V.35 receiver is

±200mV. The V.35 receivers

Pin Label

Mode:

RS-232

V.35

RS-422

RS-485

RS-449

EIA-530

RDEC

0000

0010

1110

0100

0101

1100

1101

RD(a)

Undefined

RS-232

V.35

RS-422

RS-485

RS-422

RD(b)

Undefined

15k to GND

V.35+

RS-422+

RS-485+

RS-422+

RT(a)

Undefined

RS-232

V.35

RS-422

RS-485

RS-422

RT(b)

Undefined

15k to GND

V.35+

RS-422+

RS-485+

RS-422+

CS(a)

Undefined

RS-232

RS-422

RS-485

RS-422

CS(b)

Undefined

15k to GND

15K to GND

RS-422+

RS-485+

RS-422+

DM(a)

Undefined

RS-232

RS-422

RS-485

RS-422

DM(b)

Undefined

15k to GND

15K to GND

RS-422+

RS-485+

RS-422+

RR(a)

Undefined

RS-232

RS-422

RS-485

RS-422

RR(b)

Undefined

15k to GND

15K to GND

RS-422+

RS-485+

RS-422+

IC(a)

Undefined

RS-232

RS-422

RS-485

RS-423

IC(b)

Undefined

15k to GND

15K to GND

RS-422+

RS-485+

15K to GND

SCT(a)

Undefined

RS-232

V.35

RS-422

RS-485

RS-422

SCT(b)

Undefined

15k to GND

V.35+

RS-422+

RS-485+

RS-422+

Receivers
The SP503 has seven (7) independent receivers
which can be programmed for six (6) different
interface modes. One of the seven (7) receivers
(SCT) has an activehigh enable control, as
shown in the Mode Diagrams.

Control for the mode selection is done via a 4
bit control word that is independent from the
driver control word. The coding for the drivers
and receivers is identical. Therefore, if the modes
for the drivers and receivers are supposed to be
identical in the application, the control lines can
be tied together.

Like the drivers, the receivers are pre-arranged
for the specific requirements of the interface. As
the operating mode of the receivers is changed,
the electrical characteristics will change to sup-
port the requirements of clock, data, and control
line receivers. Table 2 shows a summary of the
electrical characteristics of the receivers in the
different interface modes. Unused receiver in-
puts can be left floating without causing oscilla-
tion. To ensure a desired state of the receiver
output, a pullup resistor of 100k

to +5V

should be connected to the inverting input for a
logic low, or the noninverting input for a logic
high. For single-ended receivers, a pulldown
resistor to ground of 5k

is internally con-

nected, which will ensure a logic high output.

Table 2. SP503 Receivers

Date: 7/29/04

SP503 Multiprotocol Transceiver

can operate up to 5Mbps. All of the differential
receivers can receive data up to 5Mbps.

Decoder
The SP503 has the ability to change the inter-
face mode of the drivers or receivers via an 8bit
switch. The decoder for the drivers and receiv-
ers is not latched; it is merely a combinational
logic switch. The codes shown in Tables 1 and
2 are the only specified, valid modes for the
SP503. Undefined codes may represent other
interface modes not specified or random outputs
(consult the factory for more information). The
drivers are controlled with the data bits labeled
TDEC

TDEC

. The drivers can be put into tri-

state mode by writing 0000 to the driver decode
switch. The receivers are controlled with data
bits RDEC

RDEC

; the code 0000 written to

the receivers will place the outputs in an unde-
termined state. All receivers, with the exception
of SCT, do not have tri-state capability; the
outputs will either be HIGH or LOWdepending
upon the state of the receiver input.

Date: 7/29/04

SP503 Multiprotocol Transceiver

SP502/SP503 EVALUATION BOARD
The SP502/SP503 Evaluation Board (EB) Is
designed to offer as much flexibility to the user
as possible. Each board comes equipped with an
80-pin QFP Zero-Insertion Force socket to
allow for testing of multiple devices. The con-
trol lines and inputs and outputs of the device
can be controlled either manually or via a data
bus under software control. There is a 50-pin
connector to allow for easy connection to an
existing system via a ribbon cable. There are
also open areas on the PC board to add addi-
tional circuitry to support application-specific
requirements.

Manual Control
The SP502/SP503EB will support both the
SP502 or SP503 multi-mode serial transceiv-
ers. When used for the SP502, disregard all
notation on the board that is in [brackets] . The
SP502 has a half-duplex connection between
the RxT receiver and the TT driver. Due to this
internal connection, the RxT receiver inputs can
be accessed via the TT(a) and TT(b) pins. If the
user needs separate receiver input test pins,
jumpers JP1 and JP2 can be inserted to allow for
separate receiver inputs located at SCT(a) and
SCT(b). The corresponding TTL output for this
receiver is labeled as SCT. This test point is tied
to pin 79 of the SP502 or SP503. Pin 7 of the
evaluation board is connected to the DIP switch,
and is labeled as (SCTEN). When used with the
SP502, this pin should be switched to a low
state. When the evaluation board is used with
the SP503, pin 7 is a tri-state control pin for the
SCT receiver.

The transceiver I/O lines are brought out to test
pins arranged in the same configuration as shown
elsewhere in this data sheet. A top layer
silk-screen shows the drivers and receivers to
allow direct correlation to the data sheet. The
transmitter and receiver decode bits are tied
together and are brought out to a DIP switch for
manual control of both the driver and receiver
interface modes. Since the coding for the drivers
and receivers is identical, the bits have been tied
together. The DIP switch has 7 positions, four of
which are reserved for the TDEC/RDEC control
and the other three are used as tri-state control
pins. The labels that are in [brackets] apply only

to the SP503. If a logic one is asserted, the
corresponding red LED will be lit. If a zero is
asserted, the corresponding red LED will not
be lit.

Software Control
A 50-pin connector brings all the analog and
digital I/O lines, V

, and GND to the edge of the

card. This can be wired to the user's existing
design via a ribbon cable. The pinout for the
connector is described in the following section.
When the evaluation board is operated under
software control, the DlP switch should be set
up so that all bits are LOW (all LEDs off). This
will tie 20k

pulldown resistors from the inputs

to ground and let the external system control the
state of the control inputs.

Power and Ground Requirements
The evaluation board layout has been optimized
for performance by using basic analog circuit
techniques, The four charge-pump capacitors
must be 22

µF (16V) and be placed as close to the

unit as possible; tantalum capacitors are sug-
gested. The decoupling capacitor must be a
minimum of 1

µF; depending upon the operating

environment, 10

µF should be enough for worst

case situations. The ground plane for the part
must be solid, extending completely under the
package. The power supplies for the device
should be as accurate as possible; for rated
performance

±5% is necessary. The power sup-

ply current will vary depending upon the se-
lected mode, the amount of loading and the data
rate. As a maximum, the user should reserve
200mA for I

. The worst-case operating mode

is RS-485 under full load of six (6) drivers
supplying 1.6V to 54

loads. The power and

ground inputs can be supplied through either the
banana jacks on the evaluation board (Red = V

= +5V

±5%; Black = GND) or through the con-

nector.

For reference, the 80-pin QFP Socket is a
TESCO part number FPQ-80-65-09A. The
50-pin connector is an AMP part number
749075-5.

Date: 7/29/04

SP503 Multiprotocol Transceiver

EDGE

DUT PIN

CONNECTOR

DESCRIPTIONS

TxD (pin 14) TTL Input Transmit
data; source for SD(a) and SD(b) out-
puts.

DTR (pin 13) TTL Input Data
terminal ready: source for TR(a) and
TR(b) outputs.

ST/TT (pin 6) TTL Input ST/TT
select pin; enables ST drivers and dis-
ables TT drivers when high. Disables
ST drivers and enables TT drivers when
low.

DEC

/RDEC

(pin 5) TTL Input

Transmitter/Receiver decode register.

TDEC

/RDEC

(pin 4) TTL Input

Transmitter/Receiver decode register.

TDEC

/RDEC

(pin 3) TTL Input

Transmitter/Receiver decode register.

TDEC

/RDEC

(pin 2) TTL Input

Transmitter/Receiver decode register.

RxD (pin 1 ) TTL Output Receive
data; sourced from RD(a) and RD)b)
inputs.

CTS (pin 80) TTL Output Clear to
send; sourced from CS(a) and CS(b)
inputs.

RxT (pin 79) TTL Output RxT;
sourced from TT(a), TT(b) inputs.

DSR (pin 78) TTL Output Data set
ready; sourced from DM(a) and DM(b)
inputs.

RD(b) (pin 71) Analog In Receive
data, noninverted; source for RxD.

EDGE

DUT PIN

CONNECTOR

DESCRIPTIONS

RD(a) (pin 70) Analog In Receive
data, inverted: source for RxD.

DM(b) (pin 69) Analog In Data
mode, noninverted; source for DSR.

DM(a) (pin 68) Analog In Data
mode, inverted; source for DSR.

CS(b) (pin 67) Analog In Clear to
send; noninverted; source for CTS.

CS(a) (pin 66) Analog In Clear to
send, inverted; source for CTS.

TT(b) (pin 65) Analog Out
Terminal timing, noninverted:
sourced from TxC input.

TT(a) (pin 63) Analog Out
Terminal timing; inverted: sourced
from TxC input.

TR(a) (pin 58) Analog Out Termi-
nal ready, inverted; sourced from DTR.

TR(b) (pin 56) Analog Out Termi-
nal ready; noninverted; sourced from
DTR.

SD(a) (pin 61) Analog Out Send
data, inverted; sourced from TxD.

SD(b) (pin 59) Analog Out Send
data; noninverted; sourced from TxD.

RS(a) (pin 54) Analog Out Ready to
send; inverted; sourced from RTS.

RS(b) (pin 52) Analog Out Ready
to send, noninverted; sourced from
RTS.

Date: 7/29/04

SP503 Multiprotocol Transceiver

EDGE

DUT PIN

CONNECTOR

DESCRIPTIONS

ST (pin 22) TTL Input Send Tim-
ing; source for ST(a) and ST(b) out-
puts. SP503 only.

STEN (pin 23) TTL Input -- Driver
enable control pin; active low. SP503
only,

SCT(a) (pin 76) Analog Input In-
verting; input for SCT receiver; SP503
only.

SCT(b) (pin 77) Analog Input Non
inverting; input for SCT receiver.
SP503 only.

-- +5V for all circuitry.

GND -- signal and power ground.

32 LL(a) (pin 51) Analog Out Local

loopback, inverted; sourced from LL.

LL(b) (pin 49) Analog Out Local
loopback, noninverted sourced from
LL.

RL(a) (pin 47) Analog Out Remote
loopback; inverted; sourced from RL.

RL(b) (pin 45) Analog Out Remote
loopback; noninverted; sourced from
RL.

ST(b) (pin 44) Analog Out Send
timing, noninverted; sourced from
TxC.

ST(a) (pin 42) Analog Output Send
timing, inverted; sourced from TxC.

IC(b) (pin 40) Analog In Incoming
call; noninverted; source for Rl.

EDGE

DUT PIN

CONNECTOR

DESCRIPTIONS

IC(a) (pin 39) Analog In Incoming
call; inverted; source for Rl.

RT(b) (pin 38) Analog In Receive
timing, noninverted; source for RxC.

RT(a) (pin 37) Analog In Receive
timing; inverted; source from RxC.

RR(b) (pin 36) Analog In Receiver
ready; noninverted; source for DCD.

RR(a) (pin 35) Analog In Receiver
ready; inverted; source for DCD.

LL (pin 24) TTL Input Local
loopback; source for LL(a) and LL(b)
outputs.

Rl (pin 21) TTL Output Ring
indicator; sourced from IC(a) and IC(b)
inputs.

RxC (pin 20) TTL Output Receive
clock; sourced from RT(a) and RT(b)
inputs.

DCD (pin 19) TTL Output Data
carrier detect; sourced from RR(a) and
RR(b) inputs.

RL (pin 17) Analog Out Remote
loopback; source for RL(a) and RL(b)
outputs.

RTS (pin 16) TTL Input Ready to
send; source for RS(a) and RS(b) out-
puts.

TxC (pin 15) TTL Input Transmit
clock; source for TT(A) and TT(B)
outputs.

Date: 7/29/04

SP503 Multiprotocol Transceiver

ORDERING INFORMATION

Part Number Top Mark

Temperature Range

Package Types

SP503CF ............. SP503CFYYWW......0°C to +70°C ............................ 80pin JEDEC (MS-022 BC) MQFP
SP503EF.............SP503EFYYWW......-40°C to +85°C .......................... 80pin JEDEC (MS-022 BC) MQFP
SP503EM.............SP503EMYYWW......-40°C to +85°C .......................... 80pin JEDEC (MS-022 BC) LQFP

Corporation

ANALOG EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600

DATE

REVISION

DESCRIPTION

1/27/04

Implemented tracking revision.

5/6/04

Added Top Mark to ordering information.

7/29/04

Included LQFP package option.

REVISION HISTORY

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP503EF = standard; SP503EF-L = lead free

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SP503CF

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SP503CF