rev. 7/7/03

SP508 Evaluation Board Manual

The SP508 Evaluation Board is designed to analyze the SP508 multi-protocol transceivers.
The evaluation board provides access points to all of the driver and receiver I/O pins so that
the user can measure electrical characteristics and waveforms of each signal. The SP508
Evaluation Board also includes a DB-25 serial port connector which is configured to a EIA-530
pinout. This allows easy connections to other DTE or DCE systems as well as network
analyzers. The evaluation board also has dip switches to allow the user to select the mode
of operation and test the data latch feature. The SP508 Evaluation Board Provides the means
to test both local and remote driver/receiver Loopback as well as evaluate the SP508 in a DCE
or DTE configuration.

This Manual is split into sections to give the user the information necessary to perform a
thorough evaluation of the SP508. The Board Layout section describes the I/O pins, the Dip
switches and the other components used on the evaluation board. The board schematic,
layout diagram, list of materials and DB-25 connector are also covered in the Board Layout
section. The Using the SP508 Evaluation Board details the configuration of the SP508
evaluation board for parametric testing.

DESCRIPTION

SP508

Evaluation Board Manual

FEATURES

Easy Evaluation of SP508 Multi-Protocol

Transceiver

Eight (8) Drivers and Eight (8) Receivers

Current Mode V.35 Drivers

Internal Line or Digital Loopback

Internal Transceiver Termination

Resistors for V.11 and V.35

Termination Network Disable Option

Fast 20Mbps Differential Transmission

Rates

Adheres to CTR1/CTR2 Compliancy

Requirements

PCB Friendly Flow-Through Pinout

Improved ESD Tolerance for Analog I/Os

Interface modes:

RS-232

(V.28)

EIA-530

(V.10&V.11)

X.21

(V.11)

EIA-530A

(V.10&V.11)

RS-449/V.36

(V.10&V.11)

V.35

rev. 7/7/03

SP508 Evaluation Board Manual

LOOPBACK 27

LATCH

TERM_OFF 22

V35TGND1 99

V35TGND1 94

V35TGND1 89

V35TGND1 46

V35TGND1 58

C1+

C1-

C2+

C2-

GND * *

GND

2
2
2
2
2

1
1
1
1
1

105

115

114

106

107

109

125

142

3
16

17
9

15&
12&

5
13

6
22

8&
10&

2
14

24
11

4
19

20
23

25-Pin D-Sub

Connector Pins

1µF

10µF

103

113

105

108

109

140

141

TxD

TxCE

RTS

DTR

DCD

DCE

100

SD(a)

SD(b)

TT(a)

TT(b)

ST(a)

ST(b)

RS(a)

RS(b)

TR(a)

TR(b)

RRC(a)

RRC(b)

RL(a)

LL(a)

RxD

RxC

TxC

CTS

DSR

DCD

DTE

SD(a)

SD(b)

TT(a)

TT(b)

ST(a)

ST(b)

RS(a)

RS(b)

TR(a)

TR(b)

RRC(a)

RRC(b)

RL(a)

LL(a)

SDEN

TTEN

STEN

RSEN

TREN

RRSEN

RLEN

10 LLEN

11 RDEN

12 RTEN

13 TxCEN

14 CSEN

15 DMEN

16 RRTEN

17 ICEN

18 TMEN

DECODER

MODE

SHUTDOWN

V.35

EIA-530

RS-232

EIA-530A

RS-449

X.21

Driver applies for DCE only on pins 5 and 12.

Receiver applies for DTE only on Pins 5 and 12.

Driver applies for DCE only on Pins 8 and 10.

Receiver applies for DTE only on Pins 8 and 10.

* Pins 1,26,45,64,71,77,80,84,88,93,98 = VCC

** Pins 2,25,44,52,68,74,82,86,91,96 = GND

Pins 24 and 76 are no connects.

Circuit #

Connect jumper to enable internal cable termination

Logic high

Logic low

Loopback

OFF

No Loopback

Figure 1

rev. 7/7/03

SP508 Evaluation Board Manual

SP508 EVALUATION BOARD

Figure 2: RS-232 & EIA530 Connector (ISO 2110),
DTE Connector

DB-25 Male, DCE Connector DB-

25 Female

BOARD LAYOUT

1. The SP508 Evaluation board takes ad-
vantage of the products PCB friendly flow
through pinout in its design as shown in
Figure 1.

2. The SP508 Evaluation Board has been
designed to easily and conveniently provide
access to all inputs and outputs under test.

3. Figure 1 is a block diagram of the evalu-
ation board showing the layout of the SP508
Evaluation Board. The block diagram shows
the location of the driver and receiver ac-
cess points as well as the DIP switches, V

GND and the DB-25 Connector.

4. I/O Pinouts

The SP508 Evaluation Board has been de-
signed to easily and conveniently provide
access to all inputs and outputs to the device
under test. Position the Board with the DB-
25 connector at the top and the Dip switches
at the bottom. From this orientation , all
driver inputs and outputs are on the right-
hand side and all receiver inputs and out-
puts are on the left-hand side eof the Board.

4.1. Each Driver has probe points for the
input and outputs. There is a ground buss to
the right of the drive outputs for the addition
of loads to the driver outputs and to jumper
the V.35 that is associated with the SD, TT,
and ST driver. Each V.35 driver has a
separate ground for the V.35 termination
network internal to the device.

4.2. Each Receiver has probe points for the
inputs and outputs. there is a ground buss
to the left of the receiver outputs and a
separate pin for the V.10 termination ground.

5. At the bottom of the board is a series of
six(6) DIP switches. The DIP switch on the
far left is for D_LATCH and TERM_OFF.
Each driver and receiver has its own indi-
vidual enable pin. The DIP switches to
control the enable pins are located as the
top center bank of switches for the driver and
the middle center bank of switches for the
receiver. The bottom center set of DIP
switches is for the 3 bit decoder and the
loopback control pin. The right hand DIP
switches allow the user to tie the ST driver
outputs to the TxC receiver inputs and the
RRC driver outputs to the RRT receiver
inputs.

6. Also located on the SP508 evaluation
board are the four 10uf charge pump capaci-
tors, a 10uf bypass capacitor for V

and a

termination resistor.

7. Table 1 shows the pinout of the DB-25
connector used to connect to a communica-
tion analyzer such as the TTC Firebird 6000.

rev. 7/7/03

SP508 Evaluation Board Manual

Table 1.

EIA-232

EIA-530

EIA-449

V.35

X.21

Signal Name

source

Mnemonic

Pin

Mnemonic

Pin

Mnemonic

Pin

Mnemonic

Pin

Mnemonic

Pin

Shield

Transmitted data

DTE

BA(A)

SD(A)

103

Circuit T(A)

BA(B)

SD(B)

103

Circuit T(B)

Received Data

DCE

BB(A)

RD(A)

104

Circuit R(A)

BB(B)

RD(B)

104

Circuit R(B)

Request To Send

DTE

CA(A)

RS(A)

105

Circuit C(A)

CA(B)

RS(B)

Circuit C(B)

Clear To Send

DCE

CB(A)

CS(A)

106

Circuit I(A)

CB(B)

CS(B)

Circuit I(B)

DCE Ready (DSR) DCE

CC(A)

DM(A)

107

CC(B)

DM(B)

DTE Ready (DTR)

DTE

CD(A)

TR(A)

108

CD(B)

TR(B)

Signal Ground

102

Circuit G

Recv. Line Sig.

DCE

CF(A)

RR(A)

109

Det. (DCD)

CF(B)

RR(B)

Trans. Sig.

DCE

DB(A)

ST(A)

114

Circuit S(A)

Elemt. Timing

DB(B)

ST(B)

114

Circuit S(B)

Recv. Sig.

DTE

DD(A)

RT(A)

115

Circuit B(A)**

Elemt. Timing

DD(B)

RT(B)

115

Circuit B(B)**

Local Loopback

DCE

141

Remote Loopback

DTE

140

Ring Indicator

DCE

125

Trans. Sig.

DTE

DA(A)

TT(A)

113

Circuit X(A)**

Elemt. Timing

DA(B)

TT(B)

113

Circuit X(B)**

Test Mode

DCE

142

NN*

* Optional signals
** Only one of the two x.21 signals, Circuit B or X, can be implemented and active at one time.

rev. 7/7/03

SP508 Evaluation Board Manual

Table 2

Driver

V.35

EIA-530

RS-232

EIA-530A

RS-449

X.21

Suggested

Output Pin

Mode

Mode (V.28)

Mode

Mode (v.36) Mode (v.11)

Shutdown

Signal

MODE (D0,D1,D2)

001

010

011

100

101

110

111

T1OUT(a)

V.35

V.11

V.28

V.11

High-Z

TxD(a)

T1OUT(b)

V.35

V.11

High-Z

V.11

High-Z

TxD(b)

T2OUT(a)

V.35

V.11

V.28

V.11

High-Z

TxCE(a)

T2OUT(b)

V.35

V.11

High-Z

V.11

High-Z

TxCE(b)

T3OUT(a)

V.35

V.11

V.28

V.11

High-Z

TxC_DCE(a)

T3OUT(b)

V.35

V.11

High-Z

V.11

High-Z

TxC_DCE(b)

T4OUT(a)

V.28

V.11

V.28

V.11

High-Z

RTS(a)

T4OUT(b)

High-Z

V.11

High-Z

V.11

High-Z

RTS(b)

T5OUT(a)

V.28

V.11

V.28

V.10

V.11

High-Z

DTR(a)

T5OUT(b)

High-Z

V.11

High-Z

V.10

V.11

High-Z

DTR(b)

T6OUT(a)

V.28

V.11

V.28

V.11

High-Z

DCD_DCE(a)

T6OUT(b)

High-Z

V.11

High-Z

V.11

High-Z

DCD_DCE(b)

T7OUT(a)

V.28

V.10

V.28

V.10

High-Z

T8OUT(a)

V.28

V.10

V.28

V.10

High-Z

TABLE 3

Receiver

V.35

EIA-530

RS-232

EIA-530A

RS-449

X.21

Suggested

Input Pin

Mode

Mode (V.28)

Mode

mode (v.36) Mode (v.11)

Shutdown

Signal

MODE (D0,D1,D2)

001

010

011

100

101

110

111

R1IN(a)

V.35

V.11

V.28

V.11

High-Z

RxD(a)

R1IN(b)

V.35

V.11

High-Z

V.11

High-Z

RxD(b)

R2IN(a)

V.35

V.11

V.28

V.11

High-Z

RxC(a)

R2IN(b)

V.35

V.11

High-Z

V.11

High-Z

RxC(b)

R3IN(a)

V.35

V.11

V.28

V.11

High-Z

TxC_DTE(a)

R3IN(b)

V.35

V.11

High-Z

V.11

High-Z

TxC_DTE(b)

R4IN(a)

V.28

V.11

V.28

V.11

High-Z

CTS(a)

R4IN(b)

High-Z

V.11

High-Z

V.11

High-Z

CTS(b)

R5IN(a)

V.28

V.11

V.28

V.10

V.11

High-Z

DSR(a)

R5IN(b)

High-Z

V.11

High-Z

V.10

V.11

High-Z

DSR(b)

R6IN(a)

V.28

V.11

V.28

V.11

High-Z

DCD_DTE(a)

R6IN(b)

High-Z

V.11

High-Z

V.11

High-Z

DCD_DTE(b)

R7IN(a)

V.28

V.10

V.28

V.10

High-Z

R8IN(a)

V.28

V.10

V.28

V.10

High-Z

rev. 7/7/03

SP508 Evaluation Board Manual

Recommended Equipment

· Oscilloscope

· Digital multimeter

· Signal Generator capable of >40MHz

· Communications Analyzer (such as

Firebird 6000)

Parametric Evaluation

Located on the board are two pins identified
as V

and SIGNAL GND. Connect V

a +5V DC supply. If possible limit the supply
current to 0.5 to 1.0 Amps. Be sure to have
power off when connecting the supply to the
board.

SP508 Decoder

The SP508 uses a 3 bit decoder to desig-
nate the protocol selected. There is also a
decoder latch pin available. Table 2 and
Table 3 show the decoder modes for the
driver and receiver. Upon power up the
latch pin needs to be in a transparent state
(logic low or floating) or the SP508 will be in
an unknown state. Note that D0, D1, and D2
set as logic high will put the device shut-
down overriding all individual enable/dis-
able lines and the drivers outputs and re-
ceiver inputs will tri-state. In shutdown
mode the termination resistors also discon-
nect.

Driver Evaluation

Each driver has an internal pull-up so that it
is in a defined state when the input is open.

Connect a system clock or a signal genera-
tor with a TTL-level output and the appropri-
ate frequency within the acceptable range
of the driver under test to driver input you
wish to evaluate. There is an individual
enable line for each driver that can be used
to tri-state the driver. Each enable line has
an internal pull up or pull down insure the
driver is enabled if the enable pin is not
connected or floating. Set the appropriate
DIP switch to the "OFF" position to enable
the driver under test. Once the power is on

USING THE EVALUATION BOARD

and the driver input receives a signal, the
driver outputs can be analyzed with an
oscilloscope or a digital multimeter. Mode
selection can be performed at any time by
changing the state of the DIP switches for
the 3 bit decoder. The appropriate termina-
tion for the driver under test can be added to
driver output and tied to the ground buss.

Receiver Evaluation

The SP508 receivers have internal termina-
tion appropriate for V.35 and RS-422 modes
(refer to the SP508 data sheet for more
detail on the receiver termination). The is
activated when the receiver is set to act as a
V.11 receiver (see Table 3) and the
TERM_OFF pin is logic "0". Each receiver
has a fail-safe feature than outputs a logic
"1" when the receiver in open, terminated
but open, or shorted together. There is an
individual enable line for each receiver that
can be used to tri-state the driver. Each
enable line has an internal pull up or pull
down to insure the receiver is enabled if the
enable pin is not connected or floating. Set
the appropriate DIP switch to the "OFF"
position to enable the receiver under test. As
with the drivers the mode selection can be
performed at any time after power up by
changing the state of the 3 bit decoder. To
evaluate the receiver the appropriate input
signal needs to be applied. To accomplish
this provide a signal from an external source
or use the SP508 driver output and jumper it
to the receiver input. For single ended re-
ceivers tie the active driver output to the
active receiver input. For differential drivers
tie the "A" driver output to the "A" receiver
input and the "B" driver output to the "B"
receiver input. Using the TTL signal on the
driver input will allow the analysis receiver
levels and timing characteristics. The DIP
switches on the right hand side also provide
a means of evaluating the TxC and RRT
receivers by tying the ST and RRC drivers to
the appropriate receivers eliminating the
need for jumper wires.

rev. 7/7/03

SP508 Evaluation Board Manual

Driver Receiver Remote Loopback.

The following example uses the ST driver
looped back into the TxC receiver, using the
3 bit decoder configure the SP508 for the
desired protocol. Connect a jumper cable
between the ST(a) pin and the TxC(a) pin. If
your mode select is for a differential driver/
receiver, then also connect a jumper cable
between the ST(b) pin and the TxC(b) pin.
next connect a signal generator to the ST
input pin. The signal generator output must
be a TTL-level output at a frequency within
the acceptable range of the driver mode
under test. Be sure that the STEN and the
TxCEN DIP switches are set to enable the
ST driver and TxC receiver and that the DIP
switches tying the ST driver to the TxC
receiver are off (refer to section 5.0 Dip
switch guide). The driver outputs are now
connected back to the receiver inputs so
that the driver input to receiver output can
be examined. This configuration is similar
for the other drivers.

Driver Receiver Local Loopback

The SP508 has the ability to provide an
internal loopback. This feature is invoked by
a logic "0" on the LOOPBACK pin. The
driver input and receiver output characteris-
tics adhere to the appropriate specifications
outlined in the data sheet under loopback
conditions. The LOOPBACK pin has in in-
ternal pull-up resistor so that the SP508
defaults to normal operation during power-
up or if the pin is left floating.

DCE DTE selectable configuration

· Configure the decoder for the desired

mode.

· The SP508 evaluation board has dip

switches setup to allow for the evaluation
of a selectable DCE DTE configuration.

· Switch the STEN and RRCEN to the ON

position. This will disable the ST and RRC
driver outputs. (Refer to the DIP switch
guide on Page 8)

· Switch the <TxCEN> and <RRTEN>

switches to the ON position. This will dis-
able the TxC and RRT receiver inputs.
(Refer to the DIP switch guide on Page 8)

· Switch the ST(A), ST(B), TxC(A), and

TxC(B) switches to the ON position. This
ties the ST driver outputs to the TxC Re-
ceiver inputs.

· Switch the RRC(A), RRC(B), RRT(A), and

RRT(B) switches to the ON position. This
ties the RRC driver outputs to the RRC
receiver inputs.

· To enable a DTE configuration switch the

STEN and RRCEN switch to the OFF
position. Be sure the TxC and RRT receiv-
ers are disabled by switching the TxCEN
and RRTEN switches to the ON position.
(Refer to the DIP switch guide on Page 8)

· To enable a DCE configuration switch the

TxCEN and RRTEN to the OFF position.
Be sure to disable the ST and RRC driver
outputs by switching the STEN and RRCEN
switches to the ON position. (Refer to the
DIP switch guide on Page 8)

System Level Evaluation

· The DB-25 Connect if configured as a DTE

for EIA-530 pinout. In order to connect
other DCE equipment or network analyz-
ers ( i.e. the TTC Firebird 6000A), the RxC
receiver output must looped back into the
TxCE driver input. The RxD output can
also be looped back to the TxD input.

· If connecting the evaluation board to a

microcontroller such as the Motorola
MC68360, jumper wires of the driver in-
puts and receiver outputs must connect to
the

C's appropriate pins.

USING THE EVALUATION BOARD: continued

rev. 7/7/03

SP508 Evaluation Board Manual

Driver Enable Dip Switch
(off = logic 1, on = logic 0)

The individual switches in the off position
leaves the individual enable pin floating (in-
ternally pulled up or down?) which enables
the driver. The switch in the on position ties
the high true enable pins to ground and the
low true enable pin (LLEN) to V

thereby

disabling the individual drivers.

Receiver Enable Dip Switch
(off = logic 0, on = logic 1)

The individual switches in the off position
leaves the individual enable pins floating
(internally pulled down or up?) which en-
ables the receiver. The switch in the on
position ties all of the enable pins to V

even the high true TMEN. The TMEN pin is
always high no matter what position the dip
switch is in. To disable the TM receiver the

DIP SWITCH USERS GUIDE

SP508 DIP SWITCH TRUTH TABLE

Switch

ON LOGIC

OFF LOGIC

DECODER

LOOPBACK

Logic 0 indicates SP508 is in LOOPBACK mode

TERM_OFF

Logic 1 internal termination is disables

D_LATCH

Logic 0 Latch is disabled

SDEN

Logic 1 TXD driver is enabled

TTEN

Logic 1 TXCE driver is enabled

STEN

Logic 1 ST driver is enabled

RSEN

Logic 1 RTS driver is enabled

TREN

Logic 1 DTR driver is enabled

RRCEN

Logic 1 DCD_DCE driver is enabled

RLEN

Logic 1 SD driver is enabled

LLEN

Logic 0 LL driver is enabled

RDEN

Logic 0 RXD receiver is enabled

RTEN

Logic 0 RXT receiver is enabled

TXCEN

Logic 0 TXC receiver is enabled

CSEN

Logic 0 CTS receiver is enabled

DMEN

Logic 0 DSR receiver is enabled

RRTEN

Logic 0 DCD_DTE receiver is enabled

ICEN

Logic 0 RI receiver is enabled

TMEN

Logic 1 TM receiver is enabled

DIP switch

must be off and the external pin

labeled TMEN is to be jumped to ground.

Decoder DIP Switch
(off = logic 1, on = logic 0)

The decoder DIP switch is configured such
that the switch in the off position allows the
decoder pins to float as well as the
notLOOPBACK pin. (all of these pins are
assumed to have internal pull-ups.) The dip
switch in the on position grounds each of
these pins.

DCE_DTE Selectable Switches

· Switch bank 1 ON = ST driver outputs tied

to TxC receiver inputs and also tied to D-
SUB connector for remote evaluation.

· Switch bank 2 ON = RRC driver outputs

tied to RRT receiver inputs and also tied to
D-SUB connector for remote evaluation.

rev. 7/7/03

SP508 Evaluation Board Manual

PIN

Symbol

Description

PIN

Symbol

Description

+5V Power Supply Input

TXC(b)

TXC Non-Inverting Input

GND

Signal Ground

GND

Signal Ground

SDEN

TxD Driver Enable input

TXC(a)

TXC Inverting Input

TTEN

TXCE Driver Enable Input

CS(b)

CTS Non-Inverting Input

STEN

ST Driver Enable Input

CS(a)

CTS Inverting Input

RSEN

RTS Driver Enable Input

DM(b)

DSR Non-Inverting Input

TREN

DTR Driver Enable Input

DM(a)

DSR Inverting Input

RRCEN

DCDDCE Driver Enable Input

V10GND

V.10 Rx Reference Node

RLEN

RL Driver Enable Input

RRT(b)

DCDDTE Non-Inverting Input

LLEN*

LL Driver Enable Input

RRT(a)

DCDDTE Inverting Input

RDEN*

RxD Receiver Enable Input

IC(a)

RI Receiver Input

RTEN*

RxT Receiver Enable Input

TM(a)

TM Receiver Input

TxCEN*

TxC Receiver Enable Input

LL(a)

LL Driver Output

CSEN*

CTS Receiver Enable Input

+5V Power Supply Input'

DMEN*

DSR Receiver Enable Input

RL(a)

RL Driver Output

RRTEN*

DCDDTE Receiver Enable Input

Vss

-2xV

Charge pump Output

ICEN*

RI Receiver Enable Input

C2-

Charge pump Capacitor

TMEN

TM Receiver Enable Input

GND

Signal Ground

Mode Select Input

C1-

Charge pump Capacitor

Mode Select Input

C2+

Charge pump Capacitor

Mode Select Input

+5V Power Supply Input

TERM_OFF

Termination Disable Input

C1+

Charge pump Capacitor

D_LATCH*

Decoder Latch Input

Vdd

2xVxx Charge Pump Output

N/C

No Connection

GND

Signal Ground

GND

Signal Ground

TR(a)

DTR Inverting Output

+5V Power Supply Input

N/C

No Connection

LOOPBACK* Loopback Mode Enable Input

+5V Power Supply Input

TXD

TXD Driver TTL Input

TR(b)

DTR Non-Inverting Output

TxCE

TXCE Driver TTL Input

RRC(b)

DCDDCE Non-Inverting Output

ST Driver TTL Input

+5V Power Supply Input

DTR

RTS Driver TTL Input

RRC(a)

DCDDCE Inverting Output

RTS

DTR Driver TTL Input

GND

Signal Ground

DCD_DCE

DCDDCE Driver TTL Input

RS(a)

RTS Inverting Output

RL Driver TTL Input

+5V Power Supply Input

LL Driver TTL Input

RS(b)

RTS Non-Inverting Output

RXD

RXD Receiver TTL Output

GND

Signal Ground

RXC

RXC Receiver TTL Output

ST(a)

ST Inverting Output

TXC

TXC Receiver TL Output

+5V Power Supply Input

CTS

CTS Receiver TTL Output

V35TGND3

ST Termination Reference

DSR

DSR Receiver TTL Output

ST(b)

ST Non-Inverting Output

DCD_DTE

DCDDTE Receiver TTL Output

GND

Signal Ground

RI Receiver TTL Output

TT(a)

TXCE Inverting Output

TM Receiver TTL Output

+5V Power Supply Input

GND

Signal Ground

V35TGND2

TXCE Termination Reference

+5V Power Supply Input

TT(b)

TXCE Non-Inverting Output

V35RGND

Receiver Termination Reference

GND

Signal Ground

RD(b)

RXD Non-inverting Input

SD(a)

TXD Inverting Output

RD(a)

RXD Inverting Input

+5V Power Supply Input

RT(b)

RXT Non-Inverting Input

V35TGND1

TXD Termination Reference

RT(a)

RXT Inverting Input

100

SD(b)

TXD Non-Inverting Output

Note:N/C Pins should be left floating as internal signals may be present.
Ensure all V

and ground connections are made before operating device.

SP508 PIN ASSIGNMENTS

rev. 7/7/03

SP508 Evaluation Board Manual

Model

Package

SP508CF ........................................................................................................................ 100-pin JEDEC LQFP
SP508CB ....................................................................................................................................... 132-pin BGA
SP508CEB ................................................................................................................. SP508 Evaluation Board

ORDERING INFORMATION

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600

Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com

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