Date: 8/19/04

FEATURES

20Mbps Differential Transmission Rates

15kV ESD Tolerance for Analog I/Os

Internal Transceiver Termination Resistors

for V.11/V.35

Interface Modes:

RS-232 (V.28)

EIA-530 (V.10 & V.11)

X.21 (V.11)

EIA-530A (V.10 & V.11)

RS-449/V.36

V.35

(V.10 & V.11)

Software Selectable Protocols with 3-Bit Word

Eight Drivers and Eight Receivers

V.35/V.11 Receiver Termination Network

Disable Option

Internal Line or Digital Loopback Testing

Adheres to NET1/NET2 and TBR-2 Requirements

SP508

Rugged 20Mbps, 8 Channel Multi-Protocol Transceiver

with Programmable DCE/DTE and Termination Resistors

DESCRIPTION

The SP508 is a monolithic device that supports eight (8) popular serial interface standards for
Wide Area Network (WAN) connectivity. The SP508 is fabricated using a low power BiCMOS
process technology, and incorporates a Sipex regulated charge pump allowing +5V only
operation. Sipex's patented charge pump provides a regulated output of +5.8V, which will
provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8)
receivers can be configured via software for any of the above interface modes at any time. The
SP508 requires no additional external components for compliant operation for all of the eight
(8) modes of operation other than four capacitors used for the internal charge pump. All
necessary termination is integrated within the SP508 and is switchable when V.35 drivers and
V.35 receivers, or when V.11 receivers are used. The SP508 provides the controls and
transceiver availability for operating as either a DTE or DCE.

Additional features with the SP508 include internal loopback that can be initiated in any of the
operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are
internally connected to driver inputs creating an internal signal path bypassing the serial
communications controller for diagnostic testing. The SP508 also includes a latch enable pin
with the driver and receiver address decoder. The internal V.11 or V.35 receiver termination
can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8)
drivers and receivers in the SP508 include separate enable pins for added convenience. The
SP508 is ideal for WAN serial ports in networking equipment such as routers, access
concentrators, network muxes, DSU/CSU's, networking test equipment, and other access
devices.

Applicable U.S. Patents-5,306,954; and others patents pending

APPLICATIONS

Router

Frame Relay

CSU

DSU

PBX

Secure Communication Terminals

Easy Flow-Through Pinout

+5V Only Operation

Individual Driver/Receiver Enable/Disable Controls

Operates in DTE or DCE Mode

Now Available in Lead Free Packaging

Refer to page 7 for pinout

Date: 8/19/04

= 0

C to +70

C and V

= +4.75V to +5.25V unless otherwise noted. The

denotes the specifications which applies to full

temperature range of -40

C to =+85

C, unless otherwise specified.

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

LOGIC INPUTS

0.8

Volts

2.0

Volts

LOGIC OUTPUTS

0.4

Volts

OUT

= 3.2mA

2.4

Volts

OUT

= 1.0mA

V.28 DRIVER

DC Parameters
Outputs

Open Circuit Voltage

Volts

per Figure 1

Loaded Voltage

5.0

Volts

per Figure 2

Short-Circuit Current

100

per Figure 4, V

OUT

=0V

Power-Off Impedance

300

per Figure 5

AC Parameters

= +5V for AC parameters

Outputs

Transition Time

1.5

per Figure 6; +3V to -3V

Instantaneous Slew Rate

per Figure 3

Propagation Delay
t

PHL

0.5

PLH

0.5

Max.Transmission Rate

120

230

kbps

V.28 RECEIVER

DC Parameters
Inputs

Input Impedance

per Figure 7

Open-Circuit Bias

+2.0

Volts

per Figure 8

HIGH Threshold

1.7

3.0

Volts

LOW Threshold

0.8

1.2

Volts

AC Parameters

= +5V for AC parameters

Propagation Delay

PHL

100

500

PLH

100

500

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the
device at these ratings or any other above those indicated in the
operation sections of the specifications below is not implied.
Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.

................................................................................................ +7V

Input Voltages:

Logic ................................................ -0.3V to (V

+0.5V)

Drivers ............................................. -0.3V to (V

+0.5V)

Receivers ...........................................................

15.5V

Output Voltages:

Logic ................................................ -0.3V to (V

+0.5V)

Drivers ...................................................................

12V

Receivers ........................................ -0.3V to (V

+0.5V)

Storage Temperature ................................................ -65

C to +150

Power Dissipation ................................................................. 1520mW
(derate 19.0mW/

C above +70

Package Derating:

.................................................................................................................

52.7

C/W

....................................................................................................................

6.5

C/W

STORAGE CONSIDERATIONS

Due to the relatively large package size, storage in a low
humidity environment is preferred. Large high density plastic
packages are moisture sensitive and should be stored in Dry
Vapor Barrier Bags. Prior to usage, the parts should remain
bagged and stored below 40

C and 60%RH. If the parts are

removed from the bag, they should be used within 48 hours or
stored in an environment at or below 20%RH. If the above
conditions cannot be followed, the parts should be baked for
four hours at 125

C in order to remove moisture prior to

soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier
Bags with a humidity indicator card and desiccant pack. The
humidity indicator should be below 30%RH.

ELECTRICAL SPECIFICATIONS

Date: 8/19/04

V.28 RECEIVER (cont

)

AC Parameters (cont.)

Max.Transmission Rate

120

235

kbps

V.10 DRIVER

DC Parameters
Outputs

Open Circuit Voltage

4.0

6.0

Volts

per Figure 9

Test-Terminated Voltage

0.9V

Volts

per Figure 10

Short-Circuit Current

150

per Figure 11

Power-Off Current

100

per Figure 12

AC Parameters

= +5V for AC parameters

Outputs

Transition Time

200

per Figure 13; 10% to 90%

Propagation Delay
t

PHL

100

500

PLH

100

500

Max.Transmission Rate

120

kbps

V.10 RECEIVER

DC Parameters
Inputs

Input Current

3.25

+3.25

per Figures 14 and 15

Input Impedance

Sensitivity

0.3

Volts

AC Parameters

= +5V for AC parameters

Propagation Delay

PHL

PLH

Max.Transmission Rate

120

kbps

V.11 DRIVER

DC Parameters
Outputs

Open Circuit Voltage

6.0

Volts

per Figure 16

Test Terminated Voltage

2.0

Volts

per Figure 17

0.5V

0.67V

Volts

Balance

0.4

Volts

per Figure 17

Offset

+3.0

Volts

per Figure 17

Short-Circuit Current

150

per Figure 18

Power-Off Current

100

per Figure 19

AC Parameters

= +5V for AC parameters

Outputs

Transition Time

per Fig. 21 and 36; 10% to 90%

Propagation Delay

Using C

= 50pF;

PHL

per Figures 33 and 36

PLH

per Figures 33 and 36

Differential Skew

per Figures 33 and 36

(|t

phl

-t

plh

Max.Transmission Rate

Mbps

Channel to Channel Skew

V.11 RECEIVER

DC Parameters
Inputs

Common Mode Range

Volts

Sensitivity

0.2

Volts

= 0

C to +70

C and V

= +4.75V to +5.25V unless otherwise noted. The

denotes the specifications which applies to full temperature

range of -40

C to =+85

C, unless otherwise specified.

PARAMETER

MIN.

TYP.

MAX. UNITS CONDITIONS

ELECTRICAL SPECIFICATIONS

Date: 8/19/04

= 0

C to +70

C and V

= +4.75V to +5.25V unless otherwise noted. The

denotes the specifications which applies to full temperature

range of -40

C to =+85

C, unless otherwise specified.

PARAMETER

MIN.

TYP.

MAX. UNITS CONDITIONS

V.11 RECEIVER (cont)

DC Parameters (cont.)
Input Current

3.25

per Figure 20 and 22;
power on or off

Current w/ 100

Termination

60.75

per Figure 23 and 24

Input Impedance

AC Parameters

= +5V for AC parameters

Propagation Delay

Using C

= 50pF;

PHL

per Figures 33 and 38

PLH

per Figures 33 and 38

Skew(|t

phl

-t

plh

per Figure 33

Max.Transmission Rate

Mbps

Channel to Channel Skew

V.35 DRIVER

DC Parameters
Outputs

Test Terminated Voltage

0.44

0.66

Volts

per Figure 25

Offset

0.6

Volts

per Figure 25

Output Overshoot

-0.2V

+0.2V

Volts

per Figure 25; V

ST = Steady state value

Source Impedance

150

per Figure 27; Z

= V

x 50

Short-Circuit Impedance

135

165

per Figure 28

AC Parameters

= +5V for AC parameters

Outputs

Transition Time

per Figure 29; 10% to 90%

Propagation Delay
t

PHL

per Figure 33 and 36; C

= 20pF

PLH

per Figure 33 and 36; C

= 20pF

Differential Skew

per Figure 33 and 36; C

= 20pF

(|t

phl

-t

plh

Max.Transmission Rate

Mbps

Channel to Channel Skew

V.35 RECEIVER

DC Parameters
Inputs

Sensitivity

+200

Source Impedance

110

per Figure 30; Z

= V

x 50

Short-Circuit Impedance

135

165

per Figure 31

AC Parameters

= +5V for AC parameters

Propagation Delay
t

PHL

per Figure 33 and 38; C

= 20pF

PLH

per Figure 33 and 38; C

= 20pF

Skew(|t

phl

-t

plh

per Figure 33; C

= 20pF

Max.Transmission Rate

Mbps

Channel to Channel Skew

TRANSCEIVER LEAKAGE CURRENT

Driver Output 3-State Current

500

per Figure 32; Drivers disabled

Rcvr Output 3-State Current

& R

disabled, 0.4V - V

- 2.4V

POWER REQUIREMENTS

4.75

5.00

5.25

Volts

(Shutdown Mode)

All I

values are with V

= +5V

(V.28/RS-232)

= 120kbps; Drivers active & loaded

(V.11/RS-422)

230

= 10Mbps; Drivers active & loaded

(EIA-530 & RS-449)

270

= 10Mbps; Drivers active & loaded

(V.35)

170

V.35 @ f

= 10Mbps, V.28 @ 20kbps

(EIA-530A)

200

= 10Mbps; Drivers active & loaded

ELECTRICAL SPECIFICATIONS

Date: 8/19/04

= +25

C and V

= +5.0V unless otherwise noted.

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE

RS-232/V.28
t

PZL

; Tri-state to Output LOW

0.11

5.0

= 100pF, Fig. 34 & 40; S

closed

PZH

; Tri-state to Output HIGH

0.11

2.0

= 100pF, Fig. 34 & 40; S

closed

PLZ

; Output LOW to Tri-state

0.05

2.0

= 100pF, Fig. 34 & 40; S

closed

PHZ

; Output HIGH to Tri-state

0.05

2.0

= 100pF, Fig. 34 & 40; S

closed

RS-423/V.10
t

PZL

; Tri-state to Output LOW

0.07

2.0

= 100pF, Fig. 34 & 40; S

closed

PZH

; Tri-state to Output HIGH

0.05

2.0

= 100pF, Fig. 34 & 40; S

closed

PLZ

; Output LOW to Tri-state

0.55

2.0

= 100pF, Fig. 34 & 40; S

closed

PHZ

; Output HIGH to Tri-state

0.12

2.0

= 100pF, Fig. 34 & 40; S

closed

RS-422/V.11
t

PZL

; Tri-state to Output LOW

0.04

10.0

= 100pF, Fig. 34 & 37; S

closed

PZH

; Tri-state to Output HIGH

0.05

2.0

= 100pF, Fig. 34 & 37; S

closed

PLZ

; Output LOW to Tri-state

0.03

2.0

= 15pF, Fig. 34 & 37; S

closed

PHZ

; Output HIGH to Tri-state

0.11

2.0

= 15pF, Fig. 34 & 37; S

closed

V.35
t

PZL

; Tri-state to Output LOW

0.85

10.0

= 100pF, Fig. 34 & 37; S

closed

PZH

; Tri-state to Output HIGH

0.36

2.0

= 100pF, Fig. 34 & 37; S

closed

PLZ

; Output LOW to Tri-state

0.06

2.0

= 15pF, Fig. 34 & 37; S

closed

PHZ

; Output HIGH to Tri-state

0.05

2.0

= 15pF, Fig. 34 & 37; S

closed

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE

RS-232/V.28
t

PZL

; Tri-state to Output LOW

0.05

2.0

= 100pF, Fig. 35 & 40; S

closed

PZH

; Tri-state to Output HIGH

0.05

2.0

= 100pF, Fig. 35 & 40; S

closed

PLZ

; Output LOW to Tri-state

0.65

2.0

= 100pF, Fig. 35 & 40; S

closed

PHZ

; Output HIGH to Tri-state

0.65

2.0

= 100pF, Fig. 35 & 40; S

closed

RS-423/V.10
t

PZL

; Tri-state to Output LOW

0.04

2.0

= 100pF, Fig. 35 & 40; S

closed

PZH

; Tri-state to Output HIGH

0.03

2.0

= 100pF, Fig. 35 & 40; S

closed

PLZ

; Output LOW to Tri-state

0.03

2.0

= 100pF, Fig. 35 & 40; S

closed

PHZ

; Output HIGH to Tri-state

0.03

2.0

= 100pF, Fig. 35 & 40; S

closed

OTHER AC CHARACTERISTICS

Date: 8/19/04

= +25

C and V

= +5.0V unless otherwise noted.

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

RS-422/V.11
t

PZL

; Tri-state to Output LOW

0.04

2.0

= 100pF, Fig. 35 & 39; S

closed

PZH

; Tri-state to Output HIGH

0.03

2.0

= 100pF, Fig. 35 & 39; S

closed

PLZ

; Output LOW to Tri-state

0.03

2.0

= 15pF, Fig. 35 & 39; S

closed

PHZ

; Output HIGH to Tri-state

0.03

2.0

= 15pF, Fig. 35 & 39; S

V.35
t

PZL

; Tri-state to Output LOW

0.04

2.0

= 100pF, Fig. 35 & 39; S

closed

PZH

; Tri-state to Output HIGH

0.03

2.0

= 100pF, Fig. 35 & 39; S

closed

PLZ

; Output LOW to Tri-state

0.03

2.0

= 15pF, Fig. 35 & 39; S

closed

PHZ

; Output HIGH to Tri-state

0.03

2.0

= 15pF, Fig. 35 & 39; S

closed

TRANSCEIVER TO TRANSCEIVER SKEW

(per Figures 32, 33, 36, 38)

RS-232 Driver

100

[ (t

phl

)

Tx1

phl

)

Txn

]

100

[ (t

plh

)

Tx1

plh

)

Txn

]

RS-232 Receiver

[ (t

phl

)

Rx1

phl

)

Rxn

]

[ (t

phl

)

Rx1

phl

)

Rxn

]

RS-422 Driver

[ (t

phl

)

Tx1

phl

)

Txn

]

[ (t

plh

)

Tx1

plh

)

Txn

]

RS-422 Receiver

[ (t

phl

)

Rx1

phl

)

Rxn

]

[ (t

phl

)

Rx1

phl

)

Rxn

]

RS-423 Driver

[ (t

phl

)

Tx2

phl

)

Txn

]

[ (t

plh

)

Tx2

plh

)

Txn

]

RS-423 Receiver

[ (t

phl

)

Rx2

phl

)

Rxn

]

[ (t

phl

)

Rx2

phl

)

Rxn

]

V.35 Driver

[ (t

phl

)

Tx1

phl

)

Txn

]

[ (t

plh

)

Tx1

plh

)

Txn

]

V.35 Receiver

[ (t

phl

)

Rx1

phl

)

Rxn

]

[ (t

phl

)

Rx1

phl

)

Rxn

]

OTHER AC CHARACTERISTICS

(Continued)

Date: 8/19/04

VCC 1

GND

SDEN

TTEN 4

STEN

RSEN 6

TREN 7

RRCEN 8

RLEN 9

LLEN 10

RDEN 11

RTEN 12

TXCEN 13

CSEN 14

DMEN15

RRTEN 16

ICEN 17

TMEN 18

D0 19

D1 20

D2 21

TERM_OFF 22

D_LATCH 23

N/C 24

GND 25

VCC 26

LOOPBA

CK 27

TXD 28

TXCE 29

ST 30

DTR 32

DCD_DCE 33

RL 34

RXD 36

RXC 37

TXC 38

CTS 39

DSR 40

DCD_DTE 41

RI 42

TM 43

GND 44

VCC 45

V35RGND 46

RD(b) 47

RD(a) 48

T(b) 49

T(a) 50

75 TR(a)

74 GND

73 VDD

72 C1+

71 VCC

70 C2+

69 C1-

68 GND

67 C2-

66 VSS

65 RL(a)

64 VCC

63 LL(a)

62 TM(a)

61 IC(a)

60 RRT(a)

59 RRT(b)

58 V10GND

57 DM(a)

56 DM(b)

55 CS(a)

54 CS(b)

53 TXC(a)

52 GND

51 TXC(b)

100 SD(b)

V35TGND1

VCC

97 SD(a)

96 GND

TT(b)

V35TGND2

VCC

TT(a)

91 GND

90 ST(b)

V35TGND3

VCC

87 ST(a)

86 GND

85 RS(b)

VCC

83 RS(a)

82 GND

81 RRC(a)

VCC

79 RRC(b)

78 TR(b)

VCC

76 N/C

SP508

PINOUT 100 PIN LQFP

Date: 8/19/04

PIN DESCRIPTION

Pin Number

Pin Name

Description

Pin Number

Pin Name

Description

VCC

5V Power Supply Input

TxC(b)

TxC Non-Inverting Input

GND

Signal Ground

GND

Signal Ground

SDEN

TxD Driver Enable Input

TxC(a)

TxC Inverting Input

TTEN

TxCE Driver Enable Input

CS(b)

CTS Non-Inverting Input

STEN

ST Driver Enable Input

CS(a)

CTS Inverting Input

RSEN

RTS Driver Enable Input

DM(b)

DSR Non-Inverting Input

TREN

DTR Driver Enable Input

DM(a)

DSR Inverting Input

RRCEN

DCD Driver Enable Input

GNDV10

V.10 Rx Reference Node

RLEN

RL Driver Enable Input

RRT(b)

DCD

DTE

Non-Inverting Input

LLEN#

LL Driver Enable Input

RRT(a)

DCD

DTE

Inverting Input

RDEN#

RxD Receiver Enable Input

RI Receiver Input

RTEN#

RxC Receiver Enable Input

TM(a)

TM Receiver Input

TxCEN#

TxC Receiver Enable Input

LL(a)

LL Driver Output

CSEN#

CTS Receiver Enable Input

VCC

Power Supply Input

DMEN#

DSR Receiver Enable Input

RL(a)

RL Driver Output

RRTEN#

DCD

DTE

Receiver Enable Input

VSS1

-2xVCC Charge Pump Output

ICEN#

RI Receiver Enable Input

C2N

Charge Pump Capacitor

TMEN

TM Receiver Enable Input

GND

Signal Ground

Mode Select Input

C1N

Charge Pump Capacitor

Mode Select Input

C2P

Charge Pump Capacitor

Mode Select Input

VCC

Power Supply Input

TERM_OFF Termination Disable Input

C1P

Charge Pump Capacitor

D_LATCH#

Decoder Latch Input

VDD

2xVCC Charge Pump Output

No Connect

GND

Signal Ground

GND

Signal Ground

TR(a)

DTR Inverting Output

VCC

5V Power Supply Input

No Connect

LOOPBACK# Loopback Mode Enable Input

VCC

Power Supply Input

TxD

TxD Driver TTL Input

TR(b)

DTR Non-Inverting Output

TxCE

TxCE Driver TTL Input

RRC(b)

DCD Non-Inverting Output

ST Driver TTL Input

VCC

Power Supply Input

RTS

RTS Driver TTL Input

RRC(a)

DCD Inverting Output

DTR

DTR Driver TTL Input

GND

Signal Ground

DCD_DCE

DCD

DCE

Driver TTL Input

RS(a)

RTS Inverting Output

RL Driver TTL Input

VCC

Power Supply Input

LL Driver TTL Input

RS(b)

RTS Non-Inverting Output

RxD

RxD Receiver TTL Output

GND

Signal Ground

RxC

RxC Receiver TTLOutput

ST(a)

ST Inverting Output

TxC

TxC Receiver TTL Output

VCC

Power Supply Input

CTS

CTS Receiver TTL Output

V35TGND3 ST Termination Referance

DSR

DSR Receiver TTL Output

ST(b)

ST Non-Inverting Output

DCD_DTE

DCD

DTE

Receiver TTL Output

GND

Signal Ground

RI Receiver TTL Output

TT(a)

TxCE Inverting Output

TM Receiver TTL Output

VCC

5V Power Supply Input

GND

Signal Ground

V35TGND2 ST Termination Referance

VCC

Power Supply Input

TT(b)

TxCE Non-Inverting Output

46 V35RGND Reciever Termination Refrence

GND

Signal Ground

RD(b)

RXD Non-Inverting Input

SD(a)

TxD Inverting Output

RD(a)

RXD Inverting Input

VCC

5V Power Supply Input

RT(b)

RxC Non-Inverting Input

V35TGND1 ST Termination Referance

RT(a)

RxC Inverting Input

100

SD(b)

TxD Non-Inverting Output

Date: 8/19/04

SP508 Pin Designation

SP508CF

SP508CB

DESIG

SP508CF

SP508CB

DESIG

VCC

N12

TxC(B)

GND

N13

GND

SDEN

M14

TxC(A)

TTEN

M13

CS(B)

STEN

L14

CS(A)

RSEN

K14

DM(B)

TREN

J14

DM(A)

RRCEN

J12

V10GND

RLEN

H13

RRT(B)

LLEN#

H14

RRT(A)

RDEN#

H12

IC(A)

RTEN#

G12

TM(A)

TxCEN#

G14

LL(A)

CSEN#

G13

VCC

DMEN#

F14

RL(A)

RRTEN#

F13

VSS

ICEN#

F12

C2-

TMEN

E14

GND

E13

C1-

D14

C2+

D13

VCC

TERM_OFF

C14

C1+

D_LATCH#

B14

VDD

N/C

A14

GND

A13

TR(A)

VCC

LOOPBACK#

A12

VCC

TxD

B12

TR(B)

TxCE

C12

RRC(A)

B11

VCC

RTS

A11

RRC(A)

DTR

C11

GND

DCD_DCE

B10

RS(A)

A10

VCC

C10

RS(B)

RxD

GND

RxC

ST(A)

TxC

VCC

CTS

V35TGND3

DSR

ST(B)

DCD_DTE

GND

TT(A)

VCC

GND

V35TGND2

P10

VCC

TT(B)

N10

V35RGND

GND

M10

RD(B)

SD(A)

P11

RD(A)

VCC

N11

RT(B)

V35TGND1

M11

RT(A)

100

SD(B)

Date: 8/19/04

Table 1. Driver Mode Selection

Table 2. Receiver Mode Selection

SP508 Driver Table

SP508 Receiver Table

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

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Date: 8/19/04

Figure 34. Driver Timing Test Load Circuit

Figure 35. Receiver Timing Test Load Circuit

Figure 36. Driver Propagation Delays

Figure 37. Driver Enable and Disable Times

Figure 38. Receiver Propagation Delays

500

Output

Under

Test

Receiver

Output

Test Point

+3V

DRIVER

INPUT

DRIVER

OUTPUT

DIFFERENTIAL

OUTPUT

1.5V

PLH

f > 10MHz; t

< 10ns; t

< 10ns

1/2V

PHL

DPLH

DPHL

SKEW =

DPLH -

DPHL

+3V

A, B

1.5V

A, B

2.3V

0.5V

Output normally LOW

Output normally HIGH

Mx or Tx_Enable

RECEIVER OUT

- V

)/2

- V

)/2

PLH

f > 10MHz; t

< 10ns; t

< 10ns

OUTPUT

0D2

A B

PHL

INPUT

SKEW

= | t

PHL

- t

PLH

Date: 8/19/04

Figure 45. Functional Diagram

TxD

SD(a)

V35TGND1

SD(b)

SDEN

VCC

VDD

C1-

VSS

C1+

+5V

(decoupling capacitor not shown)

Regulated Charge Pump

SP508

TxCE

TT(a)

V35TGND2

TT(b)

TTEN

ST(a)

V35TGND3

ST(b)

STEN

RD(a)

RxD

RDEN

RD(b)

RT(a)

RxC

RTEN

RT(b)

TxC(a)

TxC

TxCEN

TxC(b)

CS(a)

CTS

CSEN

CS(b)

DM(a)

DSR

DMEN

DM(b)

RRT(a)

DCD_DTE

RRTEN

RRT(b)

TM(a)

TMEN

RTS

RS(a)

RS(b)

RSEN

DTR

TR(a)

TR(b)

TREN

DCD_DCE

RRC(a)

RRC(b)

RRCEN

LL(a)

LLEN

C2-

C2+

GND

TERM-OFF

D-LATCH

V.10-GND

V.35 MODE

TX ENABLE

51ohms

124ohms

V.35 DRIVER TERMINATION NETWORK

V.35 MODE

RX ENABLE

51ohms

124ohms

RECEIVER TERMINATION NETWORK

V.11 MODE

RL(a)

RLEN

ICEN

V35RGND

LOOPBACK

46
48

36
11

37
12
49

38
13

39
14
54

40
15

41
16
59

42
17

43
18

28
97
99
100
3

29
92
94
95
4

30
87
89
90
5

31
83

85
6

32
75

78
7

33
81

VCC pins (1, 26, 45, 64, 71, 77, 80, 84, 88, 93, 98)
GND pins (2, 25, 44, 52, 68, 74, 82, 86, 91, 96)
N.C. pins (24 and 76)

Date: 8/19/04

The SP508 contains highly integrated serial
transceivers that offer programmability between
interface modes through software control. The
SP508 offers the hardware interface modes for
RS-232 (V.28), RS-449/V.36 (V.11 and V.10),
EIA-530 (V.11 and V.10), EIA-530A (V.11 and
V.10), V.35 (V.35 and V.28) and X.21(V.11). The
interface mode selection is done via three control
pins, which can be latched via microprocessor
control.

The SP508 has eight drivers, eight receivers, and
Sipex's patented on-board charge pump (5,306,954)
that is ideally suited for wide area network
connectivity and other multi-protocol applications.
Other features include digital and line loopback
modes, individual enable/disable control lines for
each driver and receiver, fail-safe when inputs are
either open or shorted, individual termination
resistor ground paths, separate driver and receiver
ground outputs, enhanced ESD protection on driver
outputs and receiver inputs.

THEORY OF OPERATION

The SP508 device is made up of 1) the drivers, 2)
the receivers, 3) a charge pump, 4) DTE/DCE
switching algorithm, and 5) control logic.

Drivers

The SP508 has eight enhanced independent drivers.
Control for the mode selection is done via a three-
bit control word into D0, D1, and D2. The drivers
are prearranged such that for each mode of
operation, the relative position and functionality
of the drivers are set up to accommodate the
selected interface mode. As the mode of the drivers
is changed, the electrical characteristics will change
to support the required signal levels. The mode of
each driver in the different interface modes that
can be selected is shown in Table 1.

There are four basic types of driver circuits
ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423),
ITU-T-V.11 (RS-422), and CCITT-V.35.

The V.28 (RS-232) drivers output single-ended
signals with a minimum of +5V (with 3k

2500pF loading), and can operate over 120kbps.
Since the SP508 uses a charge pump to generate
the RS-232 output rails, the driver outputs will
never exceed +10V. The V.28 driver architecture
is similar to Sipex's standard line of RS-232
transceivers.

The RS-423 (V.10) drivers are also single-ended
signals which produce open circuit V

and V

measurements of +4.0V to +6.0V. When terminated
with a 450

load to ground, the driver output will

not deviate more than 10% of the open circuit
value. This is in compliance of the ITU V.10
specification. The V.10 (RS-423) drivers are used
in RS-449/V.36, EIA-530, and EIA-530A modes
as Category II signals from each of their
corresponding specifications. The V.10 drivers
are guaranteed to transmit over 120kbps, but can
operate at over 1Mbps if necessary.

The third type of drivers are V.11 (RS-422)
differential drivers. Due to the nature of differential
signaling, the drivers are more immune to noise as
opposed to single-ended transmission methods.
The advantage is evident over high speeds and
long transmission lines. The strength of the driver
outputs can produce differential signals that can
maintain +2V differential output levels with a load
of 100

. The signal levels and drive capability of

these drivers allow the drivers to also support
RS-485 requirements of +1.5V differential output
levels with a 54

load. The strength allows the

SP508 differential driver to drive over long cable
lengths with minimal signal degradation. The V.11
drivers are used in RS-449, EIA-530, EIA-530A
and V.36 modes as Category I signals which are
used for clock and data. Sipex's new driver design
over its predecessors allow the SP508 to operate
over 20Mbps for differential transmission.

FEATURES

Date: 8/19/04

The fourth type of drivers are V.35 differential
drivers. There are only three available on the
SP508 for data and clock (TxD, TxCE, and TxC
in DCE mode). These drivers are current sources
that drive loop current through a differential pair
resulting in a 550mV differential voltage at the
receiver. These drivers also incorporate fixed
termination networks for each driver in order to
set the V

and V

depending on load conditions.

This termination network is basically a "Y"
configuration consisting of two 51

resistors

connected in series and a 124

resistor connected

between the two 50

resistors and a V35TGND

output. Each of the three drivers and its associated
termination will have its own V35TGND output
for grounding convenience. Filtering can be done
on these pins to reduce common mode noise
transmitted over the transmission line by
connecting a capacitor to ground.

The drivers also have separate enable pins
which simplifies half-duplex configurations for
some applications, especially programmable
DTE/DCE. The enable pins will either enable or
disable the output of the drivers according to the
appropriate active logic illustrated on Figure 45.
The enable pins have internal pull-up and pull-
down devices, depending on the active polarity
of the receiver, that enable the driver upon power-
on if the enable lines are left floating. During
disabled conditions, the driver outputs will be at
a high impedance 3-state.

The driver inputs are both TTL or CMOS
compatible. All driver inputs have an internal
pull-up resistor so that the output will be at a
defined state at logic LOW ("0"). Unused driver
inputs can be left floating. The internal pull-up
resistor value is approximately 500k

Receivers

The SP508 has eight enhanced independent
receivers. Control for the mode selection is done
via a three-bit control word that is the same as the
driver control word. Therefore, the modes for
the drivers and receivers are identical in the
application.

Like the drivers, the receivers are prearranged
for the specific requirements of the synchronous
serial interface. As the operating mode of the
receivers is changed, the electrical characteristics
will change to support the required serial interface

protocols of the receivers. Table 2 shows
the mode of each receiver in the different
interface modes that can be selected. There are
two basic types of receiver circuits--ITU-T-V .28
(RS-232) and ITU-T-V.11, (RS-422).

The RS-232 (V.28) receiver is single-ended and
accepts RS-232 signals from the RS-232 driver.
The RS-232 receiver has an operating input
voltage range of +15V and can receive signals
downs to +3V. The input sensitivity complies
with RS-232 and V .28 at +3V. The input
impedance is 3k

to 7k in accordance to RS-

232 and V .28. The receiver output produces a
TTL/CMOS signal with a +2.4V minimum for
a logic "1" and a +0.4V maximum for a logic "0".
The RS-232 (V.28) protocol uses these receivers
for all data, clock and control signals. They are
also used in V.35 mode for control line signals:
CTS, DSR, LL, and RL. The RS-232 receivers
can operate over 120kbps.

The second type of receiver is a differential type
that can be configured internally to support
ITU-T-V.10 and CCITT-V.35 depending on its
input conditions. This receiver has a typical
input impedance of 10k

and a differential

threshold of less than +200mV, which complies
with the ITU-T-V.11 (RS-422) specifications.
V.11 receivers are used in RS-449/V.36,
EIA-530, EIA-530A and X.21 as Category I
signals for receiving clock, data, and some control
line signals not covered by Category II V.10
circuits. The differential V.11 transceiver has
improved architecture that allows over 20Mbps
transmission rates.

Receivers dedicated for data and clock (RxD,
RxC, TxC) incorporate internal termination for
V.11. The termination resistor is typically 120

connected between the A and B inputs. The
termination is essential for minimizing crosstalk
and signal reflection over the transmission line .
The minimum value is guaranteed to exceed
100

, thus complying with the V.11 and RS-422

specifications. This resistor is invoked when the
receiver is operating as a V.11 receiver, in modes
EIA-530, EIA-530A, RS-449/V.36, and X.21.

Date: 8/19/04

The same receivers also incorporate a termination
network internally for V.35 applications. For
V.35, the receiver input termination is a "Y"
termination consisting of two 51

resistors

connected in series and a 124

resistor connected

between the two 50

resistors and V35RGND

output. The V35RGND is usually grounded. The
receiver itself is identical to the V.11 receiver.

The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
1Mbps and are used in RS-449/V.36, E1A-530,
E1A-530A and X.21 modes as Category II signals
as indicated by their corresponding specifications.
All receivers include an enable/disable line for
disabling the receiver output allowing convenient
half-duplex configurations. The enable pins will
either enable or disable the output of the receivers
according to the appropriate active logic
illustrated on Figure 45. The receiver's enable
lines include an internal pull-up or pull-down
device, depending on the active polarity of the
receiver, that enables the receiver upon power up
if the enable lines are left floating. During disabled
conditions, the receiver outputs will be at a high
impedance state. If the receiver is disabled any
associated termination is also disconnected from
the inputs.

All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
are internal 5k

pull-down resistors on the inputs

which produces a logic high ("1") at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH ("1")
at the receiver output.

CHARGE PUMP

The charge pump is a Sipex-patented design
(5,306,954) and uses a unique approach compared
to older less-efficient designs. The charge pump
still requires four external capacitors, but uses
four-phase voltage shifting technique to attain
symmetrical power supplies. The charge pump
V

and V

outputs are regulated to +5.8V and

-5.8V, respectively. There is a free-running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.

Phase 1

__V

charge storage ----During this phase of

the clock cycle, the positive side of capacitors C

and C

are initially charged to V

. C+ is then

switched to ground and the charge in C

- is

transferred to C

-. Since C

+ is connected to V

the voltage potential across capacitor C

is now

Phase 2

--V

transfer --Phase two of the clock connects

the negative terminal of C

to the V

storage

capacitor and the positive terminal of C

ground, and transfers the negative generated
voltage to C

. This generated voltage is regulated

to 5.8V. Simultaneously, the positive side of
the capacitor C

is switched to V

and the

negative side is connected to ground.

Phase 3

--V

charge storage --The third phase of the

clock is identical to the first phase--the charge
transferred in C

produces V

in the negative

terminal of C

which is applied to the negative

side of the capacitor C

. Since C

+ is at V

, the

voltage potential across C

is 2

Phase 4

--V

transfer --The fourth phase of the clock

connects the negative terminal of C

to ground,

and transfers the generated 5.8V across C

to C

the V

storage capacitor. This voltage is

regulated to +5.8V. At the regulated voltage, the
internal oscillator is disabled and simultaneously
with this, the positive side of capacitor C

switched to V

and the negative side is connected

to ground, and the cycle begins again. The charge
pump cycle will continue as long as the
operational conditions for the internal oscillator
are present.

Date: 8/19/04

Since both V

and V

are separately generated

from V

; in a no-load condition V

and V

will

be symmetrical. Older charge pump approaches
that generate V

from V

will show a decrease in

the magnitude of V

compared to V

due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 1

µF with a 16V breakdown voltage

rating.

TERM_OFF FUNCTION

The SP508 contains a TERM_OFF pin that
disables all three receiver input termination
networks regardless of mode. This allows the
device to be used in monitor mode applications
typically found in networking test equipment.
The TERM_OFF pin internally contains a
pull-down device with an impedance of over
500k

, which will default in a "ON" condition

during power-up if V.35 receivers are used. The
individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.

LOOPBACK FUNCTION

The SP508 contains a LOOPBACK pin that
invokes a loopback path. This loopback path is
illustrated in Figure 50. LOOPBACK has an
internal pull-up resistor that defaults to normal
mode during power up or if the pin is left floating.
During loopback, the driver output and receiver
input characteristics will still adhere to its
appropriate specifications.

DECODER AND D_LATCH FUNCTION

The SP508 contains a D_LATCH pin that latches
the data into the D0, D1, and D2 decoder inputs.
If tied to a logic LOW ("0"), the latch is
transparent, allowing the data at the decoder
inputs to propagate through and program
the SP508 accordingly. If tied to a logic
HIGH("1"), the latch locks out the data and
prevents the mode from changing until this pin
is brought to a logic LOW.

There are internal pull-up devices on D0, D1,
and D2, which allow the device to be in
SHUTDOWN mode ("111") upon power up.
However , if the device is powered -up with the
D_LATCH at a logic HIGH, the decoder state of
the SP508 will be undefined.

ESD TOLERANCE

The SP508 device incorporates ruggedized ESD
cells on all driver output and receiver input
pins. The ESD structure is improved over our
previous family for more rugged applications
and environments sensitive to electrostatic
discharges and associated transients.

CTR1/CTR2 EUROPEAN COMPLIANCY

As with all of Sipex's previous multi-protocol
serial transceiver IC's the drivers and receivers
have been designed to meet all the requirements
to NET1/NET2 and TBR2 in order to meet
CTR1/CTR2 compliancy. The SP508 is also
tested in-house at Sipex and adheres to all the
NET1/2 physical layer testing and the ITU Series
V specifications before shipment. Please note
that although the SP508 , as with its predecessors,
adhere to CTR1/CTR2 compliancy testing,
any complex or unusual configuration should
be double-checked to ensure CTR1/CTR2
compliance. Consult the factory for details.

Date: 8/19/04

Figure 47. SP508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability

20 (V

.11,

V
.
28)

DTR_DSR_A

23 (V

.11)

DTR_DSR_B

C1-

C2-

C1+

C2+

SP509CF

TxD

TxCE

DTR

DCD_DCE

RxC

TxC

CTS

DSR

DCD_DTE

DB-26 Serial P

ort Connector Pins

Signal (DTE_DCE)

.11, V

.
35, V

.
28)

TXD_RXD_A

14 (V

.11,

V
.
35)

TXD_RXD_B

11 (V

.11,

V
.
35)

TXCE_TXC_B

25 (V

.10,

V
.
28)

LL_TM

.11, V

.
35, V

.
28)

*TXC_RXC_A

12 (V

.11,

V
.
35)

*TXC_RXC_B

SDEN

.11, V

.
35, V

.
28)

TXCE_TXC_A

.11, V

.
35, V

.
28)

RXD_TXD_A

16 (V

.11,

V
.
35)

RXD_TXD_B

8 (V

.11,

V
.
28)

DCD_DCD_A

10 (V

.11)

DCD_DCD_B

T
ypical SP509 DB-26 Ser

ial P

o
r
t
Configur

ation

Customer :

t
l
e :

Date :

Doc. # :

v
.

Ref

ence Design Sc

hematic

233 South Hillvie

w Dr

.
· Milpitas

, CA.

95035

SIGN

AL GND (10 Pins)

9 (V

.11,

V
.
35)

RXC_TXCE_B

.11, V

.
35, V

.
28)

RXC_TXCE_A

LLEN

STEN

GND

* - Dr

er applies f

or DCE only on pins 15 and 12.

Receiv

er applies f

or DTE only on pins 15 and 12.

+5V

#103 (TxD)

#108 (DTR)

#105 (R

TS)

#141 (LL)

#105 (RXD)

#115 (RXC)

#106 (CTS)

#107 (DSR)

#109 (DCD)

DTE

I/O Lines represented b

y
doub

le arro

whead signifies a bi-directional b

u
s
.

Input Line

Output Line

#114 (TxC)

#113 (TXCE)

#109 (DCD)

DCE

RxD

TTEN

TREN

RSEN

RRCEN

RLEN

RDEN

TMEN

TxCEN

TEN

DMEN

CSEN

TEN

ICEN

V10_GND

V35TGND1

V35TGND2

V35TGND3

V35RGND

TERM_OFF

D_LA

TCH

Charge Pump Section

ansceiv

er Section

Logic Section

+5V

21 (V

.10,

V
.
28)

RL_RI

22 (V

.10,

V
.
28)

RI_RL

18 (V

.10,

V
.
28)

LL_TM

#125 (RI)

#142 (TM)

#140 (RL)

DCE/DTE

er applies f

or DCE only on pins 8 and 10.

Receiv

er applies f

or DTE only on pins 8 and 10.

LOOPBA

+5V

19 (V

.11)

R
TS_CTS_B

4 (V

.11,

V
.
28)

R
TS_CTS_A

6 (V

.11,

V
.
28)

DSR_DTR_A

22 (V

.11)

DSR_DTR_B

13 (V

.11)

CTS_R

TS_B

5 (V

.11,

V
.
28)

CTS_R

TS_A

Date: 8/19/04

SP508 Enhanced WAN MultiProtocol Serial Transceiver

Date: 6/14/04

SP508 Enhanced WAN MultiProtocol Serial Transceiver

DCE CONFIGURATION

Recommended Signals and Port Pin Assignments

Number

Pin Mnemonic

Circuit

Pin Mnemonic

Number

Signal

Type

Mnemo

nic

DB-25

Pin(F)

Signal

Type

Mnemo

nic

DB-25

Pin(F)

Signal

Type

Mnemo

nic

DB-37

Pin(F)

Signal

Type

Mnemo

nic

M34

Pin(F)

Signal

Type

Mnemo

nic

DB-15
Pin(F)

TxD

SD(A)

V.28

V.11

BB(A)

V.11

RD(A)

V.35

104

V.11

R(A)

SDEN

SD(B)

100

V.11

BB(B)

V.11

RD(B)

V.35

104

V.11

R(B)

TxCE

TT(A)

V.28

V.11

DD(A)

V.11

RT(A)

V.35

115

V.11

B(A)

7**

TTEN

TT(B)

V.11

DD(B)

V.11

RT(B)

V.35

115

V.11

B(B)

14**

ST(A)

V.28

V.11

DB(A)

V.11

ST(A)

V.35

114

V.11

S(A)

STEN

ST(B)

V.11

DB(B)

V.11

ST(B)

V.35

114

V.11

S(B)

RTS

RS(A)

V.28

V.11

CB(A)

V.11

CS(A)

V.28

106

V.11

I(A)

RSEN

RS(B)

V.11

CB(B)

V.11

CS(B)

V.11

I(B)

DTR

TR(A)

V.28

V.11

CC(A)

V.11

DM(A)

V.28

107

TREN

TR(B)

V.11

CC(B)

V.11

DM(B)

DCD_DCE

RRC(A)

V.28

V.11

CF(A)

V.11

RR(A)

V.28

109

RRCEN

RRC(B)

V.11

CF(B)

V.11

RR(B)

RL(A)

V.28

125

RLEN

LL(A)

V.28

V.10

V.28

142

LLEN#

RxD

RD(A)

V.28

V.11

BA(A)

V.11

SD(A)

V.35

103

V.11

T(A)

RDEN#

RD(B)

V.11

BA(B)

V.11

SD(B)

V.35

103

V.11

T(B)

RxC

RT(A)

V.28

V.11

DA(A)

V.11

TT(A)

V.35

113

V.11

X(A)

7**

RTEN#

RT(B)

V.11

DA(B)

V.11

TT(B)

V.35

113

V.11

X(B)

14**

TxC

TxC(A)

TxCEN#

TxC(B)

CTS

CS(A)

V.28

V.11

CA(A)

V.11

RS(A)

V.28

105

V.11

C(A)

CSEN#

CS(B)

V.11

CA(B)

V.11

RS(B)

V.11

C(B)

DSR

DM(A)

V.28

V.11

CD(A)

V.11

TR(A)

V.28

108

DMEN#

DM(B)

V.11

CD(B)

V.11

TR(B)

DCD_DTE

RRT(A)

RRTEN#

RRT(B)

V.28

V.10

V.28

140

ICEN#

TM(A)

V.28

V.10

V.28

141

TMEN

Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver

** X.21 use either B() or
X(), not both

Pin assignments and signal functions are subject to national or regional variation and
proprietary / non-standard implementations

Receiver_7

Receiver_8

RS-449

V.35

X.21

Driver_1

RS-232 or V.24

EIA-530

Receiver_5

Receiver_6

Driver_7

Driver_8

Receiver_2

Receiver_3

Receiver_1

SP508 Multiprotocol Configured as DCE

Interface to System Logic

Interface to Port-

Connector

Receiver_4

Driver_2

Driver_3

Driver_4

Driver_5

Driver_6

Date: 8/19/04

SP508 Enhanced WAN MultiProtocol Serial Transceiver

DDate: 6/14/04

SP508 Enhanced WAN MultiProtocol Serial Transceiver

DTE CONFIGURATION

Recommended Signals and Port Pin Assignments

Number

Pin Mnemonic

Circuit

Pin Mnemonic

Number

Signal

Type

Mnemo

nic

DB-25
Pin(M)

Signal

Type

Mnemo

nic

DB-25

Pin(M)

Signal

Type

Mnemo

nic

DB-37

Pin(M)

Signal

Type

Mnemo

nic

M34

Pin(M)

Signal

Type

Mnemo

nic

DB-15

Pin(M)

Signal

Type

Mnemo

nic

DIN-8
Pin(F)

TxD

SD(A)

V.28

V.11

BA(A)

V.11

SD(A)

V.35

103

V.11

T(A)

V.11

TxD -

SDEN

SD(B)

100

V.11

BA(B)

V.11

SD(B)

V.35

103

V.11

T(B)

V.11

TxD +

TxCE

TT(A)

V.28

V.11

DA(A)

V.11

TT(A)

V.35

113

V.11

X(A)

7**

TTEN

TT(B)

V.11

DA(B)

V.11

TT(B)

V.35

113

V.11

X(B)

14**

ST(A)

STEN

ST(B)

RTS

RS(A)

V.28

V.11

CA(A)

V.11

RS(A)

V.28

105

V.11

C(A)

RSEN

RS(B)

V.11

CA(B)

V.11

RS(B)

V.11

C(B)

DTR

TR(A)

V.28

V.11/10 CD(A)

V.11

TR(A)

V.28

108

V.10

HSKo

TREN

TR(B)

V.11/Z CD(B)

V.11

TR(B)

DCD_DCE

RRC(A)

RRCEN

RRC(B)

RL(A)

V.28

V.10

V.28

140

RLEN

LL(A)

V.28

V.10

V.28

141

LLEN#

RxD

RD(A)

V.28

V.11

BB(A)

V.11

RD(A)

V.35

104

V.11

R(A)

V.11

RxD-

RDEN#

RD(B)

V.11

BB(B)

V.11

RD(B)

V.35

104

V.11

R(B)

V.11

RxD+

RxC

RT(A)

V.28

V.11

DD(A)

V.11

RT(A)

V.35

115

RTEN#

RT(B)

V.11

DD(B)

V.11

RT(B)

V.35

115

TxC

TxC(A)

V.28

V.11

DB(A)

V.11

ST(A)

V.35

114

V.11

S(A)

TxCEN#

TxC(B)

V.11

DB(B)

V.11

ST(B)

V.35

114

V.11

S(B)

CTS

CS(A)

V.28

V.11

CB(A)

V.11

CS(A)

V.28

106

V.11

I(A)

GND

CSEN#

CS(B)

V.11

CB(B)

V.11

CS(B)

V.11

I(B)

V.10*

HSKi

DSR

DM(A)

V.28

V.11/10 CC(A)

V.11

DM(A)

V.28

107

V.11

B(A)

7**

V.10

GPi

DMEN#

DM(B)

V.11/Z CC(B)

V.11

DM(B)

V.11

B(B)

14**

DCD_DTE

RRT(A)

V.28

V.11

CF(A)

V.11

RR(A)

V.28

109

RRTEN#

RRT(B)

V.11

CF(B)

V.11

RR(B)

V.28

V.10

V.28

125

ICEN#

TM(A)

V.28

V.10

V.28

142

TMEN

RS-449

V.35

X.21

Receiver_7

Driver_3

Driver_4

Driver_5

EIA-530

Receiver_4

Receiver_5

Receiver_6

Driver_7

Driver_8

Driver_6

Driver_2

SP508 Multiprotocol Configured as DTE

Interface to System Logic

Interface to Port-

Connector

Driver_1

EIA-530 uses V.11 (differential) for DSR (CC) and DTR (CD) signals; EIA-530-A uses single-
ended V.10 for DSR and DTR and adds RI signal on pin 22

AppleTalkTM

Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver

** X.21 use either B() or
X(), not both

Pin assignments and signal functions are subject to national or regional variation and proprietary
/ non-standard implementations

Receiver_1

Receiver_2

Receiver_3

Receiver_8

RS-232 or V.24

Date: 8/19/04

ORDERING INFORMATION

Part Number Top Mark Temperature Range

Package Types

SP508CF ...................... SP508CFYYWW..........................0

C to +70

C .............................. 100 Lead LQFP

SP508EF ...................... SP508EFYYWW.......................-40

C to +85

C .............................. 100 Lead LQFP

Corporation

ANALOG EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600

DATE

REVISION

DESCRIPTION

3/31/04

Implemented tracking revision.

5/6/04

Added Top Mark to ordering information.

6/3/04

Added Tables to page 28 and 29.

8/19/04

Corrected pin description table and figure 49. Updated DCE/DTE
tables.

REVISION HISTORY

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP508EF/TR = standard; SP508EF-L/TR = lead free

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SP508CF

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SP508CF