1
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
SP6651A
FEATURES
DFN Package (3mm x 3mm)
Ultra-low 20
A Quiescent Current
98% Efficiency Possible
800mA Output Current
2.7V to 5.5V Input Voltage Range
Output Adjustable Down to 1.0V
No External FET's Required
1.25A Inductor Peak Current Limit
100% Duty Ratio Low Dropout Operation
80
A Light Load Quiescent Current
in Dropout
Over Temperature Protection
Logic Shutdown Control
Programmable UVLO and Adaptive
Battery Low Output
High Efficiency 800mA Synchronous Buck Regulator
APPLICATIONS
PDA's
DSC's
MP3 Players
USB Devices
Point of Use Power
The SP6651A is a 800mA synchronous buck regulator which is ideal for portable applications that
use a Li-Ion or 3 cell alkaline/NiCD/NiMH input. The SP6651A's proprietary control loop, 20
A
light load quiescent current, and 0.3
power switches provide excellent efficiency across a wide
range of output currents. As the input battery supply decreases towards the output voltage the
SP6651A seamlessly transitions into 100% duty ratio operation further extending useful battery
life. The SP6651A is protected against overload and short circuit conditions with a precise
inductor peak current limit. Other features include programmable under voltage lockout and low
battery detection, externally programmed output voltage down to 1.0V, logic level shutdown
control, and 140
C over temperature shutdown.
BLON
VI
VO
D1
D0
22
F
L1
10
H
V
OUT
800mA
2.7V to 5.5V Input
10
1
F
SP6651A
P
VIN
BLON
D1
D0
LX
GND
V
OUT
FB
P
GND
V
IN
22
F
C
IN
CV
IN
C
OUT
R
VIN
R
F
CF
22pF
R
I
200K
1M
Ideal for portable designs powered with Li Ion battery
TYPICAL APPLICATION SCHEMATIC
DESCRIPTION
SP6651A
10 Pin DFN
10
9
8
7
6
1
2
3
4
5
PV
IN
V
IN
BLON
D1
D0
LX
P
GND
GND
V
OUT
FB
Now Available in Lead Free Packaging
2
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
Input Voltage Operating
UVLO
5.5
V
Result of I
Q
measurement at V
IN
=PV
IN
=5.5V
Range
Minimum Output Voltage
1.0
V
FB Set Voltage, Vr
0.784
0.800
0.816
V
25
C, I
O
=200mA Close Loop. L
I
= 10
H,
C
OUT
= 22
F
Overall Accuracy
Measured at V
IN
=5.5V, no load and
(-40
C to 85
C)
5
%
V
IN
=3.6V, 200mA load, Close Loop
(0
C to 70
C)
4
On-Time Constant - K
ON
1.5
2.25
3.0
V*
s
Close Loop, L
I
= 10
H,C
OUT
= 22
F
Min, T
ON
=K
ON
/(V
IN
-V
OUT
)
Off-Time Constant - K
OFF
1.6
2.4
3.2
V*
s
Inductor current limit tripped, VFB=0.5V
Min, T
OFF
=K
OFF
/V
OUT
Measured at V
OUT
= 2V
Off-Time Blanking
100
ns
PMOS Switch Resistance
0.3
0.6
I
PMOS
= 200mA
NMOS Switch Resistance
0.3
0.6
I
NMOS
= 200mA
Inductor Current Limit
1.0
1.25
1.50
A
VFB=0.5V
LX Leakage Current
0.01
3
A
D0=D1=0
Power Efficiency
96
%
V
OUT
=2.5V, I
O
=200mA
92
V
OUT
=3.3V, I
O
=800mA
Minimum Guaranteed Load
800
900
mA
Current
V
IN
Quiescent Current
20
30
A
V
OUT
=3.3V, V
IN
=3.6V and V
IN
= 5.5V
V
IN
Shutdown Current
1
500
nA
D1=D0=0V
V
OUT
Quiescent Current
2
5
A
V
OUT
= 3.3V
V
OUT
Shutdown Current
1
500
nA
D1=D0=0V
UVLO
2.55
2.70
2.85
D1=0V, D0=V
IN
Undervoltage Lockout
2.70
2.85
3.00
V
D1=V
IN
, D0=0V
Threshold, V
IN
falling
2.85
3.00
3.15
D1=V
IN
, D0=V
IN
UVLO hysteresis
40
mV
Battlo Trip Voltage, V
IN
falling
265
300
335
mV
Measured as V
IN
-V
OUT
Battlo Trip Voltage Hysteresis
9
mV
BLON Low Output Voltage
0.4
V
V
IN
=3.3V, I
SINK
=1mA
BLON Leakage Current
1
A
V
BLON
=3.6V
Over-Temperature
140
C
Rising Trip Point
Over-Temperature Hysteresis
14
C
D1,D0 Leakage Current
1
500
nA
D1,D0 Input Threshold Voltage
0.60
0.90
V
High to Low Transition
1.25
1.8
V
Low to High Transition
FB Leakage Current
1
100
nA
FB=1V
V
IN
=UV
IN
=V
SDN
=3.6V, V
OUT
=V
FB
, I
O
= 0mA, T
AMB
= -40
C to +85C, typical values at 27C unless otherwise noted.
PV
IN
,V
IN
.............................................................................................. 6V
All other pins .............................................................. -0.3V to V
IN
+0.3V
PV
IN
, P
GND
, LX current ........................................................................ 2A
Storage Temperature .................................................. -65
C to 150
C
Operating Temperature ................................................. -40
C to +85
C
Lead Temperature (Soldering, 10 sec) ....................................... 300
C
Thermal Resistance
JA
:
10-Pin MSOP....................................................................128
C/W
10-Pin DFN ........................................................................68
C/W
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may
affect reliability.
ELECTRICAL CHARACTERISTICS
3
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
PIN DESCRIPTION
PIN NUMBER
PIN NAME
DESCRIPTION
1
PV
IN
Input voltage power pin. Inductor charging current passes through this pin.
2
V
IN
Internal supply voltage. Control circuitry powered from this pin.
3
BLON
Open drain battery low output. (V
IN
-V
O
) less than 300mV pulls this
node to ground. (V
IN
-V
O
) above threshold, this node is open.
4
D1
Digital mode control input. See table I for definition.
5
D0
Digital mode control input. See table I for definition.
6
FB
External feedback network input connection. Connect a resistor from
FB to ground and FB to V
OUT
to set the output voltage. This pin
regulates to the internal bandgap reference voltage of 0.8V.
7
V
OUT
Output voltage sense pin. Used by the timing circuit to set minimum on
and off times.
8
GND
Internal ground pin. Control circuitry returns current to this pin.
9
P
GND
Power ground pin. Synchronous rectifier current returns through this pin.
10
LX
Inductor switching node. Inductor tied between this pin and the output
capacitor to create regulated output voltage.
FUNCTIONAL DIAGRAM
D1
D0
0
0
Shutdown. All internal circuitry is disabled and the power switches are opened.
0
1
Device enabled, falling UVLO threshold =2.70V
1
0
Device enabled, falling UVLO threshold =2.85V
1
1
Device enabled, falling UVLO threshold =3.00V
Table 1. Operating Mode Definition
V
IN
Zero_X
DRVON
Q
R
Q
S
Min Ton
BLON
D0
PV
IN
OVR_I
MIN Ton
OVR_I
K
OFF
/V
OUT
Vin
LX
T
OFF
=
UVLO
BLANK = Tblank(=100ns) or Toff = Koff/Vout
V
OUT
ILIM/M
REF
1
VOLOW
_
FB
+
-
V
RAMP
RST
P
GND
TSD
BLANK
+
-
300mV
+
-
C
UVLO
TONOVER
Internal Supply
REF'
OVR_I
V
OUT
+
-
C
DRVON
BLANK
ILIM/M
D1
VOLOW
+
-
C
TONOVER
Min Ton = K
ON
/(V
IN
-V
OUT
)
Ref
One-Shot
DRVON
+
-
C
Block
FB'
GND
REF
M
+
-
Vos
DRIVER
DRVON
=100ns
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Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
60
65
70
75
80
85
90
95
100
0.1
1.0
10.0
100.0
1000.0
ILoad (mA)
Ef
ficiency (%)
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
3.20
3.25
3.30
3.35
3.40
0
200
400
600
800
1000
ILoad (mA)
V
out (V)
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
0
100
200
300
400
500
3.0
3.3
3.6
3.9
4.2
Vin (V)
Iin (uA)
Tamb = 85C
Tamb = 25C
Tamb = -40C
1.45
1.47
1.49
1.51
1.53
1.55
0
200
400
600
800
1000
ILoad (mA)
V
out (V)
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
0
10
20
30
40
50
3.0
3.3
3.6
3.9
4.2
Vin (V)
Iin (
A)
Tamb = 85C
Tamb = 25C
Tamb = -40C
100
1.0
10.0
100.0
1000.0
ILoad (mA)
Ef
ficiency (%)
95
90
85
80
75
70
65
60
0.
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
Figure 1. Efficiency vs Load, V
OUT
= 3.3V
Figure 2. Efficiency vs Load, V
OUT
= 1.5V
Figure 3. Line/Load Rejection, V
OUT
= 3.3V
Figure 4. Line/Load Rejection, V
OUT
= 1.5V
Figure 5. No Load Battery Current, V
OUT
=3.3V
Figure 6. No Load Battery Current, V
OUT
=1.5V
TYPICAL PERFORMANCE CHARACTERISTICS
Refer to the typical application schematic, T
AMB
= +27
C
5
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Vin (V)
Kon (V*usec)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Vin (V)
Kon (V*usec)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Vin (V)
Koff (V*usec)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Vin (V)
Kof
f (V*usec)
Figure 7. K
ON
vs V
IN
, V
OUT
=3.3V
Figure 8. K
ON
vs V
IN
, V
OUT
=1.5V
Figure 9. K
OFF
vs V
IN
, V
OUT
=3.3V
Figure 10. K
OFF
vs V
IN
, V
OUT
=1.5V
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
Refer to the typical application schematic, T
AMB
= +27
C
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
3.5
4.0
4.5
5.0
Vin (V)
Frequency (KHz)
Vout = 3.3V
Measured
Vout = 3.3V
Calculated
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
3.4
3.8
4.2
4.6
5.0
Vin (V)
Frequency (KHz)
Vout = 1.5V
Measured
Vout = 1.5V
Calculated
Figure 11. Ripple Frequency vs. V
IN
, I
OUT
=600mA,
V
OUT
=3.3V
Figure 12. Ripple Frequency vs. V
IN
, I
OUT
=600mA,
V
OUT
=1.5V
6
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
CH.2=V
OUT
50mV/div. AC
CH.4=I
OUT
0.5A/div
CH.2=V
OUT
50mV/div. AC
CH.4=I
IN
0.5A/div
CH.1=V
SHDN
10V/div.
CH.2=V
OUT
1V/div. AC
CH.4=ILx
0.5A/div
CH.1=V
SHDN
10V/div.
CH.2=V
OUT
2V/div. AC
CH.4=ILx
0.5A/div
Figure 15. Load Step, I
OUT
=0.4A to 0.8A, V
OUT
=3.3V
Figure 16. Load Step, I
OUT
=0.4A to 0.8A, V
OUT
=1.5V
Figure 17. Start up from SHDN, I
OUT
=0.6A, V
OUT
=3.3V
Figure 18. Start up from SHDN, I
OUT
=0.6A, V
OUT
=1.5V
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
Refer to the typical application schematic, T
AMB
= +27
C
CH.1=V
IN
2.5V/div
CH.2=V
OUT
2.0V/div
CH.4=I
IN
0.5A/div
CH.1=V
IN
2.5V/div
CH.2=V
OUT
5.0V/div
CH.4=I
IN
0.5A/div
Figure 13. V
IN
Start up, I
OUT
=0.6A, V
OUT
=3.3V
Figure 14. V
IN
Start up, I
OUT
=0.6A, V
OUT
=1.5V
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Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
THEORY OF OPERATION
The SP6651A is a high efficiency synchronous
buck regulator with an input voltage range of
+2.7V to +5.5Vand an output that is adjustable
between +1.0V and V
IN
. The SP6651A features
a unique on-time control loop that runs in dis-
continuous conduction mode (DCM) or con-
tinuous conduction mode (CCM) using syn-
chronous rectification. Other features include
over-temperature shutdown, over-current pro-
tection, digitally controlled enable and under-
voltage lockout, a battery low indicator, and an
external feedback pin.
The SP6651A operates with a light load quies-
cent current of 20
A using a 0.3 PMOS main
switch and a 0.3
NMOS synchronous switch.
It operates with excellent efficiency across the
entire load range, making it an ideal solution for
battery powered applications and low current
step-down conversions. The part smoothly tran-
sitions into a 100% duty cycle under heavy load/
low input voltage conditions.
On-Time Control - Charge Phase
The SP6651A uses a precision comparator and
a minimum on-time to regulate the output volt-
age and control the inductor current under nor-
mal load conditions. As the feedback pin drops
below the regulation point, the loop comparator
output goes high and closes the main switch.
The minimum on-timer is triggered, setting a
logic high for the duration defined by:
T
ON
=
K
ON
V
IN
- V
OUT
where:
K
ON
= 2.25V*
sec constant
V
IN
= V
IN
pin voltage
V
OUT
= V
OUT
pin voltage
To accommodate the use of ceramic and other
low ESR capacitors, an open loop ramp is added
to the feedback signal to mimic the inductor
current ripple. The following waveforms de-
scribe the ideal ramp operation in both CCM and
DCM operation.
In either CCM or DCM, the negative going
ramp voltage (V
RAMP
in the functional diagram)
is added to FB and this creates the FB's signal.
This FB signal is applied to the negative termi-
nal of the loop comparator. To the positive
terminal of the loop comparator is applied the
REF voltage of 0.8V plus an offset voltage Vos
to compensate for the DC level of V
RAMP
ap-
plied to the negative terminal. The result is an
internal ramp with enough negative going offset
(approximately 50mV) to trip the loop com-
parator whenever FB falls below regulation.
The output of the loop comparator, a rising
VOLOW, causes a SET if BLANK = 0 and
OVR_I = 0. This starts inductor charging
(DRVON = 1) and starts the minimum on-timer.
The minimum on-timer times out and indicates
DRVON can be reset if the voltage loop is
satisfied. If V
OUT
is still below the regulation
DRVON
REF, FB
V
OS
REF'
FB'
I(L1)
RAMP: DCM OPERATION
DRVON
REF, FB
V
OS
REF'
FB'
I(L1)
RAMP: CCM OPERATION
8
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
point RESET is held low until V
OUT
is above
regulation. Once RESET occurs T
ON
minimum
is reset, and the T
OFF
one-shot is triggered to
blank the loop comparator from starting a new
charge cycle for a minimum period. This blank-
ing period occurs during the noisy LX transition
to discharge, where spurious comparator states
may occur. For T
OFF
> T
BLANK
the loop is in a
discharge or wait state until the loop comparator
starts the next charge cycle by DRVON going
high.
If an over current occurs during charge the loop
is interrupted and DRVON is RESET. The off-
time one-shot pulse width is widened to T
OFF
=
K
OFF
/ V
OUT
, which holds the loop in discharge
for that time. At the end of the off-time the loop
is released and controlled by VOLOW. In this
manner maximum inductor current is controlled
on a cycle-by-cycle basis. An assertion of UVLO
(undervoltage lockout) or TSD (thermal shut-
down) holds the loop in no-charge until the fault
has ended.
On-Time Control - Discharge Phase
The discharge phase follows with the high side
PMOS switch opening and the low side NMOS
switch closing to provide a discharge path for
the inductor current. The decreasing inductor
current and the load current cause the output
voltage to drop. Under normal load conditions
when the inductor current is below the pro-
grammed limit, the off-time will continue until
the output voltage falls below the regulation
threshold, which initiates a new charge cycle via
the loop comparator.
The inductor current "floats" in continuous con-
duction mode. During this mode the inductor
peak current is below the programmed limit and
the valley current is above zero. This is to satisfy
load currents that are greater than half the mini-
mum current ripple. The current ripple, I
LR
, is
defined by the equation:
I
LR
K
ON
*
V
IN
- V
OUT
- I
OUT
* R
CH
L
V
IN
- V
OUT
where:
L = Inductor value
I
OUT
= Load current
R
CH
= PMOS on resistance, 0.3
typ.
If the I
OUT
* R
CH
term is negligible compared
with (V
IN
- V
OUT
), the above equation simplifies
to:
I
LR
K
ON
L
For most applications, the inductor current ripple
controlled by the SP6651A is constant regard-
less of input and output voltage. Because the
output voltage ripple is equal to:
V
OUT
(ripple) = I
LR
* R
ESR
where:
R
ESR
= ESR of the output capacitor
the output ripple of the SP6651A regulator is
independent of the input and output voltages.
For battery powered applications, where the
battery voltage changes significantly, the
SP6651A provides constant output voltage ripple
through-out the battery lifetime. This greatly
simplifies the LC filter design.
The maximum loop frequency in CCM is de-
fined by the equation:
F
LP
(V
IN
- V
OUT
) * (V
OUT
+ I
OUT
* R
DC
)
K
ON
* [V
IN
+ I
OUT
* (R
DC
- R
CH
)]
where:
F
LP
= CCM loop frequency
R
DC
= NMOS on resistance, 0.3
typ.
Ignoring conduction losses simplifies the loop
frequency to:
F
LP
1
*
V
OUT
* (V
IN
- V
OUT
)
K
ON
V
IN
AND'ing the loop comparator and the on-timer
reduces the switching frequency for load cur-
rents below half the inductor ripple current. This
increases light load efficiency. The minimum
on-time insures that the inductor current ripple
THEORY OF OPERATION : Continued
9
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
is a minimum of K
ON
/L, more than the load
current demands. The converter goes in to a
standard pulse frequency modulation (PFM)
mode where the switching frequency is propor-
tional to the load current.
Low Dropout and Load Transient Operation
AND'ing the loop comparator also increases the
duty ratio past the ideal D= V
OUT
/V
IN
up to and
including 100%. Under a light to heavy load
transient, the loop comparator will hold the
main switch on longer than the minimum on
timer until the output is brought back into regu-
lation.
Also, as the input voltage supply drops down
close to the output voltage, the main MOSFET
resistance loss will dictate a much higher duty
ratio to regulate the output. Eventually as the
input voltage drops low enough, the output
voltage will follow, causing the loop compara-
tor to hold the converter at 100% duty cycle.
This mode is critical in extending battery life
when the output voltage is at or above the
minimum usable input voltage. The dropout
voltage is the minimum (V
IN
-V
OUT
) below
which the output regulation cannot be main-
tained. The dropout voltage of SP6651A is equal
to I
L
* (0.3
+ R
L1
) where 0.3
is the typical
R
DS(ON)
of the P-Channel MOSFET and R
L
is
the DC resistance of the inductor.
The SP6651A has been designed to operate in
dropout with a light load Iq of only 80
A. The
on-time control circuit seamlessly operates the
converter between CCM, DCM, and low drop-
out modes without the need for compensation.
The converter's transient response is quick since
there is no compensated error amplifier in the loop.
Inductor Over-Current Protection
To reduce the light load dropout Iq, the SP6651A
over-current system is only enabled when I
L1
>
400mA. The inductor over-current protection
circuitry is programmed to limit the peak induc-
tor current to 1.25A. This is done during the on-
time by comparing the source to drain voltage
drop of the PMOS passing the inductor current
with a second voltage drop representing the
maximum allowable inductor current. As the
two voltages become equal, the over-current
comparator triggers a minimum off-time one
shot. The off-time one shot forces the loop into
the discharge phase for a minimum T
OFF
time
causing the inductor current to decrease. At the
end of the off-time, loop control is handed back
to the AND'd on-time signal. If the output
voltage is still low, charging begins until the
output is in regulation or the current limit has
been reached again. During startup and over-
load conditions, the converter behaves like a
current source at the programmed limit minus
half the current ripple. The minimum T
OFF
is
controlled by the equation:
T
OFF (MIN)
=
K
OFF
V
OUT
Under-Voltage Lockout
The SP6651A is equipped with a programmable
under-voltage lockout to protect the input bat-
tery source from excessive currents when sub-
stantially discharged. When the input supply is
below the UVLO threshold both power switches
are open to prevent inductor current from flow-
ing. The three levels of falling input voltage
UVLO threshold are shown in Table 1, with a
typical hysteresis of 120mV to prevent chatter-
ing due to the impedance of the input source.
During UVLO, BLON is forced low.
Under-Current Detection
The synchronous rectifier is comprised of an
inductor discharge switch, a voltage compara-
tor, and a driver latch. During the off-time,
positive inductor current flows into the PGND
pin 9 through the low side NMOS switch to LX
pin 10, through the inductor and the output
capacitor, and back to pin 9. The comparator
monitors the voltage drop across the discharge
NMOS. As the inductor current approaches zero,
the channel voltage sign goes from negative to
positive, causing the comparator to trigger the
THEORY OF OPERATION: Continued
10
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
For the typical SP6651A application circuit with
inductor size of 10
H, and K
ON
of 2V*
sec, the
SP6651A current ripple would be about 200mA,
driver latch and open the switch to prevent
inductor current reversal. This circuit along
with the on-timer puts the converter into PFM
mode and improves light load efficiency when
the load current is less than half the inductor
ripple current defined by K
ON
/L.
Thermal Shutdown
The converter will open both power switches if
the die junction temperature rises above 140
C.
The die must cool down below 126
C before the
regulator is re-enabled. This feature protects the
SP6651A and surrounding circuitry from exces-
sive power dissipation due to fault conditions.
Shutdown/Enable Control
The D0, D1 pins 4,5 of the device are logic level
control pins that according to Table 1 shut down
the converter when both are a logic low, or
enables the converter when either are a logic
high. When the converter is shut down, the
power switches are opened and all circuit bias-
ing is extinguished leaving only junction leak-
age currents on supply pins 1 and 2. After pins
4 or 5 are brought high to enable the converter,
there is a turn on delay to allow the regulator
circuitry to re-establish itself. Power conversion
begins with the assertion of the internal refer-
ence ready signal which occurs approximately
150
s after the enable signal is received.
Battery Low Indicator
The BLON function is a differential measure-
ment of (V
IN
-V
OUT
) which causes the open
drain NMOS on pin 3 to sink current to ground
when (V
IN
-V
OUT
) < 300mV. Tying a resistor
from pin 3 to V
IN
or V
OUT
creates a logic level
battery low indicator. A low bandwidth com-
parator and 3% hysteresis filter the input voltage
ripple to prevent noisy transitions at the thresh
old. BLON is forced Low when in UVLO.
External Feedback Pin
The FB pin 6 is compared to an internal refer-
ence voltage of 0.8V to regulate the SP6651A
output. The output voltage can be externally
programmed within the range +1.0V to +5.0V
by tying a resistor from FB to ground and FB to
V
OUT
(pin7). See the applications section for
resistor selection information.
Inductor Selection
The SP6651A uses a specially adapted mini-
mum on-time control of regulation utilizing a
precision comparator and bandgap reference.
This adaptive minimum on-time control has the
advantage of setting a constant current ripple
for a given inductor size. From the operations
section it has been shown:
Inductor Current Ripple, I
LR
K
ON
L
THEORY OF OPERATION: Continued
APPLICATION INFORMATION
and would be fairly constant for different input and
output voltages, simplifying the selection of com-
ponents for the SP6651A power circuit. Other
inductor values could be selected, as shown in
Table 2 Components Selection. Using a larger
value than 10
H in an attempt to reduce output
voltage ripple would reduce inductor current ripple
and may not produce as stable an output ripple.
For larger inductors with the SP6651A, which
has a peak inductor current of 1.25A, most
15
H or 22H inductors would have to be larger
physical sizes, limiting their use in small por-
table applications. Smaller values like 6.8
H
would more easily meet the 1.25A limit and
come in small case sizes, and the increased
11
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
For the 22
F POSCAP with 0.04 ESR, and a
10
H inductor yielding 200mA inductor current
ripple I
LR
, the V
OUT
ripple would be 8mVpp.
Since 8mV is a very small signal level, the actual
value would probably be larger due to noise and
layout issues, but this illustrates that the SP6651A
output ripple can be very low indeed. To improve
stability, a small ceramic capacitor, C
F
= 22pF
should be paralleled with the feedback voltage
divider RF, as shown on the typical application
schematic on page 1. Another function of the
output capacitance is to hold up the output voltage
during the load transients and prevent excessive
overshoot and undershoot. The typical perfor-
mance characteristics curves show very good load
step transient response for the SP6651A with the
recommended output capacitance of 22
F ce-
ramic.
The input capacitor will reduce the peak current
drawn from the battery, improve efficiency and
significantly reduce high frequency noises in-
duced by a switching power supply. The typical
input capacitor for the SP6651A is 22
F ceramic,
POSCAP or Aluminum Polymer. These capaci-
tors will provide good high frequency bypassing
and their low ESR will reduce resistive losses for
higher efficiency. An RC filter is recommended
for the V
IN
pin 2 to effectively reduce the noise for
the ICs analog supply rail which powers sensitive
circuits. This time constant needs to be at least 5
times greater than the switching period, which is
calculated as 1/FLP during the CCM mode. The
typical application schematic uses the values of
R
VIN
= 10
and C
VIN
= 1
F to meet these require-
ments.
APPLICATION INFORMATION: Continued
inductor current ripple of almost 300mA would
produce very stable regulation and fast load
transient response at the expense of slightly
reduced efficiency.
Other inductor parameters are important: the in-
ductor current rating and the DC resistance. When
the current through the inductor reaches the level
of I
SAT
, the inductance drops to 70% of the
nominal value. This non-linear change can cause
stability problems or excessive fluctuation in in-
ductor current ripple. To avoid this, the inductor
should be selected with saturation current at least
equal to the maximum output current of the con-
verter plus half the inductor current ripple. To
provide the best performance in dynamic condi-
tions such as start-up and load transients, inductors
should be chosen with saturation current close to
the SP6651A inductor current limit of 1.25A.
DC resistance, another important inductor charac-
teristic, directly affects the efficiency of the con-
verter, so inductors with minimum DC resistance
should be chosen for high efficiency designs.
Recommended inductors with low DC resistance
are listed in table 2. Preferred inductors for on
board power supplies with the SP6651A are mag-
netically shielded types to minimize radiated mag-
netic field emissions.
Capacitor Selection
The SP6651A has been designed to work with
very low ESR output capacitors (listed in Table 2
Component Selection) which for the typical appli-
cation circuit are 22
F ceramic, POSCAP or Alu-
minum Polymer. These capacitors combine small
size, low ESR and good value. To regulate the
output with low ESR capacitors of 0.01
or less,
an internal ramp voltage V
RAMP
has been added to
the FB signal to reliably trip the loop comparator
(as described in the Operations section).
Output ripple for a buck regulator is determined
mostly by output capacitor ESR, which for the
SP6651A with a constant inductor current ripple
can be expressed as:
V
OUT
(ripple) = I
LR
* R
ESR
12
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
APPLICATION INFORMATION: Continued
Output Voltage Program
The output voltage is programmed by the external
divider, as shown in the typical application circuit
on page 1. First pick a value for R
I
that is no larger
than 300K. Too large a value of R
I
will reduce the
AC voltage seen by the loop comparator since the
internal FB pin capacitance can form a low pass
filter with R
F
in parallel with R
I
. The formula for
R
F
with a given R
I
and output voltage is:
R
F
= (
V
OUT
- 1
) R
I
0.8V
Output Voltage Ripple Frequency
An important consideration in a power supply
application is the frequency value of the output
ripple. Given the control technique of the
SP6651A (as described in the operations sec-
tion), the frequency of the output ripple will
vary when in light to moderate load in the
discontinuous or PFM mode. For moderate to
heavy loads greater than about 100mA inductor
current ripple, (for the typical 10
H inductor
application on 100mA is half the 200mA induc-
tor current ripple), the output ripple frequency
will be fairly constant. From the operations
section, this maximum loop frequency in con-
tinuous conduction mode is:
1
V
OUT
(
V
IN
- V
OUT
)
F
LP
K
ON
*
V
IN
*
Data for loop frequency, as measured from
output voltage ripple frequency, can be found in
the typical performance curves.
Layout Considerations
Proper layout of the power and control circuits is
necessary in a switching power supply to obtain
good output regulation with stability and a mini-
mum of output noise. The SP6651A application
circuit can be made very small and reside close to
the IC for best performance and solution size, as
long as some layout techniques are taken into
consideration. To avoid excessive interference
INDUCTORS SURFACE MOUNT
Inductor Specification
Inductance
Manufacturer/Part No.
Series R
I
SAT
(A)
Size
Inductor Type
Manufacturer
(
H)
LxW(mm)
Ht. (mm)
Website
10
Sumida CDRH5D28-100
0.048
1.30
5.7 x 5.5
3.0
Shielded Ferrite Core
sumida.com
10
TDK RLF5018T-100MR94
0.056
0.94
5.6 x 5.2
2.0
Shielded Ferrite Core
tdk.com
10
Coilcraft DO1608C-103
0.160
1.10
6.6 x 4.5
2.9
Unshielded Ferrite Core coilcraft.com
10
Coilcraft LPO6013-103
0.300
0.70
6.0 x 5.4
1.3
Unshielded Ferrite Core coilcraft.com
6.8
Sumida CDRH5D28-6R8
0.081
1.12
4.7 x 4.5
3.0
Shielded Ferrite Core
sumida.com
6.8
TDK RLF5018T-6R8M1R1
0.47
1.10
5.6 x 5.2
2.0
Shielded Ferrite Core
tdk.com
6.8
Coilcraft DO1608C-682
0.130
1.20
6.6 x 4.5
2.9
Unshielded Ferrite Core coilcraft.com
6.8
Coilcraft LPO6013-103
0.200
0.60
6.0 x 5.4
1.3
Unshielded Ferrite Core coilcraft.com
CAPACITORS - SURFACE MOUNT
Capacitor Specification
Capacitance
Manufacturer/Part No.
ESR
RippleCurrent
Size
Voltage
Capacitor Type
Manufacturer
(
F)
(max)
(A) @ 45
C
LxW(mm) Ht. (mm)
(V)
Website
22
TDK C3216X5R0J226M
0.002
3.00
3.2 x 1.6
1.6
6.3
X5R Ceramic
tdk.com
22
SANYO 6APA22M
0.040
1.90
7.3 x 4.3
2.0
6.3
POSCAP
sanyovideo.com
47
TDK C3225X5R0J46M
0.002
4.00
3.2 x 1.6
1.6
6.3
X5R Ceramic
tdk.com
47
SANYO 6TPA47M
0.040
1.90
6.0 x 3.2
2.8
6.3
POSCAP
sanyovideo.com
Table 2 Component Selection
Note: Components highlighted in bold are those used on the SP6651A Evaluation Board.
13
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
APPLICATION INFORMATION: Continued
Figure 19. SP6651A PCB Component Sample Layout
Figure 20. SP6651A PCB Top Sample Layout
Figure 21. SP6651A PCB Bottom Sample Layout
between the SP6651A high frequency converter
and the other active components on the board,
some rules should be followed. Refer to the typical
application schematic on page 1 and the sample
PCB layout shown in the following figures to
illustrate how to layout a SP6651A power supply.
Avoid injecting noise into the sensitive part of
circuit via the ground plane. Input and output
capacitors conduct high frequency current through
the ground plane. Separate the control and power
grounds and connect them together at a single
point. Power ground plane is shown in the figure
titled PCB top sample layout and connects the
ground of the C
OUT
capacitor to the ground of the
C
IN
capacitor and then to the PGND pin 10. The
control ground plane connects from pin 9 GND to
ground of the C
VIN
capacitor and the R
I
ground
return of the feedback resistor. These two separate
control and power ground planes come together in
the figure titled PCB top sample layout where
SP6651A pin 9 GND is connected to pin 10
PGND.
Power loops on the input and output of the con-
verter should be laid out with the shortest and
widest traces possible. The longer and narrower
the trace, the higher the resistance and inductance
it will have. The length of traces in series with the
capacitors increases its ESR and ESL and reduces
their effectiveness at high frequencies. Therefore,
put the 1
F bypass capacitor as close to the V
IN
and
GND pins of the converter as possible, the 22
F
C
IN
close to the P
VIN
pin and the 22
F output
capacitor as close to the inductor as possible. The
external voltage feedback network R
F
, R
I
and
feedforward capacitor C
F
should be placed very
close to the FB pin. Any noise traces like the LX
pin should be kept away from the voltage feedback
network and separated from it by using power
ground copper to minimize EMI.
14
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
PACKAGE: 10 PIN MSOP
10-PIN MSOP
0.07 - -
L1
L
R1
1
R
1
1
Seating Plane
1
E1
2
E/2
e1
e
E
D
Gauge Plane
L2
A2
A
A1
b
- - 1.10
0.00 - 0.15
Dimensions in (mm)
10-PIN MSOP
JEDEC MO-187
(BA) Variation
0.75 0.85 0.95
0.17 - 0.27
0.08 - 0.23
3.00 BSC
4.90 BSC
3.00 BSC
0.4 0.60 0.80
0.95 REF
0.25 BSC
10
0.07 - -
0 - 8
A
A1
A2
b
c
D
E
E1
L
L1
L2
N
R
R1
5 - 15
1
MIN NOM MAX
e1
e
2.00 BSC
0.50 BSC
c
WITH PLATING
BASE METAL
(b)
Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)
0 0
Section B-B
B
B
15
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
PACKAGE: 10 PIN DFN
Top View
D/2
Bottom View
D
E
D2
E/2
E2
e
b
L
1
2
Pin 1 identifier to be located within this shaded area.
Terminal #1 Index Area (D/2 * E/2)
K
Side View
A
A1
A3
DIMENSIONS
in
(mm)
10 Pin DFN
(JEDEC MO-229,
VEED-5 VARIATION)
A
A1
A3
b
D
E2
E
e
D2
L
K
0.80 0.90 1.00
0.20 REF
2.20
-
2.70
3.00 BSC
1.40 -
1.75
0.30
0.40 0.50
0.20
0.18
0.25 0.30
3.00 BSC
0.50 PITCH
SYMBOL
MIN NOM MAX
0
0.02 0.05
-
-
10 PIN DFN
16
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator Copyright 2004 Sipex Corporation
Corporation
ANALOG EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
ORDERING INFORMATION
Part Number Top Mark Operating Temperature Range
Package Type
SP6651AEU..............6651AEU....................... -40
C to +85
C ................................................... 10 Pin MSOP
SP6651AEU/TR........6651AEU ............ ........... -40
C to +85
C .................................................. 10 Pin MSOP
SP6651AER.............6651AER......................... -40
C to +85
C ..................................................... 10 Pin DFN
SP6651AER/TR.......6651AER......................... -40
C to +85
C ..................................................... 10 Pin DFN
/TR = Tape and Reel
Pack quantity is 2500 for MSOP and 3,000 for DFN.
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6651AEU/TR = standard; SP6651AEU-L/TR = lead free
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