1
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
SP690T/S/R, SP802T/S/R,
SP804T/S/R, and SP805T/S/R
3.0V/3.3V Low Power Microprocessor
Supervisory with Battery Switch-Over
The SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices are a family of
microprocessor (
P) supervisory circuits that integrate a myriad of components involved in
discrete solutions to monitor power-supply and battery-control functions in
P and digital
systems. The series will significantly improve system reliability and operational efficiency
when compared to discrete solutions. The features of the SP690T/S/R, SP802T/S/R,
SP804T/S/R and SP805T/S/R devices include a watchdog timer, a
P reset and backup-
battery switchover, and power-failure warning; a complete
P monitoring and watchdog
solution. The series is ideal for 3.0V or 3.3V applications in portable electronics, computers,
controllers, and intelligent instruments and is a solid match for designs where it is critical to
monitor the power supply to the
P and it's related digital components. Refer to Sipex's
SP690A/692A/802L/802M/805L/805M series for similar devices designed for +5V systems.
s
RESET and RESET Outputs
s
Reset asserted down to V
CC
= 1V
s
Reset Time Delay - 200ms
s
Watchdog Timer - 1.6 sec timeout
s
40
A Maximum V
CC
Supply Current
s
1
A Maximum Battery Supply Current
s
Power Switching
50mA Output in V
CC
Mode (1.5
)
10mA Output in Battery Mode (15
)
s
Battery Can Exceed V
CC
in Normal Operation
s
Precision Voltage Monitor for Power-Fail
or Low-Battery Warning
s
Available in 8 pin SO and DIP packages
s
Pin Compatible Upgrades to
MAX690T/S/R, MAX802T/S/R,
MAX804T/S/R, MAX805T/S/R
DESCRIPTION
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SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
2
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect
reliability and cause permanent damage to the device.
V
CC
..................................................................................-0.3V to 6.0V
V
BATT
................................................................................-0.3V to 6.0V
All Other Inputs (NOTE 1).................................-0.3V to the higher of V
CC
or V
BATT
Continuous Input Current:
V
CC
..................................................................................100mA
V
BATT
..................................................................................20mA
GND..................................................................................20mA
WDI, PFI...........................................................................20mA
Continuous Output Current:
RESET, RESET, PFO.........................................................20mA
V
OUT
......................................................................................100mA
Power Dissipation per Package:
8pin NSOIC (derate 6.14mW/
C above +70
C)..............500mW
8pin PDIP (derate 11.8mW/
C above +70
C)..............1,000mW
Storage Temperature........................................-65
C to +160
C
Lead Temperature(soldering,10sec).............................................+300
C
ESD Rating........................................................4KV Human Body Model
SPECIFICATIONS
V
CC
= 3.17V to 5.50V for the SP690T/SP80_T, V
CC
= 3.02V to 5.50V for the SP690S/SP80_S, V
CC
= 2.72V to 5.50V for the SP690R/SP80_R, V
BATT
= 3.60V, and
T
A
= T
MIN
to T
MAX
unless otherwise noted. Typical values taken at T
AMB
= +25
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SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
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n
e
r
r
u
C
t
u
p
n
I
I
D
W
1
-
1
0
.
0
1
A
V
<
V
0
C
C
V
5
.
5
<
d
l
o
h
s
e
r
h
T
t
u
p
n
I
I
F
P
0
0
2
.
1
5
2
2
.
1
5
2
.
1
5
2
.
1
0
0
3
.
1
5
7
2
.
1
V
V
,
_
5
0
8
/
_
0
9
6
P
S
C
C
<
V
,
V
6
.
3
I
F
P
g
n
il
l
a
f
V
,
_
4
0
8
/
_
2
0
8
P
S
C
C
<
V
,
V
6
.
3
I
F
P
g
n
il
l
a
f
t
n
e
r
r
u
C
t
u
p
n
I
I
F
P
5
2
-
1
0
.
0
5
2
A
n
V
,
s
i
s
e
r
e
t
s
y
H
I
F
P
H
F
P
0
1
0
2
V
m
V
,
g
n
i
s
i
r
I
F
P
C
C
<
V
6
.
3
SPECIFICATIONS (continued)
V
CC
= 3.17V to 5.50V for the SP690T/SP80_T, V
CC
= 3.02V to 5.50V for the SP690S/SP80_S, V
CC
= 2.72V to 5.50V for the SP690R/SP80_R, V
BATT
= 3.60V, and
T
A
= T
MIN
to T
MAX
unless otherwise noted. Typical values taken at T
AMB
= +25
O
C.
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
4
SPECIFICATIONS (continued)
V
CC
= 3.17V to 5.50V for the SP690T/SP80_T, V
CC
= 3.02V to 5.50V for the SP690S/SP80_S, V
CC
= 2.72V to 5.50V for the SP690R/SP80_R, V
BATT
= 3.60V, and
T
A
= T
MIN
to T
MAX
unless otherwise noted. Typical values taken at T
AMB
= +25
O
C.
NOTE 1: The following are tested at V
BATT
= 3.6V and V
CC
= 5.5V: V
CC
supply current, watchdog
functionality, logic input leakage, PFI functionality, and the RESET and RESET states. The state of
RESET or RESET and PFO is tested at V
CC
= V
CC
(min).
NOTE 2: Tested V
BATT
= 3.6V, V
CC
= 3.5V and 0V.
NOTE 3: Leakage current into the battery is tested under the following worst-case conditions: V
CC
= 5.5V, V
BATT
= 1.8V and at V
CC
= 1.5V, V
BATT
= 1.0V.
NOTE 4: "-" equals the battery-charging current, "+" equals the battery-discharging current.
NOTE 5: When V
SW
> V
CC
> V
BATT
, V
OUT
remains connected to V
CC
until V
CC
drops below V
BATT
. The
V
CC
-to-V
BATT
comparator has a small 25mV typical hysteresis to prevent oscillation.
NOTE 6: When V
BATT
> V
CC
> V
SW
, V
OUT
remains connected to V
CC
until V
CC
drops below the battery
switch threshold, V
SW
.
NOTE 7: V
OUT
switches from V
BATT
to V
CC
when V
CC
rises above the reset threshold, independent of
V
BATT
. Switchover back to V
CC
occurs at the exact voltage that causes RESET to go HIGH (on the
SP804_ and SP805_ RESET goes LOW). Switchover occurs 200ms prior to reset.
NOTE 8: The reset threshold tolerance is wider for V
CC
rising than for V
CC
falling to accommodate the
10mV typical hysteresis, which prevents internal oscillation.
NOTE 9: SP690_ and SP802_ devices only.
NOTE 10: SP804_ and SP805_ devices only.
NOTE 11: The leakage current into or out of the RESET pin is tested with RESET asserted (RESET
output high impedance).
5
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
INTERNAL BLOCK DIAGRAM
1.25V
BATTERY
SWITCHOVER
CIRCUIT
PFI
WATCHDOG
TIMER
RESET
GENERATOR
V
CC
BATTERY
SWITCHOVER
COMPARATOR
RESET
COMPARATOR
1.25V
1.25V
WDI
V
BATT
PFO
RESET / RESET*
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
*SP804T/S/R and SP805T/S/R only
POWER-FAIL
COMPARATOR
7
5
4
6
8
2
V
OUT
GND
3
1
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
6
PIN ASSIGNMENTS
Pin 1 --V
OUT
-- Output Supply Voltage for
CMOS RAM. When V
CC
is above the
reset threshold, V
OUT
connects to V
CC
through a P-channel MOSFET switch.
When V
CC
falls below the V
SW
and
V
BATTERY
, V
BATTERY
connects to V
OUT
.
Connect to V
CC
if no battery is used.
Pin 2 -- V
CC
-- +5V Supply Input
Pin 3 -- GND -- Ground reference for all
signals
Pin 4 -- PFI -- Power-Fail Comparator Input.
When PFI is less than 1.25V or when V
CC
falls below the V
SW
, PFO goes LOW,
otherwise PFO remains HIGH. Connect
to GND if unused.
Pin 5 -- PFO -- Power-Fail Comparator
Output. Leave open if unused.
Pin 6 -- WDI -- Watchdog Input. If WDI
remains HIGH or LOW for 1.6 seconds,
the internal watchdog timer triggers a
reset. The internal watchdog timer clears
when reset is asserted or WDI sees a
rising or falling edge. The watchdog
function cannot be disabled.
Pin 7 for SP690_/802_ only -- Active-LOW
Reset Output. -- Whenever RESET is
triggered by a watchdog timeout, it goes
LOW for 200ms. It stays LOW whenever
V
CC
is below the reset threshold and re-
mains LOW for 200ms after V
CC
rises
above the reset threshold or when the
watchdog triggers a reset.
Pin 7 for SP804_/805_ only -- Active-HIGH
Open-Drain Reset Output. -- The
inverse operation of RESET.
Pin 8 -- V
BATTERY
-- Backup-Battery Input.
When V
CC
falls below V
SW
and V
BATTERY
,
V
OUT
switchesfrom V
CC
to V
BATTERY
.
When V
CC
rises above the reset threshold,
V
OUT
reconnects to V
CC
. V
BATTERY
may
exceed V
CC
. Connect to V
CC
if no battery
is used.
V
OUT
V
CC
GND
PFI
V
BATTERY
RESET / RESET*
WDI
PFO
1
2
3
4
5
6
7
8
*
SP804T/S/R and SP805T/S/R only
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
PINOUT
7
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
TYPICAL CHARACTERISTICS
(T
AMB
= 25
o
C, unless otherwise noted)
Figure 1. V
CC
Supply Current vs. Temperature (Normal
Mode)
Figure 3. PFI Threshold vs. Temperature
Figure 2. Battery Supply Current vs. Temperature
Figure 4. V
BATTERY
to V
OUT
ON-Resistance vs. Temperature
Figure 5. V
CC
to V
OUT
On-Resistance vs. Temperature
Figure 6. Reset Threshold vs. Temperature
40
35
30
25
20
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
Suppl
y Current (
A)
10000
1000
100
10
1
0.1
-60 -35 -10 15 40 65 90 115 140
Temperature (
o
C)
Batter
y Suppl
y
Current (nA)
1.262
1.26
1.258
1.256
1.254
1.252
1.25
1.248
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
PFI Threshold
(V
olts)
30
25
20
15
10
5
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
V
B
A
TTER
Y
to
V
OUT
On-Resistance (
)
3.5
3
2.5
2
1.5
1
0.5
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
On Resistance (
)
3.15
3.13
3.11
3.09
3.07
3.05
-60 -35 -10 15 40 65 90 115 140
Temperature (
o
C)
Reset Threshold
(V
olts)
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
8
Figure 7. Reset Output Resistance vs. Temperature
Figure 9. Battery Current vs. V
CC
Voltage
Figure 8. Reset Timeout vs. Temperature
Figure 10. Reset-Comparator Propagation Delay vs.
Temperature
Figure 11. V
CC
to V
OUT
Vs. Output Current
Figure 12. V
BATTERY
to V
OUT
Vs. Output Current
1E-06
decade
/div
1E-14
5.000
.0000
V3 .5000/div (V)
1000
100
10
1
1
10
100
I
OUT
(mA)
V
oltage Drop (mV) [ V
CC
- V
OUT
]
V
CC
= 4.5V
V
BATTERY
= 0V
1000
100
10
1
1
10
I
OUT
(mA)
V
oltage Drop (mV) [ V
BA
TTER
Y
- V
OUT
]
V
CC
= 0V
V
BATTERY
= 4.5V
14000
12000
10000
8000
6000
4000
2000
0
-60 -35 -10 15 40 65 90 115 140
Temperature (
o
C)
RESET Output Resistance (
)
185
180
175
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
Reset Timeout
(mS)
30
26
22
18
14
10
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
Pr
opa
gation Dela
y (
s)
9
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
Figure 15A. SP690A RESET Response Time
Figure 15B. Circuit for the SP690A/802L RESET
Response Time
GND
RESET
V
CC
30pF
V
CC
10K
T
A
= +25 C
Figure 13A. SP690A RESET Output Voltage vs.
Supply Voltage
Figure 13B. Circuit for the SP690A/802L RESET
Output Voltage vs. Supply Voltage
Figure 14A. SP805L RESET Output Voltage vs.
Supply Voltage
Figure 14B. Circuit for the SP805 RESET Output
Voltage vs. Supply Voltage
GND
RESET
V
CC
330pF
V
CC
10K
V
BATTERY
V
CC
GND
RESET
V
CC
330pF
V
CC
2K
RESET
V
BATTERY
= 0V
T
A
= +25 C
0V
0V
1
T
V
CC
2V
div
1 sec / div
RESET
0
3.1V
[ T ]
T
1
1V / div
3.1V
2V
RESET
10
S / div
V
CC
0V
0V
1
1V
div
RESET
V
CC
1 sec /div
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
10
Figure 16A. SP805L RESET Response Time
Figure 16B. Circuit for the SP805 RESET Response
Time
GND
RESET
V
CC
330pF
V
CC
10K
V
CC
Figure 17B. Circuit for the Power-Fail Comparator
Response Time (fall)
Figure 17A. Power-Fail Comparator Response Time (fall)
30pF
1K
PFO
+1.25V
+5V
PFI
V
CC
= +5V
T
A
= +25 C
Figure 18A. Power-Fail Comparator Response Time (rise)
Figure 18B. Circuit for the Power-Fail Comparator
Response Time (rise)
30pF
1K
PFO
+1.25V
+5V
PFI
V
CC
= +5V
T
A
= +25 C
0V
PFI
1.3V
1.2V
5V
500ns / div
PFO
V
CC
= 5V
= 0
V
BATTERY
2
1
T
1
1.3V
1.2V
V
CC
= 5
= 0
V
BATTERY
PFI
PFO
500ns / div
0V
[ T ]
1
T
V
CC
1V / div
3.1V
2V
10
s / div
RESET
11
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
Figure 19. Timing Diagram
V
CC
0V
3.0V or 3.3V
t
WP
RESET
RESET*
PFO
V
OUT
3.0V or 3.3V
3.0V or 3.3V
V
SW
V
BATTERY
=3.6V
V
RST
V
SW
0V
V
BATTERY
=PFI=3.6V
I
OUT
=0mA
*SP804T/S/R and SP805T/S/R only; Reset externally pulled up to V
CC
.
0V
0V
3.0V or 3.3V
3.0V or 3.3V
0V
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
12
THEORY OF OPERATION
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices are microprocessor
(
P) supervisory circuits that monitor the power
supplied to digital circuits such as microproces-
sors, microcontrollers, or memory. The series is
an ideal solution for portable, battery-powered
equipment that requires power supply monitoring.
Implementing this series will reduce the
number of components and overall complexity.
The watchdog functions of this product family
will continuously oversee the operational status
of a system.
These
P supervisory circuits are not short-
circuit protected. Shorting V
OUT
to ground -
excluding power-up transients such as charging
a decoupling capacitor - may potentially damage
these devices. Decouple both V
CC
and V
BATTERY
pins to ground by placing 0.1
F capacitors as
close to the device as possible. The operational
features and benefits of the SP690T/S/R,
SP802T/S/R, SP804T/S/R and SP805T/S/R
devices are described in more detail below.
Reset Output
The microprocessor's (
P's) reset input starts
the
P in a known state. When the
P is in an
unknown state, it should be held in reset. The
SP690T/S/R, SP802T/S/R, SP804T/S/R and
SP805T/S/R devices assert reset during
power-up and prevent code execution errors
during power-down or brownout conditions.
RESET is guaranteed to be a logic LOW for 0V
< V
CC
< V
RST
, provided that V
BATTERY
is greater
than 1V. Without a backup battery, RESET is
guaranteed valid for V
CC
> 1V. Once V
CC
exceeds the reset threshold, an internal timer
keeps RESET low for the reset timeout period.
After this period, RESET goes HIGH, as seen in
Figure 19.
If a brownout condition occurs and V
CC
dips
below the reset threshold, RESET goes LOW.
Each time RESET is triggered, it stays low for
the reset timeout period. Any time V
CC
goes
below the reset threshold, the internal timer
restarts.
FEATURES
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices provide four key
functions:
1. A battery backup switch for CMOS RAM,
CMOS microprocessors, or other logic.
2. A reset output during power-up, power-down
and brownout conditions.
3. A reset pulse if the optional watchdog timer
has not been toggled within a specified time.
4. A 1.25V threshold detector for power-fail
warning, low battery detection, or to monitor a
power supply other than 3.3V or 3.0V.
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices differ in their reset-
voltage threshold levels and are ideally suited
for applications in automotive systems, intelligent
instruments, and battery-powered computers and
controllers. The series is a solid match for
designs where it is critical to monitor the
power supply to the
P and it's related digital
components.
Figure 20. Typical Operating Circuit
GND
GND
RESET
NMI
I/O LINE
V
CC
pin 7*
PFO
WDI
V
OUT
BUS
V
CC
GND
V
BATTERY
R
2
R
1
Unregulated
Regulated +3.3V or +3.0V
V
CC
0.1
F
PFI
DC
Lithium
Battery
3.6V
P
CMOS
RAM
0.1
F
RESET for the SP690T/S/R and the SP802T/S/R
RESET for the SP804T/S/R and the SP805T/S/R
*
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
13
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
The watchdog timer can also initiate a reset.
Refer to the
Watchdog Input
section.
The SP804T/S/R and SP805T/S/R active-HIGH
RESET output is open drain and the inverse
of the SP690T/S/R and SP802T/S/R RESET
outputs.
RESET is also triggered by a watchdog timeout.
If WDI remains either high or low for a period
that exceeds the watchdog timeout period (1.6
sec), RESET pulses low for 200mS. As long as
RESET is asserted, the watchdog timer remains
cleared. When RESET comes high, the watch-
dog resumes timing and must be serviced within
1.6sec. If WDI is tied high or low, a RESET
pulse is triggered every 1.8sec (t
WD
plus t
RS
).
Reset Threshold
The SP690T and SP805T devices are designed
for 3.3V systems with a
5% power-supply
tolerance and a 10% system tolerance. Except
for watchdog faults, reset will not assert as long
as the power supply remains above 3.15V (3.3V
- 5%). Reset is guaranteed to assert before the
power supply falls below 3.0V.
The SP690S and SP805S devices are designed
for 3.3V
10% power supplies. Except for
watchdog faults, they are guaranteed not to
assert reset as long as the supply remains above
3.0V (3.3V - 10%). Reset is guaranteed to
assert before the power supply fails below 2.85V
(V
CC
- 14%).
The SP690R and SP805R devices are optimized
for monitoring 3.0V
10% power supplies. Reset
will not occur until V
CC
falls below 2.7V (3.0V
- 10%), but is guaranteed to occur before the
supply falls below 2.55V (3.0V - 15%).
The SP802T/S/R and SP804T/S/R devices are
respectively similar to the SP690T/S/R and
SP805T/S/R devices with tightened reset
and power-fail threshold tolerances.
Watchdog Input
The watchdog circuit monitors the
P's activity.
If the
P does not toggle the watchdog input
(WDI) within 1.6sec, a reset pulse is triggered.
The internal 1.6sec timer is cleared by either a
reset pulse or by a transition (LOW-to-HIGH or
HIGH-to-LOW) at WDI. If WDI is tied HIGH
or LOW, a RESET pulse is triggered every
1.8sec (t
WD
plus t
RS
).
As long as reset is asserted, the timer remains
cleared and does not count. As soon as reset is
de-asserted, the timer starts counting. Unlike
the 5V SP690A series, the watchdog function
cannot be disabled.
Power-Fail Comparator
The power-fail comparator can be used as an
under-voltage detector to signal the failing of a
power supply (it is completely separate from the
rest of the circuitry and does not need to be
dedicated to this function). The PFI input is
compared to an internal 1.25V. If PFI is less than
V
PFT
, PFO goes low.
The power-fail comparator turns off and PFO
goes LOW when V
CC
falls below V
SW
on
power-down. The power-fail comparator turns
on as V
CC
crosses V
SW
on power-up. If the
comparator is not used, connect PFI to ground
and leave PFO unconnected.
Backup-Battery Switchover
In the event of a brownout or power failure, it
may be necessary to preserve the contents of
RAM. With a backup battery installed at
V
BATTERY
, the devices automatically switch
RAM to backup power when V
CC
fails.
This family of
P supervisors (designed for
3.3V and 3V systems) doesn't always connect
V
BATTERY
to V
OUT
when V
BATTERY
is greater
than V
CC
. V
BATTERY
connects to V
OUT
(through
a 15
switch) when V
CC
is below V
SW
and
V
BATTERY
is greater than V
CC
.
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
14
Switchover at V
SW
(2.40V) ensures that battery-
backup mode is entered before V
OUT
gets too
close to the 2.0V minimum required to reliably
retain data in CMOS RAM. Switchover at higher
V
CC
voltages would decrease backup-battery
life. When V
CC
recovers, switchover is deferred
until V
CC
rises above the reset threshold, V
RST
,
to ensure a stable supply. V
OUT
is connected to
V
CC
through a 1.5
PMOS power switch.
Using a High Capacity Capacitor as a
Backup Power Source
Figure 21 shows two ways to use a High Value
Capacitor as a backup power source. The High
Value Capacitor may be connected through a
diode to the 3V input as in Figure 21A or, if a
5V supply is also available, the High Value
Capacitor may be charged up to the 5V supply
as in Figure 21B allowing a longer backup
period. Since V
BATTERY
can exceed V
CC
while V
CC
is above the reset threshold, there are no
special precautions when using these
P
supervisors with a High Value Capacitor.
Operation Without a Backup Power
Source
These
P supervisors were designed for
battery-backed applications. If a backup power
source is not used, connect both VBATTERY
and V
OUT
to V
CC
. Since there is no need to
switch over to any backup power source, V
OUT
does not need to be switched. A direct connec-
tion to V
CC
eliminates any voltage drops across
the switch which may push V
OUT
below V
CC
.
Replacing the Backup Battery
If V
BATTERY
is decoupled with a 0.1
F capacitor
to ground, the backup battery can be removed
while V
CC
remains valid without danger of
triggering RESET/RESET. As long as V
CC
stays above V
SW
, battery-backup mode cannot
be entered.
Adding Hysteresis to the Power-Fail
Comparator
The power-fail comparator has a typical input
hysteresis of 10mV. This is sufficient for most
applications where a power-supply line is being
monitored through an external voltage divider
(refer to the
Monitoring an Additional Power
Supply
section).
If additional noise margin is desired, connect a
resistor between PFO and PFI as shown in
Figure 22A. Select the ratio of R1 and R2 such
that PFI sees 1.25V when V
IN
falls to its trip
point (V
TRIP
). R3 adds the hysteresis and will
typically be more than 10 times the value of R1
or R2. The hysteresis window extends both
above (V
H
) and below (V
L
) the original trip
point (V
TRIP
).
V
CC
3.0V or 3.3V
GND
V
BATTERY
V
OUT
CONNECT TO
STATIC RAM
TO
P
0.1F
CONNECT
pin 7*
1N4148
V
CC
3.0V or 3.3V
GND
V
BATTERY
V
OUT
RESET for the SP690T/S/R and the SP802T/S/R
RESET for the SP804T/S/R and the SP805T/S/R
*
CONNECT TO
STATIC RAM
TO
P
0.1F
CONNECT
pin 7*
1N4148
+5V
Figure 21. Using a High Capacity Capacitor as a Backup Power Source
A)
B)
15
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
Connecting an ordinary signal diode in series
with R3, as in Figure 22B, causes the lower trip
point (V
L
) to coincide with the trip point without
hysteresis (V
TRIP
), so the entire hysteresis
window occurs above V
TRIP
. This method pro-
vides additional noise margin without compro-
mising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is
useful for accurately detecting when a voltage
falls past a threshold.
Figure 22A. Adding Additional Hysteresis to the Power-Fail Comparator.
Figure 22B. Shifting the Additional Hysteresis above V
PFT
The current through R1 and R2 should be at least
1
A to ensure that the 25nA (max over extended
temperature range) PFI input current does not
shift the trip point. R3 should be larger than
10k
so it does not load down the PFO pin.
Capacitor C1 adds additional noise rejection.
Figure 23. Using the Power-Fail Comparator to Monitor an Additional Power Supply
V
IN
R1
R2
+
R3
TO
P
PFI
PFO
GND
V
CC
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
PFO
0V
0V
V
L
V
TRIP
V
H
V
IN
V
IN
R1
R2
+
R3
TO
P
PFI
PFO
GND
V
CC
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
PFO
0V
0V
V
TRIP
V
H
V
IN
*OPTIONAL
V
TRIP
= V
PFT
V
H
=
V
L
= R1
WHERE V
PFT
= 1.25V
V
PFH
= 10mV
R1 + R2
R2
(
)
V
PFT
+ V
PFH
(
)
R1
( )
1 + 1 + 1
R1 R2 R3
(
)
V
PFT
[ (
1 + 1 + 1
R1 R2 R3
)
- V
CC
R3
]
V
TRIP
= V
PFT
V
L
= R1
WHERE V
PFT
= 1.25V
V
PFH
= 10mV
V
D
= DIOD FORWARD VOLTAGE DROP
R1 + R2
R2
(
)
V
PFT
+ V
PFH
[
(
1 + 1 + 1
R1 R2 R3
)
- (V
CC -
V
D
)
R3
]
(
)
*C1
*C1
R1
R2
V-
PFI
PFO
GND
V
CC
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
PFO
V
L
V
TRIP
V-
V
IN
R1
R2
PFI
PFO
GND
V
CC
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
PFO
V
TRIP
V
H
V
IN
V
CC
0V
3.0V OR 3.3V
V
CC
V
TRIP
= R2
V
L
= R2
WHERE V
PFT
= 1.25V
V
PFH
= 10mV
NOTE: V
TRIP
IS NEGATIVE
V
PFT
+ V
PFH
(
)
1 + 1
R1 R2
(
)
V
PFT
[ (
1 + 1
R1 R2
)
- V
CC
R3
]
[
- V
CC
R1
]
V
TRIP
= V
PFT
V
H
=
R1 + R2
R2
(
)
V
PFT
+ V
PFH
(
R1 + R2
R2
)
(
)
A.)
B.)
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
16
Figure 24. Interfacing to Microprocessors with
Bidirectional RESET I/O
V
CC
GND
V
CC
GND
RESET
RESET
4.7K
P
Buffered RESET connects to System Components
Monitoring an Additional Power Supply
These
P supervisors can monitor either positive
or negative supplies using a resistor voltage
divider to PFI. PFO can be used to generate an
interrupt to the
P, as seen in Figure 23.
Interfacing to
Ps with Bidirectional
Reset Pins
Any
Ps with bidirectional reset pins, such as
the Motorola 68HC11 series, can interface with
the SP690_ and the SP802_ RESET outputs.
For example, if the RESET output is driven
HIGH and the
P wants to pull it LOW,
indeterminate logic levels may result. To correct
this, connect a 4.7k
resistor between the
RESET output and the
P reset I/O, as in
Figure 24. Buffer the RESET output to other
system components.
Negative-Going V
CC
Transients
While issuing resets to the
P during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to short-
duration negative-going V
CC
transients
(glitches). It is usually undesirable to reset the
P when V
CC
experiences only small glitches.
Figure 25 shows maximum transient duration
vs. reset-comparator overdrive, for which reset
pulses are not generated. The data was generated
using negative-going V
CC
pulses, starting at
3.3V and ending below the reset threshold by
the magnitude indicated (reset comparator
overdrive). The graph shows the maximum pulse
width a negative-going V
CC
transient may
typically have without causing a reset pulse to
be issued. As the amplitude of the transient
increases (i.e. goes farther below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a V
CC
transient that goes
100mV below the reset threshold and lasts for
40
s or less will not cause a reset pulse to be
issued. A 100nF bypass capacitor mounted close
to the V
CC
pin provides additional transient
immunity.
Figure 25. Maximum Transient Duration without
Causing a Reset Pulse vs. Reset Comparator Overdrive
1nF Capacitor
V
OUT
TO GND
Above Line
RESET
Generated
NO
RESET
Generated
17
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
D
ALTERNATE
END PINS
(BOTH ENDS)
D1 = 0.005" min.
(0.127 min.)
E
PACKAGE: PLASTIC
DUALINLINE
(NARROW)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
A = 0.210" max.
(5.334 max).
E1
C
L
A2
A1 = 0.015" min.
(0.381min.)
B
B1
e = 0.100 BSC
(2.540 BSC)
e
A
= 0.300 BSC
(7.620 BSC)
A2
B
B1
C
D
E
E1
L
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.735/0.775
(18.669/19.685)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.355/0.400
(9.017/10.160)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
22PIN
8PIN
14PIN
16PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
1.145/1.155
(29.083/29.337)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.780/0.800
(19.812/20.320)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
18PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.880/0.920
(22.352/23.368)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
20PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.980/1.060
(24.892/26.924)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
18
D
E
H
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(NARROW)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
8PIN
A
A1
L
B
e
h x 45
A
A1
B
D
E
e
H
h
L
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249
0.014/0.019
(0.35/0.49)
0.189/0.197
(4.80/5.00)
0.150/0.157
(3.802/3.988)
0.050 BSC
(1.270 BSC)
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
14PIN
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249)
0.013/0.020
(0.330/0.508)
0.337/0.344
(8.552/8.748)
0.150/0.157
(3.802/3.988)
0.050 BSC
(1.270 BSC)
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
16PIN
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249)
0.013/0.020
(0.330/0.508)
0.386/0.394
(9.802/10.000)
0.150/0.157
(3.802/3.988)
0.050 BSC
(1.270 BSC)
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
19
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP690TCN......................................................0
C to +70
C......................................................8-Pin NSOIC
SP690TCP......................................................0
C to +70
C.........................................................8-Pin PDIP
SP690TEN.....................................................-40
C to +85
C....................................................8-Pin NSOIC
SP690TEP.....................................................-40
C to +85
C.......................................................8-Pin PDIP
SP690SCN......................................................0
C to +70
C......................................................8-Pin NSOIC
SP690SCP......................................................0
C to +70
C.........................................................8-Pin PDIP
SP690SEN.....................................................-40
C to +85
C....................................................8-Pin NSOIC
SP690SEP.....................................................-40
C to +85
C.......................................................8-Pin PDIP
SP690RCN......................................................0
C to +70
C......................................................8-Pin NSOIC
SP690RCP......................................................0
C to +70
C.........................................................8-Pin PDIP
SP690REN.....................................................-40
C to +85
C....................................................8-Pin NSOIC
SP690REP.....................................................-40
C to +85
C.......................................................8-Pin PDIP
SP802TCN........................................................0
C to +70
C....................................................8-Pin NSOIC
SP802TCP........................................................0
C to +70
C.......................................................8-Pin PDIP
SP802TEN.......................................................-40
C to +85
C..................................................8-Pin NSOIC
SP802TEP.......................................................-40
C to +85
C.....................................................8-Pin PDIP
SP802SCN........................................................0
C to +70
C....................................................8-Pin NSOIC
SP802SCP........................................................0
C to +70
C.......................................................8-Pin PDIP
SP802SEN.......................................................-40
C to +85......................................................8-Pin NSOIC
SP802SEP.......................................................-40
C to +85
C.....................................................8-Pin PDIP
SP802RCN........................................................0
C to 0
C........................................................8-Pin NSOIC
SP802RCP........................................................0
C to+70
C...................................................... 8-Pin PDIP
SP802REN.......................................................-40
C to +85
C..................................................8-Pin NSOIC
SP802REP.......................................................-40
C to +85
C.....................................................8-Pin PDIP
SP804TCN.......................................................0
C to +70
C.....................................................8-Pin NSOIC
SP804TCP.......................................................0
C to +70
C........................................................8-Pin PDIP
SP804TEN......................................................-40
C to +85
C...................................................8-Pin NSOIC
SP804TEP......................................................-40
C to +85
C......................................................8-Pin PDIP
SP804SCN.......................................................0
C to +70
C.....................................................8-Pin NSOIC
SP804SCP.......................................................0
C to +70
C........................................................8-Pin PDIP
SP804SEN......................................................-40
C to +85
C...................................................8-Pin NSOIC
SP804SEP......................................................-40
C to +85
C......................................................8-Pin PDIP
SP804RCN.......................................................0
C to +70
C.....................................................8-Pin NSOIC
SP804RCP.......................................................0
C to +70
C........................................................8-Pin PDIP
SP804REN......................................................-40
C to +85
C...................................................8-Pin NSOIC
SP804REP......................................................-40
C to +85
C......................................................8-Pin PDIP
SP805TCN........................................................0
C to +70
C....................................................8-Pin NSOIC
SP805TCP........................................................0
C to +70
C.......................................................8-Pin PDIP
SP805TEN.......................................................-40
C to +8C.................................................. ..8-Pin NSOIC
SP805TEP.......................................................-40
C to +85
C.....................................................8-Pin PDIP
SP805SCN........................................................0
C to+70
C.....................................................8-Pin NSOIC
SP805SCP........................................................0
C to +70
C.......................................................8-Pin PDIP
SP805SEN.......................................................-40
C to +85
C..................................................8-Pin NSOIC
SP805SEP.......................................................-40
C to +85
C.....................................................8-Pin PDIP
SP805RCN........................................................0
C to +70
C....................................................8-Pin NSOIC
SP805RCP........................................................0
C to +70
C.......................................................8-Pin PDIP
SP805REN.......................................................-40
C to +85
C..................................................8-Pin NSOIC
SP805REP.......................................................-40
C to +85
C.....................................................8-Pin PDIP
Please consult the factory for pricing and availability on a Tape-On-Reel option.
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
20
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
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