ST
Sitronix
ST2108
PRELIMINARY
8 BIT Microcontroller with 1M bytes ROM
Notice: This is not a final specification. Some parameters are subject to change.
Ver 0.36
1
/
46
2002-03-14
1
1
.
.
F
F
E
E
A
A
T
T
U
U
R
R
E
E
S
S
n
Totally static 65C02S CPU
n
ROM: 1M x 8-bit
n
RAM: 4K x 8-bit
n
Stack: Up to 128-level deep
n
Operation voltage: 2.4V ~ 3.4V
n
I/O ports
- 24 CMOS bidirectional bit programmable I/O pins
- 8 output pins (shared with LCD common output)
- Bit programmable pull-up for input pins
- Hardware de-bounce option for Port-A
n
Low voltage detector
n
Timer/Counter:
- Two 8-bit timer/16-bit event counter
- One 8-bit Base timer
n
6 Prioritized interrupt sources
- External interrupt (edge triggered)
- Timer0 interrupt
- Timer1 interrupt
- Base timer interrupt
- Port-A[7~0] interrupt (transition triggered)
- DAC reload interrupt
n
Dual clock source with warm-up timer
- Crystal oscillator
.........
32.768K Hz
- RC oscillator
...............
500K~4M Hz
- Resonator oscillator (code option)
...............
455K~4M Hz
n
Direct memory access (DMA)
- Block-to-Block move
- Block to Single port
n
LCD controller
- 16-level contrast control
- 1752 (73x24) dots (1/24 duty)
- 1168 (73x16) dots (1/16 duty)
n
Programmable sound generator (PSG)
- Two channels with three playing modes
- Tone/noise generator
- 16-level volume control
n
PWM DAC: Three modes up to 8-bit resolution
n
Three power down modes:
- WAI0 mode
- WAI1 mode
- STP mode
2
2
.
.
G
G
E
E
N
N
E
E
R
R
A
A
L
L
D
D
E
E
S
S
C
C
R
R
I
I
P
P
T
T
I
I
O
O
N
N
The ST2108 is a W65C02S based 8-bit microcontroller
designed with CMOS silicon gate technology. This single chip
microcontroller is useful for translator, databank and other
consumer applications. It integrates with SRAM, mask program
ROM, LCD controller/drivers, I/O ports, timers, PSG and PWM
DAC. This chip also builds in dual oscillators for the chip
performance enhancement.
Sitronix
ST2108
Ver 0.36
2/46
2002-03-14
3
3
.
.
P
P
A
A
D
D
D
D
I
I
A
A
G
G
R
R
A
A
M
M
4
4
.
.
B
B
L
L
O
O
C
C
K
K
D
D
I
I
A
A
G
G
R
R
A
A
M
M
CLOCK
GENERATOR
LCD
RAM
ROM
TIMER
PSG
DAC
PORT
CPU
LOW
VOLTAGE
DETECTOR
ST2108
72
74 73
76
77
78
79
80
81
82
83
75
84
86 85
88
89
91
92
93
94
95
87
96
97
99 98
101
102
103
105
106
107
108
100
38
36
37
34
33
32
31
30
29
28
27
35
26
24 25
22
21
20
19
18
17
16
15
23
14
13
11 12
9
8
7
6
5
4
3
2
10
1
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
71 70
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
110
111
128
129
130
131
132
133
134
135
136
137
138
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM19
COM20
COM21
COM22
COM23
SEG4
SEG5
SEG6
SEG7
SEG0
SEG1
SEG2
SEG3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG33
SEG36
SEG37
SEG34
SEG35
SEG40
SEG41
SEG38
SEG39
SEG44
SEG45
SEG42
SEG43
SEG48
SEG49
SEG46
SEG47
SEG52
SEG53
SEG50
SEG56
SEG54
SEG55
SEG71
COM18
SEG69
SEG70
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
OSCX
O
OSCX
I
OSCI
XI
O
VDD
CUP1+
CUP1-
VP
V1
V2
V3
V4
RESET
109
LPDET
104
SEG17
SEG18
SEG19
SEG13
SEG14
SEG15
SEG16
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG28
SEG29
SEG26
SEG27
SEG32
SEG30
SEG31
SEG72
PB2
SEG67
SEG65
SEG66
SEG68
SEG63
SEG61
SEG62
SEG64
SEG59
SEG57
SEG58
SEG60
90
SEG51
TEST
V5
Sitronix
ST2108
Ver 0.36
3/46
2002-03-14
5
5
.
.
P
P
A
A
D
D
D
D
E
E
S
S
C
C
R
R
I
I
P
P
T
T
I
I
O
O
N
N
Pin No.
Designation
I/O
Description
19~91
SEG 0~72
O
LCD segment output
103~92, 7~18
COM 0~23
O
LCD common output
105
PA0 / INTX
I/O
I
I
I
Port-A bit programmable I/O
Edge-trigger Interrupt.
Transition-trigger Interrupt
Programmable Timer1 clock source
106~112
PA 1~7
I/O
I
Port-A bit programmable I/O
Transition-trigger Interrupt
113,114
PB 0, 1
I/O
O
Port-B bit programmable I/O
PSG/DAC Output
115~120
PB 2~7
I/O
Port-B bit programmable I/O
121~128
PC 0~7
I/O
Port-C bit programmable I/O
131
RESET
I
Pad reset input (low active)
134
GND
P
Ground Input and chip substrate
136
VDD
P
Power supply
129, 130
OSCXO, OSCXI
I/O
OSC I/O pin. For 32768Hz crystal used.
132
OSCI
I
RC oscillator pin, had to be connected to external resistor
133
XIO
I
Resonator input pin
135
NC
6
VP
O
LCD pumping voltage output
137
CUP1+
I/O
Pump capacitance 1 positive edge
138
CUP1-
I/O
Pump capacitance 1 negative edge
5~1
V1~V5
I
External LCD voltage supply
104
TEST
I
Test pin for chip test, normal to NC.
Note: I = input, O = output, I/O = input/output, P = power.
Sitronix
ST2108
Ver 0.36
4/46
2002-03-14
6
6
.
.
C
C
P
P
U
U
Register Model
7
0
A
7
0
Y
7
0
X
7
0
PCH
PCL
7
0
1
S
Accumulator A
Index Register Y
Index Register X
Program Counter PC
Stack Pointer S
Accumulator (A)
The Accumulator is a general-purpose 8-bit register that stores
the results of most arithmetic and logic operations. In addition,
the accumulator usually contains one of the two data words
used in these operations.
Index Registers (X,Y)
There are two 8-bit Index Registers (X and Y), which may be
used to count program steps or to provide and index value to be
used in generating an effective address. When executing an
instruction, which specifies indexed addressing, the CPU
fetches the OP code and the base address, and modifies the
address by adding the index register to it prior to performing the
desired operation. Pre or post-indexing of indirect addresses is
possible.
Stack Pointer (S)
The Stack Pointer is an 8-bit register, which is used to control
the addressing of the variable-length stack. It's range from
100H to 1FFH total for 256 bytes (128 level deep). The stack
pointer is automatically increment and decrement under control
of the microprocessor to perform stack manipulations under
direction of either the program or interrupts (IRQ). The stack
allows simple implementation of nested subroutines and
multiple level interrupts. The stack pointer is initialized by the
user's software.
Program Counter (PC)
The 16-bit Program Counter register provides the address,
which step the microprocessor through sequential program
instructions. Each time the microprocessor fetches and
instruction from program memory, the lower byte of the program
counter (PCL) is placed on the low-order bits of the address bus
and the higher byte of the program counter (PCH) is placed on
the high-order 8 bits. The counter is increment each time an
instruction or data is fetched from program memory.
Status Register (P)
The 8-bit Processor Status Register contains seven status flags.
Some of these flags are controlled by program; others may be
controlled both by the program and the CPU. The instruction set
contains a member of conditional branch instructions that are
designed to allow testing of these flags. Refer to TABLE 6-1
TABLE 6-1 Status register (P)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N
V
1
B
D
I
Z
C
Bit 7: N : Signed flag by arithmetic
1 = Negative
0 = Positive
Bit 3: D : Decimal mode flag
1 = Decimal mode
0 = Binary mode
Bit 6: V : Overflow of signed Arithmetic flag
1 = Negative
0 = Positive
Bit 2: I : Interrupt disable flag
1 = Interrupt disable
0 = Interrupt enable
Bit 1: Z : Zero flag
1 = Zero
0 = Non zero
Bit 4: B : BRK interrupt flag
1 = BRK interrupt occur
0 = Non BRK interrupt occur
Bit 0: C : Carry flag
1 = Carry
0 = Non carry
Sitronix
ST2108
Ver 0.36
5/46
2002-03-14
7
7
.
.
M
M
E
E
M
M
O
O
R
R
Y
Y
C
C
O
O
N
N
F
F
I
I
G
G
U
U
R
R
A
A
T
T
I
I
O
O
N
N
7.1 Memory map
ST2108 has total 1M bytes ROM and 4K RAM inside. This ROM can be used as data memory or program memory. PRR is the
Program ROM Bank Pointer Register and DRR is the Data ROM Bank Pointer Register. The data ROM address area in ST2108 is
from $8000 to $FFFF (32K bytes) and program ROM address is from $4000 to $7FFF(16K bytes).
.
Control Register Region
0000
003F
SRAM Region
0040
0FFF
LCD RAM Mapping Region
1000
1148
NO USE
Program ROM Region
(PPR)
16K Bytes
Data ROM Region
(DRR)
32K Bytess
1149
3FFF
4000
7FFF
8000
FFFF
00000~
03FFF
04000~
07FFF
08000~
0BFFF
0C000~
0FFFF
F0000~
F3FFF
F4000~
F7FFF
F8000~
FBFFF
FC000~
FFFFF
PRR = 01H
PRR = 00H
PRR = 03H
DRR = 01H
PRR = 02H
PRR = 3EH
DRR = 1FH
PRR = 3FH
PRR = 3CH
DRR = 1EH
PRR = 3DH
The Interrupt Vector Region
1M Bytes ROM
CPU Memory Mapping
NO USE
007F
0080
DRR = 00H
7.2 ROM
7.2.1 Bank Description
Setting corresponding value to register PRR(program memory) or DRR(data memory) when user wants uses different memory bank.
FIGURE 7-1 ROM Control Registers ($31~$32)
Address
Register
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PRR
$31
RW
PRR7
PRR6
PRR5
PRR4
PRR3
PRR2
PRR1
PRR0
DRR
$32
RW
DRR7
DRR6
DRR5
DRR4
DRR3
DRR2
DRR1
DRR0
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