DATA SHEET

CX74038: 2.6 GHz/800 MHz Dual Fractional-N/lnteger-N

Frequency Synthesizer

APPLICATIONS

Multi-slot GSMTM/DCS
PCS/W-CDMA
Portable communication systems
Dual-mode cellular telephone systems
Spread spectrum receiver
Wireless Local Area Network (LAN) systems
Wireless Routers, Wireless Local Loop (WLL) systems
SATCOM Receivers

FEATURES

2.6 GHz maximum operating frequency
800 MHz maximum IF synthesizer
Supply voltage as low as 2.6 V
Fast frequency settling time with fractional-N operation
Internal fractional spur reduction
Programmable charge pump currents
Digital lock detector
Power saving at lower frequency

Skyworks' CX74038 is a complete low-power 2.6 GHz/800
MHz dual frequency synthesizer. The device provides both
Radio Frequency (RF) channels and Intermediate Frequency (IF)
channels. Fractional-N operation offers low phase noise, fast
settling time, and low spurious tones for RF channels. A
standard integer-N division is used for IF channels. The three-
wire serial interface provides programmable control of the
frequency synthesizer to support dual-conversion transceivers.

The CX74038 has two package options:

A 20-pin Thin Shrink Small Outline Package (TSSOP)
A 24-pin 3.5 × 4.5 mm Chip Scale Package (CSP)

Figure 1 shows a functional block diagram for the CX74038.
The device package and pinout for the 20-pin TSSOP is shown
in Figure 2 and the device package and pinout for the 24-pin
3.5 x 4.5 mm CSP is shown in Figure 3.

Divider

Charge

Pump 1

Divider

Charge

Pump 2

Serial-to Parallel

Interface

MUX

(LD/TEST)

P/P+1

Prescaler

Q/Q+1

Prescaler

P/FD 1

P/FD 2

GND

VDD2_RF

VDD1_RF

GND

CPO_RF

VDD2_IF

VDD1_IF

GND

CPO_IF

SP1

SC1

SP2

SC2

RFIN

FREF

LD_TP

RFINB

IFIN
IFINB

LE
CLK
DAT

C1451

Figure 1. CX74038 Functional Block Diagram

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Data Sheet I CX74038

Technical Description

A dithering disable function is accessible via word 00, data bits
21 and 20. When the RF synthesizer is programmed for
fractional divide values, these bits should be programmed to 1
0 (dithering enable). However, when the RF synthesizer is
programmed to output a frequency which is a whole integer
multiple of the comparison frequency, the synthesizer should
be programmed for dithering disabled (bits set to 11). This
improves the phase noise when operating on integer-N
boundaries. These data bits must be programmed after power-
up, otherwise erroneous device operation may occur. Refer to
the Synthesizer Register Programming section of this
document for bit definitions.

The CX74038 has two package options: the 20-pin TSSOP and
the 24-pin 3.5 x 4.5 mm CSP. The device pinouts are shown in
Figures 1 and 2, respectively.

The CX74038 is a fractional-N frequency synthesizer using a
modulation technique. The fractional-N implementation
provides low in-band noise by having a low division ratio and
fast frequency settling time. In addition, the CX74038 provides
arbitrarily fine frequency resolution with a digital word, so that
the frequency synthesizer can be used to compensate for
crystal frequency drift in the RF transceiver.

Voltage Controlled Oscillator (VCO) Prescalers

Modulator

The VCO prescalers, P/P+1 and Q/Q+1, provide low noise
signal conditioning of the VCO signals. They translate from an
off-chip, single-ended or differential signal to an on-chip
differential signal. By changing the PS bit, the RF synthesizer
has the option to use either the 8/9 or the 16/17 prescaler
depending on the desired operational frequency. The
maximum frequency is 2.6 GHz and 2.0 GHz for the 16/17 and
8/9 prescalers, respectively. The IF synthesizer has a fixed
16/17 prescaler with a maximum frequency of 800 MHz.

The primary limitation of conventional fractional-N synthesizers
is the fractional spurs. The CX74038

technique improves

the synthesizer performance by randomizing the spurs using
internal dithering.

Serial Interface

The serial interface is a versatile three-wire interface
consisting of three pins: serial clock (CLK), serial input (DAT),
and Latch Enable (LE). It enables the CX74038 to operate in a
system where one or multiple masters and slaves are present.
For more information, refer to the Synthesizer Register
Programming section of this document.

RF and IF Dividers

The CX74038 provides programmable dividers that control the
prescaler and supply the divided VCO signals to the charge
pump phase detectors. Programmable ratios on the RF
fractional-N synthesizer ranging from 256 to 2

are possible

with the 16/17 prescaler, and from 64 to 2

with the 8/9

prescaler. The IF integer-N synthesizer has a programmable
divide ratio ranging from 256 to 2

LE is set low before the rising edge of the 1

clock (CLK) pulse

and is held low until after the last (22

) clock pulse, at which

time LE is set high. The data word is transferred to the correct
device register when LE is high (there are four internal
registers selected by the D1 and D0 bits of the 22-bit
data/address word). If the LE signal does not go high, the data
does not get transferred to the register. Between each 22-bit
data/address word transfer, LE must be pulsed to make the
transfer to the specific device register. Data/address transfer is
MSB first.

Reference Frequency Dividers

The reference signal can be divided by a ratio of 1 to 7 for the
RF reference divider (R1) and from 1 to 8192 for the IF
reference divider (R2). The input frequency for the reference
signal can be as high as 50 MHz.

LE must not go high when CLK is high; otherwise, the data
word is not transferred to the register. LE must only go high
after CLK has gone low.

Phase Detectors and Charge Pumps

The CX74038 uses a separate charge pump phase detector for
each synthesizer. The IF and RF Phase/Frequency Detector
(PFD) can have a programmable charge pump current from 0.4
mA to 1.6 mA and 120

µA to 480 µA, respectively.

After the transfer of the last 22-bit data/address word, the LE
signal can be left in a high state. It does not have to be
returned to a low state unless another data/address word
transfer is required.

For optimum performance, the divided reference frequency
presented at the phase detector input must not exceed 9 MHz
using the RF 16/17 prescaler synthesizer mode, 15 MHz using
the RF 8/9 prescaler, or 2 MHz for the IF synthesizer mode.
The comparison frequency is also limited by the desired
frequency divided by the minimum divide ratio.

It is not necessary to write all four data/address words to the
synthesizer to make a change in programming. For example, if
a change to the Lock Detect (LD) pin operation is desired, only
word 00 has to be changed.

Registers

The charge-pump can be programmed to high impedance (Hi-
Z) state for open-loop VCO modulation use.

The CX74038 includes four 22-bit registers that can be
programmed independently in any order. Bits D0 and D1
represent the register addresses. For more information on
registers, addresses, and format, refer to the Synthesizer
Register Programming section of this document.

Lock Detection

The output of the IF/RF dividers (R1, N1, R2, N2) and lock
detectors for both synthesizers can be multiplexed to the LD
pin. When programmed for lock detection, the CX74038

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Data Sheet I CX74038

provides an active low output to indicate the out-of-lock
condition. When locked, the LD pin is high.

Power Down

The CX74038 supports a number of power-down modes
through the serial interface. Both IF and RF synthesizer blocks
can be powered down, powered up individually, or both
powered up using the EN bits (see the Synthesizer Register
Programming section of this document). The CX74038 is
enabled at power up by default.

Synthesizer Register Programming

IF Integer-N Synthesizer

The N2 17-bit divider ratio is calculated using the following
equation:

REF

-------------

As with all integer-N synthesizers, the minimum step size is
related to the divided reference frequency, F

REF

RF Fractional-N Synthesizer

The N1 divider ratio is calculated using the following equation:

REF

------------- N1

Total

where: N1

Total

= N1 + 3.5 + FN + ME

FN sets the fractional-N modulo up to 256 modulo, as
calculated by:

1
2

--- D

-----

... + D

-----

where: D

represents the bit locations within the register field.

The fractional modulo can be extended up to 2

using the

modulo extender (ME), if required, as shown by the following
equation:

-----

--------

... +

--------

Because the way the

modulator is implemented in the

CX74038, the number 3.5 must be added to the division
number to obtain the final division ratio. If the integer field of
the N divider shows a non-integer number, the desired
frequency or the division fraction portion needs to be adjusted.

Sample calculations for two fractional-N applications are
shown in Figure 4.

Electrical and Mechanical Specifications

Signal pin assignments and functional pin descriptions are
specified in Table 1 (20-pin TSSOP) and Table 2 (24-pin CSP).

The CX74038 absolute maximum ratings are provided in
Table 3. The recommended operating conditions are specified
in Table 4. Electrical characteristics are defined in Table 5 and
Table 6 provides the register descriptions.

Figure 5 illustrates the CX74038 serial data word format and
Figure 6 illustrates the CX74038 serial data input timing
diagram.

Package dimensions for the CX74038 are shown in Figure 7
(20-pin TSSOP) and Figure 8 (24-pin 3.5 x 4.5 mm CSP).
Figure 9 provides the tape and reel dimensions for the 20-pin
TSSOP package (for 3.5 x 4.5 mm CSP tape and reel
dimensions, contact a Skyworks' sales office).

Electrostatic Discharge Information

The CX74038 is an electrostatic sensitive device. Observe
precautions when handling.

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Case 1: To achieve a desired F

VCO_RF

frequency of 2440.2 MHz using a crystal frequency of 24 MHz with operation

of the synthesizer in RF mode using the 16/17 prescaler (PS = 1). R1 is set to divide by 3 to achieve a
comparison frequency of 8 MHz, since the maximum internal reference frequency is 9 MHz. Divide the operating
frequency by the internal reference frequency to determine the value of N

Total

= 2440.2 MHz

8 MHz

305.025

Subtract 3.5 from N

Total

and remove the fractional portion of the result to determine N1:

305.025 3.5 = 301.525

N1 = 301 (decimal)

Fractional portion = 0.525 (decimal)

N1 = 000100101101 (binary)

-----------D

Multiply the fractional portion of N1 by 256 and remove the fractional portion of the result to determine FN:

0.525 × 256 = 134.4

FN = 134 (decimal)

FN = 10000110 (binary)

-------D

Divide FN by 256 to determine the actual fractional portion:

134 = 0.5234375
256

Subtract this result from the fractional portion of N1:

0.525 0.5234375 = 0.0015625

Multiply this result by 2097152 (the 21-bit

modulator value 2

) and remove the fractional portion to determine

the ME:

0.0015625 × 2097152 = 3276.8

ME = 3276 (decimal)

ME = 0110011001100 (binary)

--------------D

In this example, N1 is greater than 256, the minimum divide ratio for the 16/17 prescaler.

C1454

Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)

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Case 2: To achieve a desired F

VCO_RF

frequency of 1400 MHz using a crystal frequency of 13 MHz with operation

of the synthesizer in RF mode using the 8/9 prescaler (PS = 0). The crystal frequency does not need to be
divided further, since the maximum comparison frequency is 15 MHz. Divide the operating frequency by the
internal reference frequency to determine the value of N

Total

= 1400 MHz

13 MHz

=107.6923076

Subtract 3.5 from N

Total

and remove the fractional portion of the result to determine N1:

107.6923076 3.5 = 104.1923076

N1 = 104 (decimal)

Fractional portion = 0.1923076 (decimal)

N1 = 000001101000 (binary)

------------D

Multiply the fractional portion of N1 by 256 and remove the fractional portion of the result to determine FN:

0.1923076 × 256 = 49.230746

FN = 49 (decimal)

FN = 00110001 (binary)

-------D

Divide FN by 256 to determine the actual fractional portion:

49 = 0.1914962

256

Subtract this result from the fractional portion of N1:

0.1923076 0.1914062 = 0.0009014

Multiply this result by 2097152 (the 21-bit

modulator value 2

) and remove the fractional portion to determine

the ME:

0.0009014 × 2097152 = 1890.3728

ME = 1890 (decimal)

ME = 0011101100010 (binary)

--------------D

In this example, N1 is greater than 64, the minimum divide ratio for the 8/9 prescaler.

C1455

Figure 4. Fractional-N Applications: Sample Calculation (2 of 2)

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Table 2. CX74038 Signal Definition (24-Pin 3.5 x 4.5 mm CSP)

Pin #

Pin Name

I/O

Definition

1 VDDA_RF

-- Power

supply

for RF analog circuits

VDDC_RF

Power supply for RF charge pump

CPO_RF

RF charge pump output

4 GND

-- Ground

RFIN

RF prescaler input

RFINB

RF prescaler complementary input

7 GND

-- Ground

FREF

Reference divider input

9 GND

-- Ground

LD_TP

Multiplexed output from lock detectors and
dividers

11 NC

-- No

connection

12 NC

-- No

connection

CLK

Serial interface clock input

DAT

Serial interface data input

15 LE

I Serial

interface load enable input

16 GND

-- Ground

IFINB

IF prescaler complementary input

IFIN

IF prescaler input

19 GND

-- Ground

CPO_IF

IF charge pump output

VDDA_IF

Power supply for IF analog circuits

VDDD

Power supply for digital circuits

23 NC

-- No

connection

24 NC

-- No

connection

Table 3. Absolute Maximum Ratings

Parameter Min

Max

Units

Power supply with GND = 0 V

0.3

+3.6

Voltage on any pin

GND

Storage temperature

+150

°C

Note:

Exposure to maximum rating conditions for extended periods may reduce
device reliability. There is no damage to device with only one parameter
set at the limit and all other parameters set at or below their nominal
conditions.

Data Sheet I CX74038

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Table 4. Recommended Operating Conditions

Parameter Min

Max

Units

Power supply

2.6

3.6

Operating junction temperature

+100

°C

Operating ambient temperature 40

+85

°C

Table 5. Electrical Characteristics (1 of 2)

(VDD = 2.7 V, T

= 25

°C, unless otherwise noted)

Parameter Symbol

Test

Conditions Minimum Typical Maximum Units

Supply

voltage

RF/IF

2.6 2.7 3.6 V

Supply current

RF @2.5 GHz

RF/IF @2.5 GHz-RF

Standby

6.5

1.9

8.2

µA

Operating input frequency

RF (PS = 1)

RF (PS = 0)

(@ 40

°C to +85 °C)

0.1

2.6

2.0

800

GHz

MHz

Reference input frequency

MHz

Phase detector frequency

RF (PS = 1)

RF (PS = 0)

(@ 40

°C to +85 °C)

MHz

Prescaler input sensitivity

(@ 40

°C to +85 °C)

+ 6

dBm

Prescaler input impedance

RF @ 2.5 GHz

IF @ 480 MHz

30 j25

200 j190

Reference oscillator sensitivity

0.3

VDD

Vp-p

In-band phase noise @10 kHz
offset (Note 1)

RF @ 2.5 GHz

IF @ 480 MHz

(@ 40

°C to +85 °C)

dBc/Hz

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Table 5. Electrical Characteristics (2 of 2)

(VDD = 2.7 V, T

= 25

°C, unless otherwise noted)

Parameter Symbol

Test

Conditions Minimum Typical Maximum Units

Charge pump output current

RF, V

= VDD/2

IF, V

= VDD/2

15%

120

240

360

480

0.4

0.8

1.2

1.6

+15%

µA
µA
µA
µA

Charge pump leakage current

0.5 < V

< VDD 0.5

0.3 < V

< VDD 0.3

0.2

0.5

Charge pump sink vs. source
mismatch

= VDD/2

+10

Charge pump current vs.
voltage/temperature

0.5 < V

< VDD 0.5

0.3 < V

< VDD 0.3

+20

High level digital I/O voltage

0.7 VDD

Low level digital I/O voltage

0.3 VDD

Serial clock HIGH time

CKH

Serial clock LOW time

CKL

Data set-up time to clock rising-
edge

DSU

Data hold time to clock rising-
edge

DHD

LE pulse width

LEW

Clock falling-edge to LE rising
edge

CLE

LE falling-edge to clock rising-
edge

LEC

Note 1: RF output frequency = 2.5 GHz, comparison frequency = 8 MHz, loop BW = 35 kHz, and charge pump current = 480 mA.

IF output frequency = 480 MHz, comparison frequency = 200 kHz, loop BW = 10 kHz, and charge pump current = 1.6 mA.

Data Sheet I CX74038

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Table 6. CX74038 Register Descriptions (1 of 2)

Symbol Function

Description

Address bits [1:0]

SC2

IF synthesizer charge-pump
output current [3:2]

Bit[3:2] selects the IF synthesizer charge pump output
current:

bit 3 bit 2

Selects 0.4 mA charge pump output current

Selects 0.8 mA charge pump output current

Selects 1.2 mA charge pump output current

Selects 1.6 mA charge pump output current

Test mode [6:4]

Bit[6:4] sets the test mode:

bit 6 bit 5 bit 4

0 multiplexes Ndiv output of IF SX to LD

output

1 multiplexes Rdiv output of IF SX to LD

output

0 multiplexes lock detect output of IF SX to LD

output

1 multiplexes ANDed lock detect of both SX to

output

0 multiplexes Ndiv output of RF SX to LD

output

1 multiplexes Rdiv output of RF SX to LD

output

0 multiplexes lock detect output of RF SX to

output

1 Hi-Zs the charge-pump output of RF SX

IF synthesizer reference divider
[19:7]

Bit[19:7] sets the IF synthesizer 13-bit reference divider ratio

RF synthesizer fractional-N mode
selection [21:20] (Note 1)

Bit[21:20] sets the RF synthesizer fractional-N mode:

bit 21 bit 20

0 0 Reserved
0 1 Reserved
1

Fractional-N mode with dithering

Fractional-N mode without dithering

Address bits [1:0]

SP1

RF synthesizer phase detector
output polarity [2]

Bit[2] sets the polarity of the RF synthesizer phase detector
output:

0 Sets phase detector output for negative VCO gain
1 Sets phase detector output for positive VCO gain

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Table 6. CX74038 Register Descriptions (2 of 2)

Symbol Function

Description

SC1

RF synthesizer charge-pump
output current [4:3]

Bit[4:3] sets the RF synthesizer charge pump output current:

bit 4 bit 3

0 0 Selects

120

µA charge pump output current

0 1 Selects

240

µA charge pump output current

1 0 Selects

360

µA charge pump output current

1 1 Selects

480

µA charge pump output current

RF synthesizer prescaler selection
[5]

Bit[5] selects the RF synthesizer prescaler:

0 Selects 8/9 prescaler
1 Selects 16/17 prescaler

RF synthesizer reference divider
[8:6]

Bit[8:6] sets the RF synthesizer 3-bit reference divider ratio

RF synthesizer modulo extender
[21:9]

Bit[21:9] extends the RF synthesizer's fractional modulo up
to 2,097,152 (optional)

Address bits [1:0]

SP2

IF synthesizer phase detector
output polarity [2]

Bit[2] sets the IF synthesizer phase detector output:

0 Sets phase detector output for negative VCO gain
1 Sets phase detector output for positive VCO gain

Enable mode [4:3]

Bit[4:3] enables the RF and/or IF synthesizers:

bit 4 bit 3

Enables both RF SX and IF SX

Enables only RF SX

Enables only IF SX

Sets power-down mode for both RF/IF SX

IF synthesizer main divider [21:5]

Bit[21:5] sets the IF synthesizer 17-bit main divider ratio

Address bits [1:0]

RF synthesizer fractional-N
division [9:2]

Bit[9:2] sets the RF synthesizer fractional-N program up to
256 modulo

RF synthesizer main divider
[21:10]

Bit[21:10] sets the RF synthesizer 12-bit main divider ratio
with a 16/17 prescaler, or an 11-bit main divider ratio with
8/9 prescaler

Note 1: These bits must be programmed after power is applied to the device. Failure to do so may result in

erroneous device operation.

Data Sheet I CX74038

Ordering Information

Model Name

Ordering Part Number

Evaluation Kit Part

Number

CX74038 Frequency Synthesizer, 20-pin TSSOP

CX74038 Frequency Synthesizer, 24-pin CSP

CX74038-12

CX74038-71

PH00-D222

N/A

Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its
customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes
to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no
responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks' Terms
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SkyworksTM products are not intended for use in medical, lifesaving or life-sustaining applications. Skyworks' customers using or selling SkyworksTM products for use in
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The following are trademarks of Skyworks Solutions, Inc.: SkyworksTM, the Skyworks symbol, SPRTM, Single Package RadioTM, and "Breakthrough Simplicity"TM. Product
names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of
their respective owners.

GSMTM, "Global System for Mobile CommunicationsTM," and the GSM logo are trademarks of the GSM Association.

Additional information, posted at www.skyworksinc.com, is incorporated by reference.

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Document Outline

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