SL4502B
System Logic
Semiconductor
SLS
Strobed Hex Inverter/Buffer
High-Voltage Silicon-Gate CMOS
The SL4502B consists of six inverter/buffers with 3-state outputs. A
logic "1" on the OUTPUT ENABLE input produces a high impedance
state in all six outputs. This feature permits common busing of the
outputs, thus simplifying system design. A logic "1" on the
DIRECTION input switches all six outputs to logic "0" if the OUTPUT
ENABLE input is a logic "0".
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
A at 18 V over full package-
temperature range; 100 nA at 18 V and 25
C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4502BN Plastic
SL4502BD SOIC
T
A
= -55
to 125
C for all packages
LOGIC DIAGRAM
PIN 16=V
CC
PIN 8= GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
Output
Enable
Direction
A
Y
L
L
L
H
L
L
H
L
L
H
X
L
H
X
X
Z
Z = high impedance
X = don't care
SL4502B
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Vo ltage (Referenced to GND)
-0.5 to +20
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
10
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
P
D
Power Dissipation per Output Transistor
100
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
3.0
18
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SL4502B
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
-55
C
25
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.5 V
V
OUT
=1 V
V
OUT
=1.5
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
= V
CC
- 0.5V
V
OUT
= V
CC
- 1.0 V
V
OUT
= V
CC
- 1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=GND
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
CC
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
I
IN
Maximum Input
Leakage Current
V
IN
= GND or V
CC
18
0.1
0.1
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
= GND or V
CC
5.0
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
A
I
OL
Minimum Output Low
(Sink) Current
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
5.0
10
15
3.84
9.6
25.2
3.06
7.8
20.4
2.16
5.4
14.4
mA
I
OH
Minimum Output High
(Source) Current
V
IN
= GND or V
CC
U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
5.0
5.0
10
15
-2
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
I
OZ
Maximum Tree-State
Leakage Current
Output in High-Impedance
State
V
IN
= GND or V
CC
V
OUT
= GND or V
CC
18
0.4
0.4
12
A
SL4502B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200k
unless otherwise specified, Input
t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
t
PHL
Maximum Propagation Delay, Input A or
Direction to Output Y (Figure 1)
5.0
10
15
270
120
80
270
120
80
540
240
160
ns
t
PLH
Maximum Propagation Delay, Input A or
Direction to Output Y (Figure 1)
5.0
10
15
380
180
130
380
180
130
760
360
260
ns
t
PHZ
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
R
L
= 1 k
5.0
10
15
120
80
60
120
80
60
240
160
120
ns
t
PZH
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
R
L
= 1 k
5.0
10
15
220
100
80
220
100
80
440
200
160
ns
t
PLZ
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
R
L
= 1 k
5.0
10
15
250
130
110
250
130
110
500
260
220
ns
t
PZL
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
R
L
= 1 k
5.0
10
15
250
110
80
250
110
80
500
220
160
ns
t
TLH
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
t
THL
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
120
60
40
120
60
40
240
120
80
ns
C
IN
Maximum Input Capacitance
-
7.5
pF
C
OUT
Maximum Tree-State Output Capacitance
(Output in High-Impedance State)
-
15
pF
SL4502B
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
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