SL74HCT163
System Logic
Semiconductor
SLS
Presettable Counters
High-Performance Silicon-Gate CMOS
The SL74HCT163 is identical in pinout to the LS/ALS163. The
SL74HCT163 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The SL74HCT163 is programmable 4-bit synchronous counter that
feature parallel Load, synchronous Reset, a Carry Output for cascading
and count-enable controls.
The SL74HCT163 is binary counter with synchronous Reset.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
A
ORDERING INFORMATION
SL74HCT163N Plastic
SL74HCT163D SOIC
T
A
= -55
to 125
C for all packages
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Reset
Load
Enable
P
Enable
T
Clock
Q0
Q1
Q2
Q3
Function
L
X
X
X
L
L
L
L
Reset to "0"
H
L
X
X
P0
P1
P2
P3
Preset Data
H
H
X
L
No change
No count
H
H
L
X
No change
No count
H
H
H
H
Count up
Count
X
X
X
X
No change
No count
X=don't care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enable T
Q0
Q1
Q2
Q3
PIN ASSIGNMENT
SL74HCT163
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
0
500
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SL74HCT163
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
20
A
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA
4.5
3.98
3.84
3.7
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
20
A
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA
4.5
0.26
0.33
0.4
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
5.5
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
5.5
4.0
40
160
A
I
CC
Additional Quiescent
Supply Current
V
IN
= 2.4 V, Any One Input
V
IN
=V
CC
or GND,
Other Inputs
-55
C
25
C to
125
C
mA
I
OUT
=0
A
5.5
2.9
2.4
SL74HCT163
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
C to
-55
C
85
C
125
C
Unit
f
max
Maximum Clock Frequency (Figures 1,6)
30
24
20
MHz
t
PLH
Maximum Propagation Delay, Clock to Q
34
43
51
ns
t
PHL
(Figures 1,6)
41
51
62
ns
t
PLH
Maximum Propagation Delay, Enable T to Ripple
Carry Out (Figures 2,6)
32
40
48
ns
t
PHL
39
49
59
ns
t
PLH
Maximum Propagation Delay, Clock to Ripple
35
44
53
ns
t
PHL
Carry Out (Figures 1,6)
43
54
65
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output,
(Figures 1 and 6)
15
19
22
ns
C
IN
Maximum Input Capacitance
10
10
10
pF
Power Dissipation Capacitance (Per Gate)
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
2
f+I
CC
V
CC
+
I
CC
V
CC
60
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
C to
-55
C
85
C
125
C
Unit
t
su
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
30
38
45
ns
t
su
Minimum Setup Time, Load to Clock (Figure 4)
27
34
41
ns
t
su
Minimum Setup Time, Reset to Clock (Figure 3)
32
40
48
ns
t
su
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 5)
40
50
60
ns
t
h
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 4)
10
13
15
ns
t
h
Minimum Hold Time, Clock to Load (Figure 4)
3
3
3
ns
t
h
Minimum Hold Time, Clock to Reset (Figure 3)
3
3
3
ns
t
h
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 5)
3
3
3
ns
t
rec
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
25
31
38
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
16
20
24
ns
t
w
Minimum Pulse Width, Reset (Figure 4)
16
20
24
ns
t
r,
t
f
Maximum Input Rise and Fall Times (Figure 1)
500
500
500
ns
SL74HCT163
System Logic
Semiconductor
SLS
SL74HCT163
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Test Circuit
SL74HCT163
System Logic
Semiconductor
SLS
V
CC
=Pin 16
GND=Pin 8
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a
combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load
signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to
the Q output of the flip-flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-
flop low.
Figure 7.Expanded logic diagram
SL74HCT163
System Logic
Semiconductor
SLS
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
Figure 8. Timing Diagram
SL74HCT163
System Logic
Semiconductor
SLS
TYPICAL APPLICATIONS CASCADING
Note:When used in these cascaded configurations the clock f
max
guaranteed limits may not apply.
Actual performance will depend on number of stages. This limitation is due to set up times
between Enable (Port) and clock.
Figure 9. N-Bit Synchronous Counters
Figure 10. Nibble Ripple Counter
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