SMSC FDC37C672
Page 1
Rev. 10-29-03
DATASHEET
FDC37C672
Enhanced Super I/O
Controller with Fast IR
Datasheet
Product Features
5 Volt Operation
PC98/99 and ACPI 1.0 Compliant
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
- Shadowed Write-Only Registers for ACPI Compliance
System Management Interrupt, Watchdog Timer
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
- Supports Two Floppy Drives Directly
- Configurable Open Drain/Push-Pull Output Drivers
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for Reduced
Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, Up to Eight IRQ and Three DMA
Options
Floppy Disk Available on Parallel Port Pins
Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data
Rates
- Programmable Precompensation Modes
Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
- Asynchronous Access to Two Data Registers and
One Status Register
- Supports Interrupt and Polling Access
- 8-Bit Counter Timer
- Port 92 Support
- 8042 P12 and P16 Outputs
Serial Ports
- Two Full Function Serial Ports
- High Speed NS16C550A Compatible UARTs with
Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud Programmable Baud
Rate Generator Modem Control Circuitry
- 480 Address and Eight IRQ Options
Infrared Port
- Multiprotocol Infrared Interface
- 128-Byte Data FIFO
- IrDA 1.1 Compliant
- TEMIC/HP Module Support
- Consumer IR
- SHARP ASK IR
- 480 Address, Up to Eight IRQ and Three DMA
Options
Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bidirectional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
- ChiProtect Circuitry for Protection Against Damage
Due to Printer Power-On
- 480 Address, Up to Eight IRQ and Three DMA
Options
ISA Host Interface
- 16-Bit Address Qualification
- 8-Bit Data Bus
- IOCHRDY for ECP and Fast IR
- Three 8-Bit DMA Channels
- Eight Direct Parallel IRQs
- Serial IRQ Option Compatible with Serialized IRQ
Support for PCI Systems
100 Pin QFP and TQFP Packages
Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
Page 2
Rev. 10-29-03
DATASHEET
ORDERING INFORMATION
Order Number(s):
FDC37C672QFP for 100 pin QFP package
FDC37C672TQFP for 100 pin TQFP package
80 Arkay Drive
Hauppauge,
NY
11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
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Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.
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OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
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NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
Page 3
Rev. 10-29-03
PRELIMINARY DATASHEET
FDC37C672 Datasheet Revision History
REVISION LEVEL
AND DATE
SECTION/FIGURE/ENTRY CORRECTION
Rev. 10-29-03
Ordering Information, page 2
Update order numbers for QFP and
TQFP packages.
Rev. 10-28-03
Chapter 3 - Description of Pin Functions, page 12
Added TQFP values.
Rev. 10-28-03
Chapter 4 - Description of Multifunction Pins, page
15
Added TQFP values.
Rev. 10-27-03
Figure 2.2 - FDC37C672 100 Pin TQFP, page 11
Added TQFP pin layout.
Rev. 10-27-03
Figure 23.2 - 100 Pin TQFP Package Outline,
14X14X1.4 Body, 2 MM Footprint, page 173
Added TQFP package outline.
Rev. 10-27-03
Features - Cover
Added TQFP package.
Rev. 06-09-97
Figure 2.1 - FDC37C672 100 Pin QFP, page 10
Pin #90 added to Pin-Out.
Rev. 06-09-97
Section 6.1.4 - Tape Drive Register (TDR), page 24
Updated section.
Rev. 06-09-97
Table 6.3 - Tape Select Bits, page 24
Updated table.
Rev. 06-09-97
Table 19.1 - Configuration Registers, page 123
Updated table.
Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
Page 4
Rev. 10-29-03
DATASHEET
Table of Contents
FDC37C672 Datasheet Revision History .................................................................................................. 3
Chapter 1
General Description................................................................................................................ 9
Chapter 2
Pin Configuration.................................................................................................................. 10
Chapter 3
Description of Pin Functions ................................................................................................ 12
3.1
Buffer Type Descriptions ............................................................................................................................14
Chapter 4
Description of Multifunction Pins .......................................................................................... 15
Chapter 5
Functional Description.......................................................................................................... 17
5.1
Super I/O Registers....................................................................................................................................17
5.2
Host Processor Interface............................................................................................................................17
Chapter 6
Floppy Disk Controller .......................................................................................................... 18
6.1
FDC Internal Registers...............................................................................................................................18
6.1.1
Status Register A (SRA) .....................................................................................................................19
6.1.2
Status Register B (SRB) .....................................................................................................................21
6.1.3
Digital Output Register (DOR).............................................................................................................23
6.1.4
Tape Drive Register (TDR) .................................................................................................................24
6.1.5
Data Rate Select Register (DSR)........................................................................................................26
6.1.6
Main Status Register...........................................................................................................................29
6.1.7
Data Register (FIFO)...........................................................................................................................29
6.1.8
Digital Input Register (DIR) .................................................................................................................31
6.1.9
Configuration Control Register (CCR).................................................................................................33
6.1.10
Status Register Encoding ................................................................................................................34
6.2
RESET .......................................................................................................................................................36
6.2.1
RESET Pin (Hardware Reset).............................................................................................................36
6.2.2
DOR Reset vs. DSR Reset (Software Reset) .....................................................................................36
6.3
Modes of Operation....................................................................................................................................36
6.3.1
PC/AT mode - (IDENT high, MFM a "don't care") ...............................................................................36
6.3.2
PS/2 mode - (IDENT low, MFM high)..................................................................................................36
6.3.3
Model 30 mode - (IDENT low, MFM low) ............................................................................................36
6.4
DMA Transfers ...........................................................................................................................................37
6.5
Controller Phases.......................................................................................................................................37
6.5.1
Command Phase ................................................................................................................................37
6.5.2
Execution Phase .................................................................................................................................37
6.5.3
Data Transfer Termination ..................................................................................................................38
6.5.4
Result Phase.......................................................................................................................................39
Chapter 7
Command Set/Descriptions ................................................................................................. 40
Chapter 8
Instruction Set ...................................................................................................................... 43
8.1
Data Transfer Commands ..........................................................................................................................49
8.1.1
Read Data...........................................................................................................................................49
8.1.2
Read Deleted Data..............................................................................................................................51
8.1.3
Read A Track ......................................................................................................................................51
8.1.4
Write Data ...........................................................................................................................................52
8.1.5
Write Deleted Data..............................................................................................................................53
8.1.6
Verify...................................................................................................................................................53
8.1.7
Format A Track ...................................................................................................................................54
8.2
Control Commands ....................................................................................................................................55
8.2.1
Read ID...............................................................................................................................................55
8.2.2
Recalibrate..........................................................................................................................................55
8.2.3
Seek....................................................................................................................................................56
8.2.4
Sense Interrupt Status ........................................................................................................................56
8.2.5
Sense Drive Status .............................................................................................................................57
8.2.6
Specify ................................................................................................................................................57
8.2.7
Configure ............................................................................................................................................58
8.2.8
Version................................................................................................................................................59
8.2.9
Relative Seek ......................................................................................................................................59
8.2.10
Perpendicular Mode ........................................................................................................................60
8.3
LOCK .........................................................................................................................................................61
Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
Page 5
Rev. 10-29-03
PRELIMINARY DATASHEET
8.4
Enhanced DUMPREG................................................................................................................................61
8.5
Compatibility...............................................................................................................................................62
Chapter 9
Serial Port (UART) ............................................................................................................... 63
9.1
Register Description ...................................................................................................................................63
9.1.1
Receive Buffer Register (RB) ..............................................................................................................64
9.1.2
Transmit Buffer Register (TB) .............................................................................................................64
9.1.3
Interrupt Enable Register (IER) ...........................................................................................................64
9.1.4
FIFO Control Register (FCR) ..............................................................................................................65
9.1.5
Interrupt Identification Register (IIR) ...................................................................................................65
9.1.6
Line Control Register (LCR)................................................................................................................67
9.1.7
Modem Control Register (MCR)..........................................................................................................68
9.1.8
Line Status Register (LSR) .................................................................................................................69
9.1.9
Modem Status Register (MSR) ...........................................................................................................71
9.1.10
Scratchpad Register (SCR) .............................................................................................................72
9.2
Programmable Baud Rate Generator (and Divisor Latches DLH, DLL) .....................................................72
9.2.1
Effect Of The Reset on Register File...................................................................................................72
9.3
FIFO Interrupt Mode Operation ..................................................................................................................72
9.4
FIFO Polled Mode Operation .....................................................................................................................73
9.5
Notes on Serial Port Operation ..................................................................................................................76
9.5.1
FIFO Mode Operation: ........................................................................................................................76
Chapter 10
Infrared Interface .................................................................................................................. 78
Chapter 11
Fast IR.................................................................................................................................. 79
Chapter 12
Parallel Port.......................................................................................................................... 80
12.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes .........................................................................81
12.2
Extended Capabilities Parallel Port.........................................................................................................87
12.2.1
Vocabulary.......................................................................................................................................87
12.3
ISA Implementation Standard.................................................................................................................88
12.3.1
Register Definitions .........................................................................................................................90
12.4
Operation................................................................................................................................................96
12.4.1
Mode Switching/Software Control....................................................................................................96
12.4.2
Data Compression...........................................................................................................................97
12.4.3
Pin Definition ...................................................................................................................................97
12.4.4
ISA Connections..............................................................................................................................97
12.4.5
Interrupts .........................................................................................................................................98
12.4.6
FIFO Operation................................................................................................................................98
12.5
DMA Transfers........................................................................................................................................98
12.5.1
Programmed I/O Mode or Non-DMA Mode .....................................................................................99
12.5.2
Programmed I/O - Transfers from the FIFO to the Host ..................................................................99
12.5.3
Programmed I/O - Transfers from the Host to the FIFO ................................................................100
12.6
Parallel Port Floppy Disk Controller ......................................................................................................100
Chapter 13
Auto Power Management...................................................................................................102
Chapter 14
Serial IRQ...........................................................................................................................106
14.1
Serial Interrupts ....................................................................................................................................106
14.1.1
Timing Diagrams For IRQSER Cycle ............................................................................................106
14.1.2
IRQSER Cycle Control ..................................................................................................................107
14.1.3
IRQSER Data Frame.....................................................................................................................108
14.1.4
Stop Cycle Control.........................................................................................................................108
14.1.5
Latency..........................................................................................................................................109
14.1.6
EOI/ISR Read Latency ..................................................................................................................109
14.1.7
AC/DC Specification Issue ............................................................................................................109
14.1.8
Reset and Initialization ..................................................................................................................109
Chapter 15
GP Index Registers ............................................................................................................110
Chapter 16
Watch Dog Timer ...............................................................................................................111
Chapter 17
8042 Keyboard Controller Description ...............................................................................112
17.1
Keyboard ISA Interface.........................................................................................................................112
17.1.1
Keyboard Data Write .....................................................................................................................113
17.1.2
Keyboard Data Read .....................................................................................................................113
17.1.3
Keyboard Command Write ............................................................................................................113
17.1.4
Keyboard Status Read ..................................................................................................................113
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