SMSC LAN9115

PRODUCT PREVIEW

Revision 0.1 (12-20-04)

Data Brief

PRODUCT FEATURES

LAN9115

Highly Efficient
Single-Chip 10/100
Non-PCI Ethernet
Controller

Highlights

Member of LAN9118 Family; optimized for medium-

performance applications

Easily interfaces to most 16-bit embedded CPU's

Efficient architecture with low CPU overhead

Integrated PHY; supports external PHY via MII

interface

Supports audio & video streaming over Ethernet:

multiple standard-definition (SD) MPEG2 streams

Medium-speed member of LAN9118 Family

(all members are pin-compatible)

Target Applications

Printers, kiosks, security systems

General embedded applications

Audio distribution systems

Basic Cable, satellite, and IP set-top boxes

Video-over IP Solutions, IP PBX & Video Phones

Wireless routers & access points

Digital video recorders

Key Benefits

Non-PCI Ethernet controller for medium-performance

applications

-- 16-bit interface
-- Burst-mode read support

Eliminates dropped packets

-- Internal SRAM can store over 200 packets
-- Supports automatic or host-triggered PAUSE and back-

pressure flow control

Minimizes CPU overhead

-- Supports Slave-DMA
-- Interrupt Pin with Programmable Hold-off timer

Reduces system cost and increases design flexibility

-- SRAM-like interface easily interfaces to most

Embedded CPU's or SoC's

-- Low-cost, low-pin count non-PCI interface for

embedded designs

Reduced-Power Modes

-- Numerous power management modes
-- Wake on LAN
-- Magic packet wakeup
-- Wakeup indicator event signal
-- Link Status Change

Single chip Ethernet controller

-- Fully compliant with IEEE 802.3/802.3u standards
-- Integrated Ethernet MAC and PHY
-- 10BASE-T and 100BASE-TX support
-- Full- and Half-duplex support
-- Full-duplex flow control
-- Backpressure for half-duplex flow control
-- Preamble generation and removal
-- Automatic 32-bit CRC generation and checking
-- Automatic payload padding and pad removal
-- Loop-back modes

Flexible address filtering modes

-- One 48-bit perfect address
-- 64 hash-filtered multicast addresses
-- Pass all multicast
-- Promiscuous mode
-- Inverse filtering
-- Pass all incoming with status report
-- Disable reception of broadcast packets

Integrated Ethernet PHY

-- Auto-negotiation
-- Automatic polarity detection and correction

Efficient host bus interface

-- Simple, SRAM-like interface
-- 16-bit data bus
-- Large, 16Kbyte FIFO memory that can be allocated to

RX or TX functions

-- One configurable Host interrupt

Miscellaneous features

-- Low profile 100-pin TQFP package; green, lead-free

package also available

-- Integral 1.8V regulator
-- General Purpose Timer
-- Support for optional EEPROM
-- Support for 3 status LEDs multiplexed with

Programmable GPIO signals

3.3V Power Supply with 5V tolerant I/O

0 to 70

�C

ORDERING INFORMATION:

LAN9115-MD FOR 100 PIN, TQFP PACKAGE

LAN9115-MT FOR 100 PIN, TQFP PACKAGE (GREEN, LEAD-FREE)

80 Arkay Drive

Hauppauge, NY 11788

(631)

435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

Revision 0.1 (12-20-04)

SMSC LAN9115

PRODUCT PREVIEW

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

SMSC LAN9115

Revision 0.1 (12-20-04)

PRODUCT PREVIEW

General Description

The LAN9115 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded
applications where performance, flexibility, ease of integration and system cost control are required.
The LAN9115 has been architected to provide the best price-performance ratio for any 16-bit
application with medium performance requirements. The LAN9115 is fully IEEE 802.3 10BASE-T and
802.3u 100BASE-TX compliant.

The LAN9115 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave
interface. The simple, yet highly functional host bus interface provides a glue-less connection to most
common 16-bit microprocessors and micro controllers. LAN9115 includes large transmit and receive
data FIFO's to accommodate bandwidth-intensive and high-latency applications. In addition, the
LAN9115 memory buffer architecture allows the most efficient use of memory resources by optimizing
packet granularity.

Applications

The LAN9115 is well suited for many medium-performance embedded applications, including:

Printers, kiosks, POS terminals and security systems

Audio distribution systems

General embedded systems

Basic cable, satellite and IP set-top boxes

Voice-over-IP solutions

Basic Cable, satellite, and IP set-top boxes

The LAN9115 supports numerous power management and wakeup features. The LAN9115 can be
placed in a reduced power mode and can be programmed to issue an external wake signal via several
methods, including Magic Packet, Wake on LAN and Link Status Change. This signal is ideal for
triggering system power-up using remote Ethernet wakeup events. The device can be removed from
the low power state via a host processor command.

The LAN9115 also supports features which reduce or eliminate packet loss. Its internal 16Kbyte SRAM
can hold over 200 received packets. If the receive FIFO gets too full, the LAN9115 can automatically
generate flow control packets to the remote node, or assert back-pressure on the remote node by
generating a network collision.

The diagram shown in Figure 1, "System Block Diagram utilizing the SMSC LAN9115", describes a
typical system configuration of the LAN9115 in a typical embedded environment.

The LAN9115 is designed to be general purpose Ethernet controller that is platform independent. The
LAN9115 consists of four major functional blocks. The four blocks are:

1. 10/100 Ethernet PHY

2. 10/100 Ethernet MAC

3. RX/TX FIFO's

4. Slave Interface Module

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

SMSC LAN9115

Revision 0.1 (12-20-04)

PRODUCT PREVIEW

Figure 2 LAN9115 Internal Block Diagram

10/100

Ethernet

PHY

10/100

Ethernet

MAC

2kB to 14kB

Configurable TX FIFO

2kB to 14kB

Configurable RX FIFO

16-bit SRAM I/F

Interrupt

Controller

GP Timer

PIO Controller

IRQ

FIFO_SEL

3.3V to 1.8V

Regulator

PLL

25MHz

+3.3V

LAN

EEPROM

Controller

EEPROM

(Optional)

RX Status FIFO

TX Status FIFO

MIL - TX Elastic

Buffer - 2K bytes

MIL - RX Elastic

Buffer - 128 bytes

PME - Wakup Indicator

Host Bus Interface

(HBI)

Power Management

Optional

External PHY - MII Interface

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

Revision 0.1 (12-20-04)

SMSC LAN9115

PRODUCT PREVIEW

Pin Description

Figure 3 Pin Configuration

**Denotes a m ultifunction pin
*1 This NC pin can also be tied to VDD_A for backw ard compatibility
*2 This NC pin can also be tied to VSS_A for backw ard com patibility

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

SMSC

LAN9115

100 PIN TQFP

GND_CORE

VREG

VDD_CORE

VSS_PLL

XTAL2
XTAL1

VDD_PLL

VDD_REF

ATEST

RBIAS

VSS_REF

A7
A6
A5
A4
A3
A2
A1

GND_IO

VDD_IO

TX_EN

RXD1
RXD2
RXD3

RX_ER

RXD0
SPEED_SEL
NC
IRQ
NC
PM E
EECLK**
EECS
EEDIO**
GND_CORE
VDD_CORE
D0
D1
D2
VDD_IO
GND_IO
D3
D4
D5
D6
VDD_IO
GND_IO
D7
D8
D9

RX_CL

GND_IO

DD_IO

*
*

COL

GND_IO

DD_IO

TXD

_CL

GND_IO

DD_IO

D15

D14

D13

D12

GND_IO

DD_IO

D11

D10

GPIO2

/
nLED

3
**

GPIO1

/
nLED

2
**

GPIO0

/
nLED

1
**

DD_I

GND_I

ESE

NC*1

NC*2

DD_A

VSS

_
A

EXR

VSS

_
A

DD_A

TPI+

TPI-

DD_A

VSS

_
A

TPO+

TPO-

VSS

_
A

FIFO_

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

SMSC LAN9115

Revision 0.1 (12-20-04)

PRODUCT PREVIEW

Package Outline

Notes:

Controlling Unit: millimeter.

Tolerance on the true position of the leads is � 0.04 mm maximum.

Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm.

Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.

Details of pin 1 identifier are optional but must be located within the zone indicated.

Figure 4 100 Pin TQFP Package Outline

Table 1 100 Pin TQFP Package Parameters

MIN

NOMINAL

MAX

REMARKS

1.60

Overall Package Height

0.05

0.15

Standoff

1.35

1.45

Body Thickness

15.80

16.20

X Span

13.90

14.10

X body Size

15.80

16.20

Y Span

13.90

14.10

Y body Size

0.09

0.20

Lead Frame Thickness

0.45

0.60

0.75

Lead Foot Length

1.00

Lead Length

0.50 Basic

Lead Pitch

Lead Foot Angle

0.17

0.22

0.27

Lead Width

0.08

Lead Shoulder Radius

0.08

0.20

Lead Foot Radius

ccc

0.08

Coplanarity

Электронный компонент: LAN9115

Document Outline