SMSC LAN91C111 Rev. B
Page 1
Rev. 1.4 (12-12-03)
DATASHEET
LAN91C111
10/100 Non-PCI Ethernet Single
Chip MAC + PHY
Datasheet
Product Features
Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and
Transmit FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM
Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer
Memory)
Early TX, Early RX Functions
Built-in Transparent Arbitration for Slave
Sequential Access Architecture
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
3.3V Operation with 5V Tolerant IO Buffers (See
Pin List Description for Additional Details)
Single 25 MHz Reference Clock for Both PHY
and MAC
External 25Mhz-output pin for an external PHY
supporting PHYs physical media.
Low Power CMOS Design
Supports Multiple Embedded Processor Host
Interfaces
- ARM
- SH
- Power PC
- Coldfire
- 680X0, 683XX
- MIPS R3000
3.3V MII (Media Independent Interface) MAC-
PHY Interface Running at Nibble Rate
MII Management Serial Interface
128 Pin QFP Package
128 Pin TQFP Package, 1.0 mm height
Industrial Temperature Range from -40
C to
85
C (LAN91C111i only)
Network Interface
Fully Integrated IEEE 802.3/802.3u-100Base-TX
/ 10Base-T Physical Layer
Auto Negotiation: 10/100, Full / Half Duplex
On Chip Wave Shaping - No External Filters
Required
Adaptive Equalizer
Baseline Wander Correction
LED Outputs (User selectable Up to 2 LED
functions at one time)
- Link
- Activity
- Full Duplex
- 10/100
- Transmit
- Receive
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 Rev. B
Page 2
Rev. 1.4 (12-12-03)
DATASHEET
ORDERING INFORMATION
Order Number(s):
LAN91C111-NC
LAN91C111I-NC
(Industrial Temperature)
for 128 Pin QFP Packages
LAN91C111-NE
(1.0mm height)
LAN91C111I-NE
(Industrial Temperature)
for 128 Pin TQFP Packages
STANDARD MICROSYSTEMS CORPORATION (SMSC) 2003
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the
trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications;
consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is
believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product
descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The
provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
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POSSIBILITY OF SUCH DAMAGES.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 Rev. B
Page 3
Rev. 1.4 (12-12-03)
DATASHEET
LAN91C111 Revisions
REVISION LEVEL
AND DATE
SECTION/FIGURE/ENTRY CORRECTION
Rev. 1.4
12-12-03
Features
Removed "user programmable" under LED
Output features
Rev. 1.3
07-29-03
Section 13.1 - Maximum Guaranteed
Ratings*, page 102
Modified LAN91C111 Temp 0
C to +85C
Rev. 1.3
07-18-03
Section 8.2 - Receive Frame Status, page 44
Modified description of the BROADCAST
bit in Receive Frame Status
Rev. 1.3
07-18-03
Section 8.5 - Bank 0 - Transmit Control
Register, page 47
Modified description of the STP_SQET bit
in TCR Register
Rev. 1.3
07-18-03
Section 8.6 - Bank 0 - EPH Status Register,
page 48
Modified description of SQET bit in EPH
Status Register
Rev. 1.2
09-17-02
Section 8.12 - Bank 1 - Base Address
Register, page 54
Added chart showing decoding of I/O Base
Address 300h
Rev. 1.0
07-01-02
Chapter 5 Description of Pin Functions,
page 14
Add Buffer Type for nLEDA and nLEDB,
Add description of LCLK
Rev.1.0
07-01-02
Section 7.7.12 - Link Integrity &
Autonegotiation, page 37
Modified Auto-Negotiation Enable
Description
Rev. 1.0
07-01-02
Section 7.8 - Reset, page 42
Add Reset Description
Rev. 1.0
07-01-02
Section 8.5 - Bank 0 - Transmit Control
Register, page 47
Add Description for FDUPLX bit
Rev. 1.0
07-01-02
Section 8.10 - Bank 0 - Receive/Phy Control
Register, page 51
Add Description for SPEED, DPLX, ANEG
bits.
Rev. 1.0
07-01-02
Section 8.21 - Bank 2 - Interrupt Status
Registers, page 61
Add Description for Interrupt Status and
Mask bits
Rev. 1.0
07-01-02
Figure 8.2 - Interrupt Structure, page 64
Modified Interrupt Structure Figure
Rev. 1.0
07-01-02
Chapter 9 - PHY MII Registers, page 68
Changed bit name 0 to Reserved
Rev. 1.0
07-01-02
Section 9.10 - Register 20. Reserved -
Structure and Bit Definition, page 79
Reserved bits default at 00A0
Rev. 1.0
07-01-02
Section 10.2 - Typical Flow of Events for
Transmit (Auto Release = 0), page 81
Modified Typical Flow of Event for TX
Rev. 1.0
07-01-02
Section 10.3 - Typical Flow of Events for
Transmit (Auto Release = 1), page 83
Modified Typical Flow of Event for TX
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Rev. 1.4 (12-12-03)
Page 4
SMSC LAN91C111 Rev. B
DATASHEET
TABLE OF CONTENTS
LAN91C111 Revisions .............................................................................................................................. 3
Chapter 1
General Description ........................................................................................................... 7
Chapter 2
Pin Configurations ............................................................................................................. 8
Chapter 3
Block Diagrams ................................................................................................................ 10
Chapter 4
Signal Descriptions........................................................................................................... 13
Chapter 5
Description of Pin Functions ........................................................................................... 14
Chapter 6
Signal Description Parameters........................................................................................ 19
6.1
Buffer Types .................................................................................................................................... 19
Chapter 7
Functional Description..................................................................................................... 20
7.1
Clock Generator Block .................................................................................................................... 20
7.2
CSMA/CD Block .............................................................................................................................. 20
7.2.1
DMA Block............................................................................................................................................20
7.2.2
Arbiter Block .........................................................................................................................................20
7.3
MMU Block ...................................................................................................................................... 21
7.4
BIU Block......................................................................................................................................... 21
7.5
MAC-PHY Interface......................................................................................................................... 21
7.5.1
Management Data Software Implementation........................................................................................22
7.5.2
Management Data Timing ....................................................................................................................22
7.5.3
MI Serial Port Frame Structure .............................................................................................................22
7.5.4
MII Packet Data Communication with External PHY.............................................................................24
7.6
Serial EEPROM Interface................................................................................................................ 25
7.7
Internal Physical Layer .................................................................................................................... 25
7.7.1
MII Disable............................................................................................................................................27
7.7.2
Encoder ................................................................................................................................................27
7.7.3
Decoder ................................................................................................................................................27
7.7.4
Clock and Data Recovery .....................................................................................................................28
7.7.5
Scrambler .............................................................................................................................................29
7.7.6
Descrambler .........................................................................................................................................29
7.7.7
Twisted Pair Transmitter.......................................................................................................................30
7.7.8
Twisted Pair Receiver...........................................................................................................................33
7.7.9
Collision ................................................................................................................................................35
7.7.10
Start of Packet...................................................................................................................................35
7.7.11
End of Packet....................................................................................................................................36
7.7.12
Link Integrity & Autonegotiation.........................................................................................................37
7.7.13
Jabber ...............................................................................................................................................40
7.7.14
Receive Polarity Correction...............................................................................................................40
7.7.15
Full Duplex Mode ..............................................................................................................................41
7.7.16
Loopback...........................................................................................................................................41
7.7.17
PHY Powerdown ...............................................................................................................................42
7.7.18
PHY Interrupt ....................................................................................................................................42
7.8
Reset ............................................................................................................................................... 42
Chapter 8
MAC Data Structures and Registers.............................................................................. 43
8.1
Frame Format In Buffer Memory..................................................................................................... 43
8.2
Receive Frame Status..................................................................................................................... 44
8.3
I/O Space......................................................................................................................................... 45
8.4
Bank Select Register....................................................................................................................... 46
8.5
Bank 0 - Transmit Control Register................................................................................................. 47
8.6
Bank 0 - EPH Status Register......................................................................................................... 48
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 Rev. B
Page 5
Rev. 1.4 (12-12-03)
DATASHEET
8.7
Bank 0 - Receive Control Register.................................................................................................. 49
8.8
Bank 0 - Counter Register............................................................................................................... 50
8.9
Bank 0 - Memory Information Register ........................................................................................... 50
8.10
Bank 0 - Receive/Phy Control Register ....................................................................................... 51
8.11
Bank 1 - Configuration Register................................................................................................... 53
8.12
Bank 1 - Base Address Register.................................................................................................. 54
8.13
Bank 1 - Individual Address Registers......................................................................................... 54
8.14
Bank 1 - General Purpose Register............................................................................................. 55
8.15
Bank 1 - Control Register............................................................................................................. 55
8.16
Bank 2 - MMU Command Register.............................................................................................. 56
8.17
Bank 2 - Packet Number Register ............................................................................................... 58
8.18
Bank 2 - FIFO Ports Register....................................................................................................... 59
8.19
Bank 2 - Pointer Register............................................................................................................. 59
8.20
Bank 2 - Data Register................................................................................................................. 60
8.21
Bank 2 - Interrupt Status Registers.............................................................................................. 61
8.22
Bank 3 - Multicast Table Registers .............................................................................................. 65
8.23
Bank 3 - Management Interface................................................................................................... 66
8.24
Bank 3 - Revision Register .......................................................................................................... 66
8.25
Bank 3 - Early RCV Register ....................................................................................................... 67
8.26
Bank 7 - External Registers ......................................................................................................... 67
Chapter 9
PHY MII Registers........................................................................................................... 68
9.1
Register 0. Control Register............................................................................................................ 72
9.2
Register 1. Status Register ............................................................................................................. 73
9.3
Register 2&3. PHY Identifier Register............................................................................................. 74
9.4
Register 4. Auto-Negotiation Advertisement Register .................................................................... 74
9.5
Register 5. Auto-Negotiation Remote End Capability Register ...................................................... 76
9.6
Register 16. Configuration 1- Structure and Bit Definition .............................................................. 76
9.7
Register 17. Configuration 2 - Structure and Bit Definition ............................................................. 77
9.8
Register 18. Status Output - Structure and Bit Definition................................................................ 77
9.9
Register 19. Mask - Structure and Bit Definition ............................................................................ 78
9.10
Register 20. Reserved - Structure and Bit Definition.................................................................. 79
Chapter 10
Software Driver and Hardware Sequence Flow......................................................... 80
10.1
Software Driver and Hardware Sequence Flow for Power Management.................................... 80
10.2
Typical Flow of Events for Transmit (Auto Release = 0) ............................................................. 81
10.3
Typical Flow of Events for Transmit (Auto Release = 1) ............................................................. 83
10.4
Typical Flow of Event For Receive .............................................................................................. 84
Chapter 11
Board Setup Information ............................................................................................. 92
Chapter 12
Application Considerations.......................................................................................... 95
Chapter 13
Operational Description ............................................................................................. 102
13.1
Maximum Guaranteed Ratings*................................................................................................. 102
13.2
DC Electrical Characteristics ..................................................................................................... 102
13.3
Twisted Pair Characteristics, Transmit ...................................................................................... 105
13.4
Twisted Pair Characteristics, Receive ....................................................................................... 106
Chapter 14
Timing Diagrams ........................................................................................................ 108
LIST OF FIGURES
Figure 2.1 - Pin Configuration - LAN91C111-FEAST 128 PIN TQFP...........................................................................8
Figure 2.2 - Pin Configuration - LAN91C111-FEAST 128 PIN QFP.............................................................................9
Figure 3.1 - Basic Functional Block Diagram .............................................................................................................10
Figure 3.2 - Block Diagram.........................................................................................................................................11
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