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Электронный компонент: SSD1851TR1

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Table of Content
LCD SEGMENT / COMMON DRIVER WITH CONTROLLER ..................................................................................1
FEATURES ................................................................................................................................................................1
ORDERING INFORMATION......................................................................................................................................2
BLOCK DIAGRAM.....................................................................................................................................................3
TAB PAD ARRAGEMENT (SSD1851T PIN ASSIGNMENT) (COPPER VIEW).......................................................4
COF PAD ARRAGEMENT (SSD1851U PIN ASSIGNMENT)(COPPER VIEW) .......................................................5
DIE PAD ARRAGEMENT (SSD1850Z DIE PIN ASSIGNMENT)..............................................................................6
DIE PAD ARRANGEMENT (SSD1851Z DIE PIN ASSIGNMENT) ...........................................................................7
PIN DESCRIPTIONS................................................................................................................................................11
FUNCTIONAL BLOCK DESCRIPTIONS ................................................................................................................14
COMMAND DESCRIPTIONS ..................................................................................................................................28
MAXIMUM RATINGS ...............................................................................................................................................32
ELECTRICAL CHARACTERISTICS .......................................................................................................................32
AC ELECTRICAL CHARACTERISTICS .................................................................................................................34
APPLICATION CIRCUIT..........................................................................................................................................41
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA

This document contains information on a new product under definition stage. Solomon Systech Limited reserves
the right to change or discontinue this product without notice.

http://www.solomon-systech.com
SSD1850/ 51
Rev 1.4
P 1
Aug 2003
Copyright
2003 Solomon Systech Limited
Advance Information

CMOS
LCD Segment / Common Driver with Controller
SSD1850/51 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic
display system. SSD1850 consists of 194 high voltage driving output pins for driving 128 Segments and
64 Commons and 1 icon line. SSD1851 consists of 210 high voltage driving output pins for driving 128
Segments and 80 Commons and 1 icon line.
SSD1850/51 display data directly from their internal 128x65x2 / 128x81x2 bits Graphic Display
Data RAM (GDDRAM). Data/Commands are sent from general MCU through hardware selectable 6800-
/8080-series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface.
SSD1850/51 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider
and an On-Chip Oscillator which reduce the number of external components. With the special design on
minimizing power consumption and die/package layout, SSD1850/51 is suitable for any portable battery-
driven applications requiring long operation period and compact size.

FEATURES
128x64/80 + 1 icon line, 4 gray-levels Graphic Display
Programmable Multiplex ratio [16Mux - 65Mux/81Mux]
Single Supply Operation, 1.8 V - 3.3V
Low Current Sleep Mode(<1.0 uA)
On-Chip Voltage Generator / External Power Supply
Software selectable 2X / 3X / 4X / 5X / 6X On-Chip DC-DC Converter
On-Chip Oscillator
On-Chip Bias Dividers
Programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio
Maximum +15.0V LCD Driving Output Voltage
Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, 3-wire Serial
Peripheral Interface or 4-wire Serial Peripheral Interface
On-Chip 128x65x2 / 128x81x2 Graphic Display Data RAM
Re-mapping of Row and Column Drivers
Vertical Scrolling
Display Offset Control
64 Level Internal Contrast Control
External Contrast Control
Maximum 15MHz SPI or 10MHz PPI (8 bit) operation
Selectable LCD Driving Voltage Temperature Coefficients (2 settings)
Available in Gold Bump Die, Standard TAB (Tape Automated Bonding) Package and COF (Chip On Foil)
SSD1850/51

Solomon Systech
Aug 2003
P 2
Rev 1.4
SSD1850/ 51
ORDERING INFORMATION
Ordering Part
Number
SEG
COM
Default Bias
Package Form
Reference
SSD1850Z
128
64 + 1
1/9
Gold Bump Die
SSD1851Z
128
80 + 1
1/10
Gold Bump Die
SSD1851TR1
128
80 + 1
1/10
TAB
SSD1851U
128
80 + 1
1/10
COF



SSD1850/ 51
Rev 1.4
P 3
Aug 2003
Solomon Systech
BLOCK DIAGRAM

VL6
VL5
VL4
VL3
VL2
VSS
C1P
C2P
C3P
C4P
C5P
C1N
C2N
GDDRAM
128 x 65 x 2 Bits (SSD1850)
128 x 81 x 2 Bits (SSSD1851)
LCD Driving
Voltage Generator
2X/3X/4X/5X/ 6X
DC/DC Converter,
Voltage Regulator,
Bias Divider,
Contrast Control,
Temperature
Compensation
193 Bit Latch (SSD1850)
209 Bits Latch (SSD1851)
ICONS
ROW0 to ROW63 (SSD1850)
ROW0 to ROW79 (SSD1851)
SEG0 ~SEG127
HV Buffer Cell Level Shifter
Display
Timing
Generator
Oscillator
Level
Selector
Command Decoder
Parallel / Serial
Interface
Command Interface
CL
V
SS
V
DD
V
R
V
CC
REF
INTRS
V
CI
V
EXT
RES# PS0 PS1 CS# R/W E D/C
(WR#)(RD#)
D7 D6 D5 D4 D3 D2 D1 D0
(SDA)(SCK)

Solomon Systech
Aug 2003
P 4
Rev 1.4
SSD1850/ 51
TAB PAD ARRAGEMENT (SSD1851T PIN ASSIGNMENT) (Copper View)

249 NC
248 NC
247 COM39
246 COM38
245 COM37





209 COM1
208 COM0
207 ICONS
206 SEG0
205 SEG1




81 SEG125
80 SEG126
79 SEG127
78 COM40
77 COM41





42 COM76
41 COM77
40 COM78
39 COM79
38 ICONS
37 N/C


N/C
1
CL
2
VR
3
VL6
4
VL5
5
VL4
6
VL3
7
VL2
8
INTRS 9
C4P
10
C2N
11
C2P
12
C1P
13
C1N
14
C3P
15
C5P
16
VCC
17
VSS
18
VCI
19
VDD
20
D7
21
D6
22
D5
23
D4
24
D3
25
D2
26
D1
27
D0
28
E(RD#) 29
R/W(WR#)30
D/C
31
RES#
32
CS#
33
PS1
34
PS0
35
N/C
36
Remarks: REF is connected to VDD
VEXT is not connected