SN8P1700
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 1
Revision 1.94
SN8P1700 Series
USER'S MANUAL
General Release Specification
SN8P1702
SN8P1704
SN8P1706
SN8P1707
SN8P1708
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SN8P1700
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 2
Revision 1.94
AMENDMENT HISTORY
Version Date
Description
VER 1.90
Sep. 2002
V1.90 first issue
VER 1.93
Feb. 2003
1. Extend chip operating temperature from "0
C ~ +70
C" to
"-20
C ~ +70
C".
2. Change the description of ADD M,A instruction from "M M+A" to "M A+M"
3. Add ADC grade table.
4. Remove "Support hardware multiplier (MUL)" in SN8P1702 FEATURES section.
5. Change "Four internal interrupts" to "Three internal interrupts" in SN8P1704
FEATURES section.
6. Change "ACC can't be access by "B0MOV" instruction" to "ACC can't be access by
"B0MOV" instruction during the instant addressing mode".
7. Correct the description of STKnH.
8. Change "special register is located at 08h~FFh" to "special register is located at
80h~FFh".
9. Correct the bit definition of INTEN register.
10. Correct the description of "TC0 CLOCK FREQUENCY OUTPUT" section.
11. Correct the description of "TC1 CLOCK FREQUENCY OUTPUT" section.
12. SCKMD = 1 means SIO is in SLAVE mode. SCKMD = 0 means SIO is in MASTER
mode.
13. Remove "SIO clock and SPI clock are compatible".
14. Modify ADB's output data table.
15. Correct an error of template code: "b0bclr FWDRST" "b0bset FWDRST".
16. Add a notice about OSCM register access cycle.
17. SN8P1702/SN8A1702A don't provide "MUL, PUSH, POP" instruction.
18. Add a notice about OSCM register access cycle.
VER 1.94
Sep. 2003
1. Correct EOC description.
2. Correct watchdog timer overflow time.
3. Correct POP operand.
4. Correct ADCKS table.
5. Add new section about checksum calculate must avoid 04H~07H.
6. Reserved Last 16 word ROM addresses
7. Add SIOM table and SIO rate note
8. Remove register bit description
9. Modify TC0M description
10. Modify TC1M description
11. Modify PWM description
12. Modify ADC Frequency description
13. Change Code option table to Chapter 2
14. Add ADC current consumption
SN8P1700
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 3
Revision 1.94
15. Add LVD detect voltage
16. Remove approval sheet.
17. Remove PCB layout notice section.
18. Add MASK/OTP relative table.
19. Modify the description of INTRQ register.
20. Modify the calculation formula of SIOR and SIO clock.
SN8P1700
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 4
Revision 1.94
Table of Contents
AMENDMENT HISTORY .............................................................................................................. 2
1
1
1
PRODUCT OVERVIEW ................................................................................................... 11
GENERAL DESCRIPTION ......................................................................................................... 11
FEATURES SELECTION TABLE
....................................................................................... 11
MASK/OTP R
ELATIVE
T
ABLE
................................................................................................. 11
ADC GRADE TABLE
............................................................................................................. 11
SN8P1702 FEATURES............................................................................................................... 12
SN8P1704 FEATURES............................................................................................................... 13
SN8P1707/SN8P1708 FEATURES ............................................................................................ 15
SYSTEM BLOCK DIAGRAM ...................................................................................................... 16
PIN ASSIGNMENT ..................................................................................................................... 17
PIN DESCRIPTIONS .................................................................................................................. 22
PIN CIRCUIT DIAGRAMS .......................................................................................................... 22
2
2
2
CODE OPTION TABLE ................................................................................................... 23
3
3
3
ADDRESS SPACES ........................................................................................................ 24
PROGRAM MEMORY (ROM)..................................................................................................... 24
OVERVIEW ............................................................................................................................. 24
USER RESET VECTOR ADDRESS (0000H).......................................................................... 26
INTERRUPT VECTOR ADDRESS (0008H)............................................................................ 26
CHECKSUM CALCULATION.................................................................................................. 28
GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................. 29
LOOKUP TABLE DESCRIPTION............................................................................................ 29
JUMP TABLE DESCRIPTION................................................................................................. 31
DATA MEMORY (RAM) .............................................................................................................. 33
OVERVIEW ............................................................................................................................. 33
SN8P1700
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 5
Revision 1.94
RAM BANK SELECTION ........................................................................................................ 35
WORKING REGISTERS............................................................................................................. 36
H, L REGISTERS .................................................................................................................... 36
Y, Z REGISTERS .................................................................................................................... 37
X REGISTERS ........................................................................................................................ 38
R REGISTERS ........................................................................................................................ 38
PROGRAM FLAG ....................................................................................................................... 39
CARRY FLAG ......................................................................................................................... 39
DECIMAL CARRY FLAG......................................................................................................... 39
ZERO FLAG ............................................................................................................................ 39
ACCUMULATOR ........................................................................................................................ 40
STACK OPERATIONS................................................................................................................ 41
OVERVIEW ............................................................................................................................. 41
STACK REGISTERS............................................................................................................... 42
STACK OPERATION EXAMPLE............................................................................................. 43
PROGRAM COUNTER............................................................................................................... 44
ONE ADDRESS SKIPPING .................................................................................................... 45
MULTI-ADDRESS JUMPING .................................................................................................. 46
4
4
4
ADDRESSING MODE...................................................................................................... 47
OVERVIEW................................................................................................................................. 47
IMMEDIATE ADDRESSING MODE ........................................................................................ 47
DIRECTLY ADDRESSING MODE .......................................................................................... 47
INDIRECTLY ADDRESSING MODE....................................................................................... 47
TO ACCESS DATA in RAM BANK 0....................................................................................... 48
TO ACCESS DATA in RAM BANK 1....................................................................................... 48
5
5
5
SYSTEM REGISTER ....................................................................................................... 49
OVERVIEW................................................................................................................................. 49
SYSTEM REGISTER ARRANGEMENT (BANK 0) ..................................................................... 49
BYTES of SYSTEM REGISTER.............................................................................................. 49
BITS of SYSTEM REGISTER ................................................................................................. 51
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