ACX306AK
3.86cm (1.5 Type) NTSC/PAL Color LCD Panel
Description
The ACX306AK is a 3.86cm diagonal active matrix
TFT-LCD panel addressed by low temperature poly-
crystalline silicon transistors with built-in peripheral
driving circuitry. This panel provides full-color
representation for NTSC and PAL systems. In
addition, RGB dots are arranged in a delta pattern
that provides smooth picture quality without fixed
color patterns compared to vertical stripe and
mosaic patterns.
Features
Number of active dots: 118,000, 3.86cm (1.5 Type) in diagonal
Horizontal resolution:
240 TV lines
Optical transmittance: 6.5% (typ.)
High contrast ratio with normally white mode: 200 (typ.)
Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
Low voltage, low power consumption: 12V drive: 43mW (panel block, typ.)
Smooth pictures with a RGB delta arrangement
Supports NTSC/PAL
Built-in picture quality improvement circuit
Up/down and/or right/left inverse display function
LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
Dirt-resistant surface treatment
Narrow frame
Element Structure
Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
Number of pixels
Total number of dots:
494 (H)
242 (V) = 119,548
Number of active dots:
490 (H)
240 (V) = 117,600
Module dimensions
Package dimensions:
38 (W)
32.6 (D)
2.2 (H) (mm)
Effective display dimensions: 31.115 (H)
30.360 (V) (mm)
Applications
LCD monitors, etc.
1
E00143-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
2
ACX306AK
Block Diagram
The panel block diagram is shown below.
T
E
S
T
L
T
E
S
T
R
C
O
M
V
S
T
V
C
K
E
N
D
W
N
V
D
D
V
S
S
V
D
D
G
V
S
S
G
T
E
S
T
2
W
I
D
E
H
S
T
R
E
F
T
E
S
T
C
e
x
t
/
R
e
x
t
H
C
K
2
H
C
K
1
P
S
I
G
G
R
E
E
N
R
E
D
B
L
U
E
R
G
T
Level Shifter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
S
h
i
f
t
R
e
g
i
s
t
e
r
H Level Shifter & Shift Register
LC
C
S
COM
Common
Voltage
Boost,
Negative Voltage
Generation Circuit
3
ACX306AK
Absolute Maximum Ratings (Vss = 0V)
H driver supply voltage
V
DD
, Cext/Rext
1.0 to +17
V
V driver boost supply voltage
VDDG
V
DD
1.0 to +18
V
V driver negative supply voltage VSSG
3.0 to +1.0
V
Common voltage of panel
COM
1.0 to +17
V
H driver input pin voltage
HST, HCK1, HCK2, RGT, WIDE
1.0 to +17
V
V driver input pin voltage
VST, VCK, EN, DWN, REF
1.0 to +15
V
Video signal, uniformity improvement signal input pin voltage
GREEN, RED, BLUE, PSIG
1.0 to +13
V
Operating temperature
Topr
10 to +60
C
Storage temperature
Tstg
30 to +85
C
Operating Conditions of Panel Block
1. Input/output supply voltage conditions
1
(V
SS
= 0V)
Item
Supply voltage
V
DD
Cext/Rext
2
VDDG
VSSG
Rext
11.4
V
DD
3.4
14.0
2.3
--
12.0
12.0
15.0
1.8
10
12.6
--
16.3
1.5
160
V
V
V
V
k
VDDG output voltage setting
VSSG output voltage setting
3
Resistor connected to Cext/Rext pin
2
Symbol
Min.
Typ.
Max.
Unit
1
The V
DD
typical voltage setting is noted as 12.0V in these specifications.
2
Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
3
For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing
Zener diode as shown in the figure below.
V
DD
Cext/Rext
Cext/Rext
V
DD
V
DD
7
V
o
l
t
a
g
e
Time
t
ext
Set a Cext value that satisfies
t
ext > 1ms.
The Cext/Rext value differs
according to the rising time
of the panel supply voltage.
Rext
ACX306AK
V
DD
VSSG
V
SS
Cext/Rext
1
F
Cext
1
F
VDDG
Recommended
voltage applied
example Zener
diode.
(RD4.3UM is
recommended)
Recommended
voltage applied
example Zener
diode.
(RD2.7UM is
recommended)
4
ACX306AK
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
TESTL
COM
VST
VCK
EN
DWN
V
DD
V
SS
VDDG
VSSG
TEST2
WIDE
13
14
15
16
17
18
19
20
21
22
23
24
HST
REF
TEST
Cext/
Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
TESTR
Start pulse input for H shift register
drive
Level shifter circuit REF voltage
input
Panel test output; no connection
Time constant power supply input
for H shift register drive
Clock input for H shift register drive
Clock input for H shift register drive
Uniformity improvement signal input
Video signal (G) input to panel
Video signal (R) input to panel
Video signal (B) input to panel
H shift register drive direction signal
input
Panel test output; no connection
Symbol
Description
Pin
No.
Symbol
Description
Panel test output; no connection
Common voltage input of panel
Start pulse input for V shift register
drive
Clock input for V shift register drive
Gate selection pulse enable input
V shift register drive direction signal
input
Power supply input for V driver
H and V driver GND
Boost power supply setting for
V driver
Negative power supply setting for
V driver
No connection inside the panel.
(with 1M
terminating resistor)
Uniformity improvement signal
control pulse input
Pin Description of Panel Block
4
Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC
as shown in Fig. 1.
PSIG waveform
VVC
Vpsig
Fig. 1
Item
H/V driver input voltage
(Low)
(High)
VIL
VIH
VREF
VVC
Vsig
Vpsig
Vcom
0.3
2.6
VIH/2 0.3
5.8
1.0
VVC 2.3
VVC 0.6
0.0
3.0
VIH/2
6.0
VVC 4.0
VVC 2.5
VVC 0.5
0.3
5.5
VIH/2 + 0.3
6.2
VDDG 4.0
(10.5V or less)
VVC 2.7
VVC 0.4
V
V
V
V
V
V
V
REF input voltage
Video signal center voltage
4
Video signal input range
4
Uniformity improvement signal
4
Common voltage of panel (Ta = 25C)
Symbol
Min.
Typ.
Max.
Unit
2. Panel input signal voltage conditions
(V
SS
= 0V)
5
ACX306AK
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to V
SS
with a
high resistance of 1M
(typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
V
DD
1M
Input
Signal line
(2) HCK1, HCK2
1M
1M
V
DD
V
DD
HCK1
HCK2
H level shifter and
shift register circuit
(3) WIDE, REF
1M
350
1M
350
V
DD
V
DD
Input
REF
Level conversion
circuit
(5) RGT, REF
1M
2k
1M
2k
V
DD
V
DD
Input
REF
Level conversion
circuit
(4) HST
1M
175
1M
175
V
DD
V
DD
Input
REF
Level conversion
circuit
PDF 
ZIP