1
E00X53A14
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ACX306BKM
Description
The ACX306BKM is an LCD panel module with LED
backlight developed exclusively for the ACX306BKM
3.86cm diagonal active matrix TFT-LCD panel
addressed by low temperature polycrystalline silicon
transistors with built-in peripheral driving circuitry.
This module provides full-color representation for
NTSC and PAL systems. In addition, RGB dots are
arranged in a delta pattern that provides smooth
picture quality without fixed color patterns compared
to vertical stripe and mosaic patterns.
Features
Total module thickness: 3.9mm (typ.) ultra-thin, narrow frame type
Center luminance
Standard mode:
260cd/m
2
(backlight 210mW typ.)
High luminance mode: 330cd/m
2
(backlight 290mW typ.)
White LED backlight eliminates the need for an inverter, achieves instant luminance rise, and maintains high
luminance even at cold temperatures
Backlight life (luminance half-life) guaranteed at 5000h for normal temperature operation and 1000h for high
temperature operation
Number of active dots: 118,000, 3.86cm (1.5-type) in diagonal
Horizontal resolution:
240 TV lines
Optical transmittance:
9.0% (typ.)
High contrast ratio with normally white mode: 200 (typ.)
Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
Low voltage, low power consumption: 12V drive, 43mW (panel block, typ.)
Smooth pictures with a RGB delta arrangement
Supports NTSC/PAL
Built-in picture quality improvement circuit
Up/down and/or right/left inverse display function
LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
Dirt-resistant surface treatment
Narrow frame
Element Structure
Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
Edge-light type backlight using high luminance white LEDs
Number of pixels
Total number of dots:
494 (H)
242 (V) = 119,548
Number of active dots:
490 (H)
240 (V) = 117,600
Module dimensions
Package dimensions:
37.1 (W)
32.7 (D)
3.9 (H) (mm)
Effective display dimensions: 31.115 (H)
22.86 (V) (mm)
Applications
Compact digital still cameras, compact video cameras, etc.
3.86cm (1.5-type) NTSC/PAL Color LCD Panel Module with LED Backlight
2
ACX306BKM
Module Configuration
Panel Block Diagram
The panel block diagram is shown below.
TESTL
TESTR
COM
VST
VCK
EN
DWN
V
DD
V
SS
VDDG
VSSG
TEST2
WIDE
HST
REF
TEST
Cext/Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
Level Shifter
Boost, Negative
Voltage Generation
Circuit
Common
Voltage
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V Shift Register
H Level Shifter & Shift Register
LC
C
S
COM
3
ACX306BKM
Absolute Maximum Ratings (V
SS
= 0V)
H driver supply voltage
V
DD
, Cext/Rext
1.0 to +17
V
V driver boost supply voltage
VDDG
V
DD
1.0 to +18
V
V driver negative supply voltage
VSSG
3.0 to +1.0
V
Common voltage of panel
COM
1.0 to +17
V
H driver input pin voltage
HST, HCK1, HCK2, RGT, WIDE
1.0 to +17
V
V driver input pin voltage
VST, VCK, EN, DWN, REF
1.0 to +15
V
Video signal, uniformity improvement
GREEN, RED, BLUE, PSIG
1.0 to +13
V
signal input pin voltage
Operating temperature
Topr
10 to +60
C
Storage temperature
Tstg
30 to +80
C
LED backlight DC forward voltage
Vfbl
18
V
LED backlight DC forward current
Ifbl
25
mA
LED backlight reverse withstand voltage
Vrbl
0
V
Operating Conditions of Panel Block
1. Input/output supply voltage conditions
1
(V
SS
= 0V)
1
The V
DD
typical voltage setting is noted as 12.0V in the above table.
2
Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
The Cext/Rext value differs according to the rising time of the panel supply voltage.
3
For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing
Zener diode as shown in the figure below.
V
DD
Cext/Rext
Cext/Rext
V
DD
V
DD
7
Voltage
Time
t
ext
Set a Cext value that satisfies
t
ext > 1ms.
Rext
ACX306BKM
V
DD
VSSG
V
SS
Cext/Rext
1F
Cext
1F
VDDG
Recommended voltage applied
example Zener diode
(RD4.3UM is recommended.)
Recommended voltage applied
example Zener diode
(RD2.7UM is recommended.)
Cext/Rext constant setting conditions
Recommended voltage applied example
IDD measurement circuit diagram
Item
Supply voltage
VDDG output voltage setting
VSSG output voltage setting
3
Resistor connected to Cext/Rext pin
2
V
DD
Cext/Rext
2
VDDG
VSSG
Rext
Symbol
11.4
V
DD
3.4
14.0
2.3
--
Min.
12.0
12.0
15.0
1.8
10
Typ.
12.6
--
16.3
1.5
160
Max
V
V
V
V
k
Unit
4
ACX306BKM
2. Panel input signal voltage conditions
(V
SS
= 0V)
4
Input video and uniformity improvement signals should be input with the voltage amplitude symmetrical to
VVC as shown in Fig. 1.
Fig. 1
PSIG waveform
VVC
Vpsig
Operating Conditions of Backlight Block
1. Input supply voltage conditions
Standard mode: luminance 260cd/m
2
operation
High luminance mode: luminance 330cd/m
2
operation
Backlight equivalent circuit
BL1
(GND)
BL2
(DC constant current input)
Item
Backlight DC forward current
Backlight DC forward voltage
Backlight power consumption
IfBL
Vfbl
20
Pbl
20
Symbol
--
12.8
256
Min.
20
14.4
288
Typ.
--
16.0
320
Max.
mA
V
mW
Unit
Item
Backlight DC forward current
Backlight DC forward voltage
Backlight power consumption
IfBL
Vfbl
15
Pbl
15
Symbol
--
12.3
185
Min.
15
13.9
209
Typ.
--
15.5
233
Max.
mA
V
mW
Unit
Item
H/V driver input voltage
REF input voltage
Video signal center voltage
4
Video signal input range
4
Uniformity improvement signal
4
Common voltage of panel (Ta = 25C)
VIL
VIH
VREF
VVC
Vsig
Vpsig
VCOM
Symbol
0.3
2.6
VIH/2 0.3
5.8
1.0
VVC 2.3
VVC 0.6
Min
0.0
3.0
VIH/2
6.0
VVC 4.0
VVC 2.5
VVC 0.5
Typ.
0.3
5.5
VIH/2 + 0.3
6.2
VDDG 2.0
VVC 2.7
VVC 0.4
Max.
V
V
V
V
V
V
V
Unit
(Low)
(High)
5
ACX306BKM
Pin Description of Panel Block
Pin Description of Backlight Block
Pin
No.
1
2
Symbol
BL1
BL2
Description
Power supply GND for backlight
lighting
Power supply input for backlight
lighting
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
TESTL
COM
VST
VCK
EN
DWN
V
DD
V
SS
VDDG
VSSG
TEST2
WIDE
Description
Panel test output; no connection
Common voltage input of panel
Start pulse input for V shift register
drive
Clock input for V shift register drive
Gate selection pulse enable input
V shift register drive direction signal
input
Power supply input for H and V
driver
H and V driver GND
Boost power supply setting for V
driver
Negative power supply setting for
V driver
No connection inside the panel.
(with 1M
terminating resistor)
Uniformity improvement signal
control pulse input
Pin
No.
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
HST
REF
TEST
Cext/
Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
TESTR
Description
Start pulse input for H shift register
drive
Level shifter circuit REF voltage
input
Panel test output; no connection
Time constant power supply input
for H shift register drive
Clock input for H shift register drive
Clock input for H shift register drive
Uniformity improvement signal input
Video signal (G) input to panel
Video signal (R) input to panel
Video signal (B) input to panel
H shift register drive direction
signal input
Panel test output; no connection
6
ACX306BKM
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to V
SS
with
a high resistance of 1M
(typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(2) HCK1, HCK2
1M
1M
V
DD
V
DD
HCK1
HCK2
H level shifter
and shift register
circuit
(3) WIDE, REF
1M
350
1M
350
V
DD
V
DD
Input
REF
Level conversion
circuit
(4) HST
1M
175
1M
175
V
DD
V
DD
Input
REF
Level conversion
circuit
(5) RGT, REF
1M
2k
1M
2k
V
DD
V
DD
REF
Input
Level conversion
circuit
(1) RED, GREEN, BLUE, PSIG
V
DD
1M
Input
Signal line
7
ACX306BKM
(6) VST, VCK, EN, REF
1M
800
1M
800
V
DD
V
DD
REF
Input
Level conversion
circuit
(7) DWN, REF
1M
1M
V
DD
V
DD
REF
2k
2k
Input
Level conversion
circuit
(8) VDDG, VSSG
V
DD
VDDG, VSSG
Boost, Negative
voltage generation
circuit
(9) COM
1M
Input
LC
(10) Cext/Rext
V
DD
Cext/Rext
H driver
2.7M
1M
(11) TEST/TEST2
V
DD
TEST
350
1M
350
TEST2
1M
(12) TESTL, TESTR
TESTL
TESTR
4M
V
DD
8
ACX306BKM
Clock Timing Conditions of Panel Block
(VIH = 3.0V, V
DD
= 12V, Ta = 25C)
5
HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)
Item
HST
HCK
VST
VCK
EN
WIDE
HST rise time
HST fall time
HST data setup time
HST data hold time
HCKn
5
rise time
HCKn
5
fall time
HCK1 fall to HCK2 rise time
HCK1 rise to HCK2 fall time
VST rise time
VST fall time
VST data setup time
VST data hold time
VCK rise time
VCK fall time
EN rise time
EN fall time
EN fall to VCK rise/fall time
EN pulse width
WIDE rise time
WIDE fall time
WIDE (H) rise to VCK rise/fall time
WIDE (H) pulse width
Symbol
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVckn
tfVckn
trEn
tfEn
tdEn
twEn
trWide
tfWide
tdhWide
twhWide
Min.
--
--
300
30
--
--
15
15
--
--
30
30
--
--
--
--
500
2900
--
--
0.4
1.4
Typ.
--
--
333
0
--
--
0
0
--
--
32
32
--
--
--
--
600
3000
--
--
0.5
1.5
Max.
30
30
363
30
30
30
15
15
100
100
34
34
100
100
100
100
700
3100
100
100
0.6
1.6
Unit
ns
s
ns
s
9
ACX306BKM
Horizontal Standard Timing
FRP
VCK
EN
WIDE
HCK2
HCK1
HST
3.0s
0.6s
3.0s
1.5s
1.1s
0.4s
10
ACX306BKM
<Horizontal Shift Register Driving Waveforms>
Item
Symbol
Waveform
Conditions
HST
HCK
HST rise time
HST fall time
HST data setup time
HST data hold time
HCKn
5
rise time
HCKn
5
fall time
HCK1 fall to HCK2 rise
time
HCK1 rise to HCK2 fall
time
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
HCKn
5
duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
HCKn
5
duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
HCKn
5
duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 333ns
thHst = 0ns
tdHst = 333ns
thHst = 0ns
WIDE
WIDE rise time
WIDE fall time
WIDE rise to VCK rise/fall
time
WIDE pulse width
trWide
tfWide
tdhWide
twhWide
HCKn
90%
90%
10%
10%
trHckn
tfHckn
5
50%
50%
50%
50%
HCK1
HCK2
to2Hck
to1Hck
6
90%
90%
10%
10%
HST
trHst
tfHst
50%
50%
50%
tdHst
thHst
HST
HCK1
50%
6
WIDE
90%
90%
10%
10%
trWide
tfWide
VCK
50%
WIDE
50%
50%
tdhWide
twhWide
6
7
6
Definitions:
The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means .
The black dot at an arrow ( ) indicates the start of measurement.
7
WIDE represents every 1H pulse as shown in Horizontal Timing.
11
ACX306BKM
Vertical Standard Timing
FRP
EN
WIDE
HST
VCK
VST
NTSC 4:3 (in case of EVEN field)
12
ACX306BKM
<Vertical Shift Register Driving Waveforms>
Item
Symbol
Waveform
Conditions
VST
VCK
VST rise time
VST fall time
VST data setup time
VST data hold time
VCK rise time
VCK fall time
trVst
tfVst
tdVst
thVst
trVck
tfVck
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32s
thVst = 32s
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
EN
EN rise time
EN fall time
EN fall to VCK rise/fall
time
EN pulse width
trEn
tfEn
tdEn
twEn
90%
90%
VST
trVst
tfVst
10%
10%
VCK
90%
90%
10%
10%
trVck
tfVck
90%
tfEn
10%
EN
90%
10%
trEn
6
VCK
50%
EN
50%
50%
tdEn
twEn
50%
50%
VST
50%
VCK
tdVst
thVst
50%
6
13
ACX306BKM
Electrical Characteristics of Panel Block
1. Horizontal drivers
(Ta = 25C, V
DD
= 12.0V, VIH = 3.0V, VREF = 1.5V)
HCKn: HCK1, HCK2 (1.5MHz)
2. Vertical drivers
3. Total power consumption of the panel
4. Pin input resistance
Item
HCKn input pin capacitance
HST input pin capacitance
Video signal input pin capacitance
Psig input pin capacitance (4:3 display)
Input pin current
HCK1
HCK2
HST
RGT
REF
Symbol
CHckn
CHst
Csig
Cpsig
I Hck1
I Hck2
I Hst
I RGT
I REF
Min.
Typ.
Max.
Unit
Conditions
--
--
--
--
600
600
200
150
900
55
30
120
5.2
300
300
100
50
300
65
50
150
8.0
--
--
--
--
--
pF
pF
pF
nF
A
A
A
A
A
HCK1: actual driving
HCK2: actual driving
HST = GND
RGT = GND
REF = VIH/2
Item
VCK input pin capacitance
VST input pin capacitance
Input pin current
VCK
VST
EN
DWN
WIDE
Symbol
CVck
CVst
I Vck
I Vst
I En
I DWN
I WIDE
Min.
Typ.
Max.
Unit
Conditions
--
--
150
150
150
150
150
10
10
50
50
50
50
50
15
15
--
--
--
--
--
pF
pF
A
A
A
A
A
VCK = GND
VST = GND
EN = GND
DWN = GND
WIDE = GND
Item
Total power consumption
of the panel (NTSC)
Symbol
PWR25
PWR60
Min.
Typ.
Max.
Unit
--
--
43
--
55
75
mW
mW
(Ta = 25C)
(Ta = 60C)
Item
Pin V
SS
input resistance 1
Symbol
Rin1
Min.
Typ.
Max.
Unit
0.5
1
--
M
14
ACX306BKM
Electro-optical Characteristics of Module/Panel Block
(Ta = 25C, NTSC mode)
1
Conforms to the measurement results for the discrete panel.
Item
Contrast ratio
Panel block optical transmittance
1
Center luminance
Chromaticity
(Iled = 15mA)
V-T characteristics
1
Half tone color reproduction
range
1
Response time
1
Flicker
1
Image retention time
1
Viewing angle range
Surface reflection ratio
Cross talk
1
X
Y
Tc
uv
X
Y
X
Y
X
Y
25C
60C
25C
60C
25C
60C
R G
B G
0C
25C
0C
25C
60C
60C
CR
10
= 0
25C
CR
25
T
Lm
15
Lm
20
Wx
Wy
Tcm
duvm
Rx
Ry
Gx
Gy
Bx
By
V
90-25
V
90-60
V
50-25
V
50-60
V
10-25
V
10-60
V
50RG
V
50BG
ton0
ton25
toff0
toff25
F
YT1
T
B
L
R
Rf
CTK
1
2
2
2
3
3
4
5
6
7
8
9
10
11
100
7.8
180
240
--
--
5900
0.016
0.590
0.320
0.260
0.460
0.120
0.080
1.30
1.30
1.70
1.70
2.30
2.30
0.115
0
--
--
--
--
--
--
15
50
35
35
--
--
200
9.0
260
330
0.295
0.310
7800
0.003
0.620
0.350
0.290
0.500
0.150
0.130
1.50
1.50
1.90
1.90
2.50
2.50
0.080
0.03
70
17
120
30
60
--
20
60
40
40
0.9
0.9
--
--
--
--
0.325
0.360
--
0.022
0.650
0.380
0.320
0.540
0.180
0.180
1.70
1.70
2.10
2.10
2.70
2.70
0.045
0.05
90
25
180
75
30
10
--
1.5
1.5
--
%
cd/m
2
CIE
standard
K
CIE
standard
V
V
ms
dB
s
Degree
()
%
%
Symbol
Measurement
method
Min.
Typ.
Max.
Unit
Iled = 15mA
Iled = 20mA
W
R
G
B
V
90
V
50
V
10
ON time
OFF time
15
ACX306BKM
Electro-optical Characteristics of Backlight Block
(Ta = 25C, discrete backlight)
Item
Backlight DC forward
voltage
Backlight power
consumption
Backlight center
luminance
Backlight center
chromaticity
Backlight luminance
uniformity
Backlight life
(Luminance half-life)
Vfbl
15
Vfbl
20
Pbl
15
Pbl
20
Lbl
15
Lbl
20
xbl
ybl
Tcbl
duvbl
BLunif
BLl
1555
BLl
1570
BLl
2040
BLl
2065
12
12
12
12
12
12
12
12
12
12
13
14
14
14
14
12.3
12.8
185
256
2200
2700
0.280
0.255
6100
+0.011
60
5000
1000
5000
1000
13.9
14.4
209
288
3000
3700
0.305
0.308
8000
0.003
--
--
--
--
--
15.5
16.0
233
320
--
--
0.330
0.360
19000
0.015
--
--
--
--
--
V
W
cd/m
2
K
%
hr
Symbol
Measurement
method
Min.
Typ.
Max.
Unit
Conditions
Ifbl = 15mA
Ifbl = 20mA
Ifbl = 15mA
Ifbl = 20mA
Ifbl = 15mA
Ifbl = 20mA
Ifbl = 15mA
Ifbl = 15mA
Ifbl = 15mA
Ifbl = 20mA
Ta = less than
55C
Ta = 55 to 70C
Ta = less than
40C
Ta = 40 to 60C
16
ACX306BKM
Luminance
Meter
Measurement
Equipment
Light Detector
Measure using the discrete LCD panel.
Drive Circuit
Light Source
Optical fiber
Light
Source
Spectroscope
Surface A
Surface A
Surface A
LCD panel
15mA
Optical fiber
Light receptor lens
Constant
current circuit
TOPCON BM-5A luminance meter
LED backlight
A
V
1. Contrast Ratio
Contrast ratio (CR) is given by the following formula.
CR = L (White)/L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude V
AC
= 0.5V.
L (Black): Surface luminance of the panel at V
AC
= 4.0V.
Both luminosities are measured by System
I
.
Surface A: See the Package Outline.
<Panel/Module/Backlight Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
V
DD
= 12.0V, VIH = 3.0V, VREF = 1.5V
VVC = 6.0V, VCOM = 5.5V, Vpsig = 6.0 2.5V
(2) Measurement temperature
25C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Three types of measurement systems are used as shown below.
(5) R, G and B input signal voltage Vsig
Vsig = 6.0 V
AC
[V] (V
AC
: signal amplitude)
Measurement system
I
Measurement system
II
Measurement system
III
17
ACX306BKM
2. Optical Transmittance of Panel, Center Luminance of Module, Color Temperature
Optical transmittance (T) is given by the following formula.
T = L (White)/Luminance of Backlight
100 [%]
L (White) is the same expression as defined in "Contrast Ratio".
Lm = White luminance at the center of the panel
Tcm = Color temperature at the center of the panel
Measured by System
I
using the TOPCON BM-5A.
3. Chromaticity
Chromaticity of the panels is measured by System
I
. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System
I
uses x and y of
the CIE standards as the chromaticity here.
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System
II
by inputting the same signal
amplitude V
AC
to each input pin. V
90
, V
50
, and V
10
correspond to the voltages which define 90%, 50%, and
10% of transmittance respectively.
5. Half Tone Color Reproduction Range
The half tone color reproduction range of LCD panels
is characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System
II
.
System
II
defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V
50R
, V
50G
and V
50B
, respectively. V
50RG
and V
50BG
, that
is to say the differences between V
50R
and V
50G
and
between V
50B
and V
50G
, are given by the following
formulas respectively.
V
50RG
= V
50R
V
50G
V
50BG
= V
50B
V
50G
90
50
10
V
10
V
50
V
90
V
AC
Signal amplitude [V]
Transmittance [%]
Transmittance [%]
0
V
50R
V
AC
Signal amplitude [V]
50
100
V
50B
V
50G
V
50RG
V
50BG
G raster
B raster
R raster
Signal amplitudes (V
AC
) supplied to each input
R input
0.5
4.0
4.0
0.0
G input
4.0
0.5
4.0
0.0
B input
4.0
4.0
0.5
0.0
R
G
B
W
Raster
(Unit: V)
18
ACX306BKM
6. Response Time
Response times ton and toff are measured
by System
II
by applying the input signal
voltages in the figure to the right to each
input pin. These times are defined by the
following formulas.
ton = t1 tON
toff = t2 tOFF
t1: time which gives 10% transmittance
of the panel.
t2: time which gives 90% transmittance
of the panel.
The relationships between t1, t2, tON and
tOFF are shown in the figure to the right.
7. Flicker
Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms) of
the panel output signal for gray raster
mode are measured by a DC voltmeter and a spectrum analyzer in
System
II
.
F [dB] = 20 log {AC component/DC component}
R, G, B input signal voltage for gray raster mode is given by Vsig = 5.5 V
50
[V]
where: V
50
is the signal amplitude which gives 50% of transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply the monoscope pattern
to the LCD panel for 1 minute and then change to a gray scale signal
(Vsig = 6.0 V
AC
[V]; V
AC
= 3 to 4V). Judging by sight at the V
AC
that holds the maximum image retention,
measure the time for the residual image to disappear.
Monoscope pattern input conditions
Vsig = 6.0 4.0 or 6.0 2.0 [V]
(shown in the figure to the right)
VCOM = 5.5V
4.0V
5.5V
0V
0.5V
Optical transmittance output
waveform
100%
90%
10%
0%
tON
t1
tOFF
t2
ton
toff
Input signal voltage (Waveform applied to measured pixels)
6.0V
0V
4.0V
2.0V
4.0V
2.0V
Black level
White level
Vsig waveform
19
ACX306BKM
9. Definition of Viewing Angle Range
Viewing angle range is measured by System
I
. The
contrast ratio (CR) is measured at the angles
defined in the figure to the right and the range
where CR
10 is taken as the viewing angle range.
Measure with surface A
facing upwards.
Surface A: See the Package Outline.
10. Surface Reflection Ratio
Surface reflection ratio (Rf) is given by the following formula.
Rf = Reflected optical luminance of the panel surface A
/Reflected optical luminance of Al (wafer)
100 [%]
The incident and reflected angles of light are both 0.
Both luminosities are measured by System
III
.
Surface A: See the Package Outline.
11. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi
(i = 1 to 4) around the black window (Vsig = 4.0V/1V).
Cross talk value CTK =
100 [%]
T
R
B
L
Normal (
= 0)
Right
Left
Bottom
Top
Surface A
W1
W1'
W4
W4'
W3
W3'
W2
W2'
Wi' Wi
Wi
20
ACX306BKM
12. Backlight Center Luminance and Chromaticity Measurement Method
1. Environmental conditions
Temperature: 25 5C
Humidity: 30 to 85%
Start measurement after leaving the module in the above environment for one hour.
Measurement should be performed in a dark room with a luminance of 10 lx or less and which is not
subject to the effects of reflective or external light.
There should be no heat insulating objects around the module unit, and measurement should be
performed in a draftless condition.
2. Luminance and chromaticity measurement method
Measurement equipment: TOPCON BM-5A, viewing angle: 0.2, distance: 450 50mm
Measure 30s after the backlight is lit.
Using a constant current circuit, measure the luminance under both conditions of Ifbl = 15mA and
20mA, and measure the chromaticity under only the condition of Ifbl = 15mA.
13. Backlight Luminance Uniformity Measurement Method
1. Environmental conditions
Measure under the same conditions as "12. Backlight Center Luminance and Chromaticity Measurement
Method" above.
2. Light the backlight at Ifbl = 15mA using a constant current circuit, and start measurement 30s after the
backlight is lit.
Backlight luminance uniformity is obtained by dividing the effective pixel area into 9 equal sections as
shown below, measuring the luminance at each of the centers 1 to 9, and calculating Min. luminance
Max. luminance
100 [%].
14. Backlight Life Measurement Method
Definition of life:
When the backlight center luminance drops to 50% of the initial value.
Lighting conditions: Discrete backlight under the following conditions.
Leave the module in a normal temperature (25C) environment for one hour before
performing optical measurement.
(1) Ifbl = 15mA
1-1) Continuous lighting at an ambient temperature of 55C. (5000h or more)
1-2) Continuous lighting at an ambient temperature of 70C. (1000h or more)
(2) Ifbl = 20mA
2-1) Continuous lighting at an ambient temperature of 40C. (5000h or more)
2-2) Continuous lighting at an ambient temperature of 65C. (1000h or more)
1
1/3
1/3
Effective pixel area of the panel
1/3
1/3
1/3
Effective pixel area of the panel
1/3
2
3
4
5
6
7
8
9
21
ACX306BKM
Description of Panel Block Operation
1. Color Coding
The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the
display.
2
490
494
2
1
240
242
1
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
B
G
B
R
G
B
R
B
R
G
B
R
G
B
R
G
R
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
B
G
B
R
G
B
R
B
R
G
B
R
G
B
R
G
R
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
B
G
B
R
G
B
R
B
R
G
B
R
G
B
R
G
R
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
B
G
B
R
G
B
R
B
R
G
B
R
G
B
R
G
R
R
Active area
22
ACX306BKM
2. Description of LCD Panel Operations
A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to each of 240 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display is
possible by using the enable pin and simultaneously controlling VCK.
A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry,
applies selected pulses to each of 490 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning
direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT
pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the
DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top
for DWN pin at low level (0V). (These scanning directions are from a front view.)
The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one
pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 240
490 pixels to
display a picture in a single vertical scanning period.
Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots
against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each
horizontal line against the horizontal sync signal to apply a video signal to each pixel properly.
The video signal should be input with the polarity-inverted every horizontal cycle.
The relationships between the vertical shift register start pulse VST and the vertical display period, and
between the horizontal shift register start pulse HST and the horizontal display period are shown below for
top to bottom and left to right scan.
(1) Vertical display period (DWN: high level)
VD
VST
VCK
1
2
Vertical display period 240H (14.5ms)
239
240
(3) Horizontal display period (RGT: high level)
BLK
HST
HCK1
HCK2
1
2
3
164
165
166
Horizontal display period (54.6s)
(2) Vertical display period (DWN: low level)
VD
VST
VCK
1
2
Vertical display period 240H (14.5ms)
239
240
23
ACX306BKM
3. RGB Simultaneous Sampling
The horizontal driver samples R, G and B video signals simultaneously, which requires phase matching
between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching
by an external signal delay circuit is needed before applying the video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block
diagrams are as follows.
The ACX306BKM has a right/left inversion function. The following phase relationship diagram indicates the
phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be
inverted for the B and G signals.
(1) Sample-and-hold (right scan)
<Phase relationship of delaying sample-and-hold pulses> (right scan)
(2) Delay element (right scan)
AC Amp
AC Amp
AC Amp
S/H
S/H
S/H
S/H
CKB
CKG
CKG
CKG
CKR
B
R
G
BLUE
RED
GREEN
ACX306BKM
S/H
20
21
22
HCKn
CKB
CKR
CKG
AC Amp
AC Amp
AC Amp
Delay
Delay
B
R
G
BLUE
RED
GREEN
ACX306BKM
Delay
20
21
22
24
ACX306BKM
System Configuration
+12.0V
+3.0V
+12.0V
PSIG
GREEN
BLUE
COM
HCK2
VCK
RED
HCK1
HST
VST
EN
RGT
REF
WIDE
Y/color difference
R/G/B
Serial data
DWN
1F
Rext
See page 3 for
the value setting.
Cext
CXA3572R
LCD panel
ACX306BK
Cext/Rext
VSSG
1F
Zener diode
RD4.3UM
VDDG
Zener diode
RD2.7UM
Dedicated LED
backlight
LCD module with backlight
Constant current circuit
V
DD
25
ACX306BKM
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels and LED backlights are easily damaged
by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install grounded conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the panel.
c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stains on the surface.
d) Use ionized air to blow dust off the panel.
(3) Module fixing method
a) The following items should be taken into account for the positioning guide design.
The design reference edges are the upper and left edges of the panel as viewed from the front.
Design the guides using the panel frame as the reference and not the backlight.
Set the guides on the same side of the set as the monitor window frame.
To prevent LCD image unevenness, the guides should be the maximum package tolerance or more
so that a clasping load is not applied to the panel from the x and y directions.
Make sure the guides do not block the panel FPC outlet and backlight lead wire outlet.
b) The guaranteed area of the polarizer is the outer circumference of 0.7mm of the effective display area
(Fig. 1). Design the monitor window frame of the set so that it is within this range including variance.
c) Set the holders on the rear of the backlight around the circumference as far from the center of the
backlight as possible. Local pressure applied to the center of the rear of the backlight for an extended
period may result in uneven luminance, so the holder pressure on the center of the backlight should be
500g/cm
2
or less.
d) Connect the panel or backlight frame to GND.
e) Use a design that does not repeatedly bend or place stress on the backlight lead wires (maximum load
in the lead wire pull-out direction: 500g) as this may cause lead wire disconnection at the solder
junction on the backlight unit side. (Forced bending of 90 or more is permitted up to 2 times, and
repeated bending of 45 up to 8 times.)
26
ACX306BKM
(4) Others
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel or backlight.
c) Do not twist or bend the panel, panel frame or backlight.
d) Keep the panel and backlight away from heat sources.
e) Do not dampen the panel or backlight with water or other solvents.
f) Avoid storage or use of the panel at high temperatures or high humidity, as this may result in damage.
0.7mm
0.7mm
Effective display area
Guaranteed area
Polarizer package
Fig. 1
27
A
CX306BKM
Son
y Cor
por
ation
Package Outline Unit: mm
No.
Name
Model No.
1
LCD panel
2
Backlight
3
Label (10.5
4mm)
4
Connector
5
Harness (Sumitomo Electric Industries)
PI28A02F 1: GND, 2: Input
AWM3633 AWG28
77 3 (+ side)
108 3
(GND side)
(32.72)
0.5
15.1
(17.2)
3.1
4
0.42
32.3
1
2
1.84
2.1
3.3 0.2
+0.2
0.1
37.1 0.3
0.5
38.1 0.3
1.7
1
Corner portion (4 places)
1.5
1.5
R1
0
-0.1
D
3
1
2
0.3 0.05
3.94
Note 1. Tolerance with no indication (0.2mm)
2. Design the guaranteed area of the polarizer
within the outer circumference of 0.7mm of
the active area.
3. Mass: approximately 10.3g
0.5
6
Reflective film
6
Electrode
(Sumiko Tec)
ACX306BK
D portion
4 0.5
3 0.15
0.35
(0.5)
0.5 0.1
P: 0.5 0.02
23
=11.5 0.03
2-R0.3
enlarged
Pin 1
Pin 24
31.115 (Active area)
34.3 (Window)
1.13
(1.13)
22.86
(Activ
e area)
26.35 (Windo
w)
(3.42)
2.17
15.52
(16.42)
C
33.3 0.4 (Polarizer)
36.56 0.1
(Corner portion)
37.1 0.3
(Bending portion)
25 0.4
(P
olar
iz
er)
31.94 0.1
(Cor
ner por
tion)
4
5
18.55
24.29 0.5
37.98 0.5
45.38 0.5
57.48 0.5
49.98 0.5
6.6 0.5
3 0.5
9.5 0.5
10.88 0.5
11.01 0.5
12.5 0.5
0.85 0.05
(Pink)
(White)
(Surface A)
Electrode
Front View
(Surface B)
Rear View
C portion enlarged
-
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