CXA1203M/N

8mm VCR PAL JOG

Description

The CXA1203M/N compensates the color alignment

in variable speed mode for PAL-system 8mm VCRs.

This IC is also available for the SECAM system with

the built-in SECAM detector and BELL and C-BELL

filters.

Features

· Color alignment compensation which does not

require 1H delay line

· No AFC (f

) adjustment necessary

· Built-in SECAM detector

· Built-in BELL and C-BELL filters

· Available for the PAL-M system

Functions

V-Invert circuit, TH/DL APC, 2fsc PLL, SQ DET,

EX burst circuit, AFC (f

), Timing generator,

SECAM detector, BELL filter, C-BELL filter

Structure

Silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

7.0

· Operating temperature Topr

20 to +75

°C

· Storage temperature

Tstg

55 to +150

°C

· Allowable power dissipation

CXA1203M

567

CXA1203N

536

Recommended Operating Conditions

Supply voltage

4.5 to 5.5

(5.0V typ.)

E01Z33-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA1203M

24 pin SOP (Plastic)

CXA1203N

24 pin SSOP (Plastic)

CXA1203M/N

Block Diagram and Pin Configuration

REC (Se)

PB (PAL)

PB (Se)

REC

TH/DL

SWD

1/2FHM

TH/DL

(1/2FHTA)

PAL-M

PAL

BF Xch

TH/DL

(1/2FHTA)

XPB

MASK 75

MASK

U ERRI

1/2FHM

PAL-M

TH/DL

XFHM

1/2FHM

SA CONT

CLG PLS

CLP PLS

SWD

1/2FHT

1/2

FHT

SECAM

DETPLS

TEST

RST

Normal

SECAM

BELL IN

SECAM IN

H ID

Normal

1/2FHTAB

SWD1/2FHM

SWD1/2FHT

D ERRI

XSHP

BELL

FILTER

ADJ

BELL IN

MODE

SECAM

DL GAIN

ADJ

fsc IN

SQ ID

DL APC

LPF

C OUT

IREF

VREG

PB C IN

SECAM

ACK

1/2FHMP

75% C

DLDP

SECAM

JUMP

SECAM

LPF

AFC

LPF

C Sync

GND

MODE

C-BELL

BELL

AMP

VCO

S/H

Peak

Hold

LPF2

S/H

75%

MASK2

75%

MASK1

EDGE

TRIG

EDGE

TRIG

Secam

P. D.

Jump

P. D.

AFC

V-I1

P.D.

LPF1

LPF

CONT

Clamp

LPF1

DEMOD

LPF3

CONV1

Dummy

LIM

LIM1

LIM2

V-I2

LPF2

MAIN

Gen

75%

150%

1/2

CXA1203M/N

Pin Description

No.

Symbol

5.0V

(typ.)

Supply voltage pin

PB C
IN

350mVp-p
150mVp-p

(burst)

Input pin of PAL playback
chrominance signal.
The chroma ACK operates to
cut off the output at Pin 15
when the DC bias voltage at
Pin 2 is 0.7V or less.

SECAM
ACK

3.8V

(H)

0V
(L)

SECAM detector output pin.
H

SECAM

PAL

The SECAM or PAL mode is
fixed by applying an external
DC voltage.
SECAM: 3.0 to 5.0V
PAL: 0 to 1.0V

1/2
FHMP

Output pin of the pulse
obtained by dividing down the
AFC (f

-PLL) output by 2.

75% C

Connecting pin of the
charging and discharging
capacity to produce the
triangular wave chronized
with the C Sync signal.
All timing pulses used in the
IC are produced from this
triangular wave.

Voltage

Equivalent circuit

Description

3.2V

1.7V

3.5V

1.0V

3.0V

60k

47k

15.2p

20k

10k

(Sub)

4k/2

(

20k/3

(

(Sub)

(

28k

CXA1203M/N

No.

Symbol

DLDP

1.4Vp-p

Input pin to switch the polarity
of the 1/2FHT pulse for the
SECAM detector.
Output pin of the AFC ID
signal in TEST mode

SECAM
JUMP

2.8V

(H)

1.4V

(L)

2.8V

(H)

1.4V

(L)

1.4Vp-p

Output pin to switch the
polarity of the 1/2FHT pulse.
Mode selection

is possible

by applying an external DC
voltage.
PAL-M: 0 to 0.5V
Normal: OPEN
RESET: 3.6 to 4.1V
TEST: 4.3 to 5.0V

SECAM
LPF

2.5V

Connecting pin of the time
constant of the LPF for the
SECAM detector.

AFC
LPF

2.0V

Connecting pin of the time
constant of the LPF for the
AFC (f

-PLL).

Voltage

Equivalent circuit

Description

10k

20k

100k

(Sub)

100k

4k/2

10k

6.5k

10k

20k

(Sub)

(

CXA1203M/N

No.

Symbol

Output pin of the HD pulse
produced in the AFC (f

-PLL).

C Sync

Input pin of the composite
sync signal.
The internal threshold voltage
is 2.0V and the polarity is
active HIGH.

GND pin

VREG

4.2V

Output pin of the regulated
voltage source in the IC
(4.2V).

IREF

2.1V

Connecting pin of the
standard resistance to
produce the reference
current source in the IC.

Voltage

Equivalent circuit

Description

20k

(

(Sub)

(

20k

46k

20k

23p

Connected to
about 30
elements

(

32)

10k

(Sub)

(

IREF

40k

4.0V

0.4V

2.0V

GND

CXA1203M/N

No.

Symbol

DL APC
LPF

2.4V

Connecting pin of the time
constant of the LPF for the
TH/DL APC loop.
The TH/DL lock phase can
be varied by applying an
external DC current.

SQ ID

4.0V

(H)

0V
(L)

350mVp-p

Output pin of the SQ detector.
The TH or DL output signal at
Pin 15 can be selected by
applying an external DC
voltage.
DL: 0 to 2.0V
TH: 3.0 to 5.0V

fsc IN

Input pin of the fsc.
(chrominance subcarrier)

Voltage

Equivalent circuit

Description

10k

20k

(Sub)

30k

10.4p

In PAL

mode

350mVp-p
150mVp-p

(burst)

C OUT

2.1V

Output pin of the playback
PAL signal (TH, DL and EX
burst)

, SECAM signal and

PAL-M signal.

(

2.5k

CXA1203M/N

No.

Symbol

MODE

Mode selection

is possible

by applying an external DC
voltage.
REC: 0 to 1.3V
PB: 1.7 to 2.8V
JOG: 3.2 to 5.0V

BELL
IN

83mVp-p

(SECAM

burst)

117mVp-p

(PAL

burst)

Input pin of the SECAM
signal.
Input pin of the SECAM
detector in playback mode.

Voltage

Equivalent circuit

Description

(Sub)

13.5k

15k

38k

15.2p

100k

150mVp-p

(burst)

DL GAIN
ADJ

5.0V

(typ.)

Control pin of the DL signal
gain.
The gain can be varied by
applying an external DC
voltage. The internally fixed
gain is obtained at 5.0V.
Output pin of the S/H circuit
in TEST mode.

SECAM
IN

Input pin of the SECAM
detector in REC mode.

13.4k

2670

13.4k

15k

10k

40k

20k

15.2p

CXA1203M/N

No.

Symbol

ADJ

5.0V

(typ.)

EX burst phase adjustment
pin.
The phase can be varied by
applying an external DC
voltage. The internally fixed
phase is obtained at 5.0V.
VCO output pin in TEST
mode.

BELL
FILTER

3.0V

Connecting pin of the time
constant of the BELL and
C-BELL filters.

Voltage

Equivalent circuit

Description

10k

38k

30k

(Sub)

(

200

(

Notes)

Refer to Mode Description.

PAL playback signal (TH, DL and EX burst)

The DL signal is symmetrical to the TH signal (PAL playback signal) about the B-Y axis.

The burst signal produced from the fsc (chrominance subcarrier) in the IC is known as the EX burst.

The EX burst is inserted into the playback chrominance signal in JOG mode.

CXA1203M/N

Mode Description

Mode

PAL

SECAM

PAL-M

RESET

TEST

REC

JOG

Control pin

Pin 3

Pin 7

Pin 17

Pin 21

Voltage

0 to 1.0V

High impedance

3.0 to 5.0V

0 to 0.5V

3.6 to 4.1V

4.3 to 5.0V

0 to 2.0V

High impedance

3.0 to 5.0V

0 to 1.3V

1.7 to 2.8V

3.2 to 5.0V

Description

Fixed PAL mode

Automatic selection of PAL or SECAM

Fixed SECAM mode

The PAL-M signal is output from Pin 15 by inputting
an NTSC signal to Pin 2.
(For details, see "Notes on Use".)

The logic block (AFC ID, 150% masking and 1/2
division) in the AFC (f

-PLL) is turned off.

The operation of the AFC ID, VCO and S/H blocks in
the AFC (f

-PLL) is checked.

The DL signal is output from Pin 15.

The TH or DL signal selected by the SQ detector
decision is output.

The TH signal is output from Pin 15.

REC mode

Playback mode

The EX burst is inserted into the original burst signal
portion in PAL playback mode.

CXA1203M/N

Electrical Characteristics

(Ta = 25

°
C, V

= 5.0V, See Fig. 1. Electrical Characteristics Test Circuit.)

No.

Item

Circuit current

(PAL PB)

Circuit current

(SECAM REC)

VREG (5.0V)

VREG (4.5V)

VREG (5.5V)

V (IREF)

Input SW crosstalk

(SECAM REC)

Input SW crosstalk

(SECAM PB)

BELL FILTER gain

C-BELL FILTER

gain

TH Amp gain

TH/DL Amp gain

ratio

TH/DL phase

difference

TH/EXB level ratio

EX burst level ratio

EX burst phase

difference

TH-EX burst phase

difference

Symbol

(PP)

(SR)

VREG (5.0)

VREG (4.5)

VREG (5.5)

V (IREF)

I-CT (SR)

I-CT (SP)

BF-G

CBF-G

THA-G

DA-G

TH-DL

TH-EXB

EXB

TH-EXB

SW1

SW3

SW5

5.0V

4.5V

5.5V

5.0V

2.5V

1.0V

3.0V

1.0V

3.0V

1.0V

3.0V

2.0V

1.7V

1.3V

1.7V

1.3V

1.7V

1.3V

1.7V

2.8V

3.2V

Bias condition

Test

point

PAL PB

SECAM

REC

PAL PB

SECAM

REC

SECAM

REC

SECAM

PAL PB

PAL JOG

DC current test

DC voltage test

C OUT output

level test

C OUT output

level test

C OUT output

level test

(4.43MHz)

C OUT phase

test

Output

level

test

C OUT

Phase

test

17.5

20.0

4.10

2.05

11.0

3.0

2.5

0.6

1.1

1.0

25.5

27.0

4.24

2.12

38.0

53.0

14.0

0.3

0.4

2.6

32.5

34.0

4.40

2.20

35.0

45.0

16.0

3.0

2.0

1.4

120

4.1

1.0

102

deg

Output waveform and test

content

Min.

Typ.

Max.

Unit

Mode

Switch condition

ON : O, OFF: blank

CXA1203M/N

No.

Item

PAL-M DL APC

loop characteristics

PAL-M EX burst

level ratio

PAL-M EX burst

phase difference

PAL-M DL-EX burst

phase difference

SQ DET +V

detection

SQ DET

detection

Main SW crosstalk

(TH)

AFC HD timing

AFC HD width

AFC lock range (1)

AFC lock range (2)

TIMING EX burst

delay

TIMING EX burst

width

TIMING 1/2FHMP

delay

TIMING 1/2FHMP

duty

Symbol

DL-APC

(PAL M)

EXB

(PAL M)

EXB

(PAL M)

TH-EXB

(PAL M)

SQ (+)

SQ (

)

MSW-CT

(TH)

HD-D

HD-W

AFC-LR

(1)

AFC-LR

(2)

EXB-D

EXB-W

1/2FH-D

1/2FH-DU

Switch condition

ON : O, OFF: blank

SW1

SW3

SW5

5.0V

2.5V

1.0V

5.0V

3.8V

3.0V

2.8V

1.7V

3.2V

1.7V

Bias condition

Test

point

PAL-M

PAL

RESET

PAL PB

PAL JOG

PAL PB

C OUT phase

test

C OUT output

level test

C OUT phase

test

DC voltage test

at Pin 17

C OUT output

level test

Time test at

Pin 10

Frequency test

at Pin 10

Time test

100

1.5

104

122

3.0

4.4

4.5

3.9

32.0

1.2

5.3

5.2

4.4

36.0

1.5

0.3

6.2

5.8

5.1

40.0

deg

µs

Output waveform and test

content

Min.

Typ.

Max.

Unit

Mode

CXA1203M/N

4.286MHz CW

350mVp-p

CW delayed by

135

from Vfsc

350mVp-p

CW delayed by

135

from Vfsc

150mVp-p

Input signal

PAL

4.286MHz CW

350mVp-p

4.286MHz CW

32mVp-p

4.286MHz CW

83mVp-p

15.625kHz,

4.0Vo-p

Vsync

4.43MHz CW

350mVp-p

Vfsc

Test the DC voltage at Pin 13.

Test the DC voltage at Pin 14.

20 log

{

}

20 log

{

}

20 log

{

}

20 log

{}

20 log

{}

Test content

C OUT (4.286MHz component)

PAL

C OUT (4.286MHz component)

C OUT (4.43MHz)

PAL

Output level of T11

C OUT (4.43MHz)

Test Methods of Electrical Characteristics

No.

Item

Circuit current

(PAL PB)

Circuit current

(SECAM REC)

VREG (5.0V)

VREG (4.5V)

VREG (5.5V)

V (IREF)

Input SW crosstalk

(SECAM REC)

Input SW crosstalk

(SECAM PB)

BELL FILTER gain

C-BELL FILTER

gain

TH Amp gain

TH/DL Amp gain

ratio

TH/DL phase

difference

CXA1203M/N

CW delayed by

from Vfsc

150mVp-p

Input signal

PAL

15.625kHz,

4.0Vo-p

15.734kHz,

4.0Vo-p

Vsync

4.43MHz CW

350mVp-p

3.58MHz CW

350mVp-p

Vfsc

20 log

{}

7.4dB

(EB)

= 20 log {V

(EB1)

(EB2)

}

(EB)

Test

(DL) on the basis of Vfsc.

(EB)

= 20 log {V

(EB1)

(EB2)

}

(EB)

= |

T18

Test content

T11 (p-p)

(EB1 + EB2)/2

EB1

EB2

EB1

130mVp-p

EB2

EB1

EB2

YC MIX

C Sync

EB1

EB2

Vfsc

EB1

EB2

EB1

EB2

Vfsc

YC MIX

C Sync

130mVp-p

Phase difference between the center

of EX burst and TH signal.

Phase difference between the center

of EX burst and DL signal.

No.

Item

TH/EXB level ratio

EX burst level ratio

EX burst phase

difference

TH-EX burst phase

difference

PAL-M DL APC

loop characteristics

PAL-M EX burst

level ratio

PAL-M EX burst

phase difference

PAL-M DL-EX burst

phase difference

63.6

CXA1203M/N

Signal with the

phase delayed

from Vfsc

150mVp-p

Signal with the

phase delayed

from Vfsc

150mVp-p

Input signal

PAL

15.625kHz,

4.0Vo-p

19.0kHz

15.625kHz,

4.0Vo-p

Vsync

4.43MHz CW

350mVp-p

4.43MHz CW

350mVp-p

Vfsc

Test the phase of V

PAL

(on the basis of Vfsc) when DC

is changed from L to H (4.0V) at Pin 17.

Test the phase of V

PAL

(on the basis of Vfsc) when DC

is changed from H to L (0V) at Pin 17.

Test by TH signal timing.

Test the time at Pin 10.

Test the frequency at Pin 10.

Test the time at C OUT.

Test content

No.

Item

SQ DET +V

detection

SQ DET

detection

Main SW crosstalk

(TH)

AFC HD timing

AFC HD width

AFC lock range (1)

AFC lock range (2)

TIMING EX burst

delay

TIMING EX burst

width

4.0V

5.0

1.0kHz

3.5V

2.0V

C Sync

3.5V

C OUT

C Sync

(

Input frequency

)

CXA1203M/N

Fig. 1. Electrical Characteristics Test Circuit

20k

100k

50k

V21

50k

820

1.2k

33p

0.1

0.01

SW4

SW5

Vfsc

V17

1500p

100k

4.43MHz

BPF

0.1

50k

10k

4.7k

4.7

PAL

0.01

110p

0.047

1000p

SW2

Vsync

3.3

SW1

SW3

REC (Se)

PB (PAL)

PB (Se)

REC

TH/DL

SWD
1/2FHM

TH/DL

(1/2FHTA)

PAL-M

PAL

BF Xch

TH/DL
(1/2FHTA)

XPB

MASK 75 1

MASK
75 2

U ERRI

1/2FHM

PAL-M

TH/DL

XFHM

1/2FHM

SA CONT

CLG PLS

CLP PLS

SWD

1/2FHT

1/2
FHT

SECAM
DETPLS

TEST
RST
Normal

SECAM

BELL IN

SECAM IN

H ID

Normal

1/2FHTAB

SWD1/2FHM

SWD1/2FHT

D ERRI

XSHP

MODE

C-BELL

BELL

AMP

VCO

S/H

Peak

Hold

LPF2

S/H

75%

MASK2

75%

MASK1

EDGE

TRIG

EDGE

TRIG

Secam

P. D.

Jump

P. D.

AFC

V-I1

P.D.

LPF1

LPF

CONT

Clamp

LPF1

DEMOD

LPF3

CONV1

Dummy

LIM

LIM1

LIM2

V-I2

LPF2

MAIN

Gen

75%

150%

1/2

BELL

FILTER

ADJ

BELL IN

MODE

SECAM

DL GAIN

ADJ

fsc IN

SQ ID

DL APC

LPF

C OUT

IREF

VREG

PB C IN

SECAM

ACK

1/2FHMP

75% C

DLDP

SECAM

JUMP

SECAM

LPF

AFC

LPF

C Sync

GND

CXA1203M/N

Description of Functions

1. Gain Adjustment Amplifier (DL Signal)

This amplifier adjusts the gain of the DL signal in PAL or PAL-M mode. The amplifier gain varies according

to the DC voltage applied to Pin 19. When 5V is applied to Pin 19, the internally fixed gain is obtained and

the levels of the TH signal and the DL signal (4.43MHz component in PAL mode, 3.58MHz component in

PAL-M mode) become the same.

2. fsc 90° PLL,

×
×

2 and EX Burst Block

Fig. 2

The fsc 90° PLL consists of the 90° phase shifter, multiplier, LPF (low pass filter) 1 and V/I converter.

A signal delayed by 90° to the fsc is obtained in this PLL. By changing the DC voltage at Pin 23, the

amount of phase shift is varied. allowing adjustment of the phase of the EX burst and the duty (DC offset)

of the 2fsc. By applying 5V at Pin 23, the internally fixed phase shift is obtained. The 2fsc is produced

from the multiplier output (

2 output).

The EX burst is produced by adding the fsc (or inverted fsc) to the fsc with 90° delay produced in the 90°

PLL.

The fsc and the inverted fsc are switched in a period of 1/2f

, so the phase of the EX burst changes every

1H.

LIM

LPF1

fsc
cos

2fsc
cos (2

t 90

)

EX Burst

2 cos (

t 45

)

2 cos (

t 135

)

cos (

t 90

)

cos (

t 180

)

cos

1/2f

cos

ADJ

CXA1203M/N

Fig. 4

The above figure shows the relation between the phase of the burst signal, the phase of the fsc (fsc) and

the output at Pin 17 (SQ). As shown in the figure, the hysteresis angle is about 64°. If the relation is as

shown in the figure below, the detector judges it as the correct sequence and set the output at Pin 17 to

HIGH.

Fig. 5

Therefore, the center phase of the burst signal (about the B-Y axis) should be 90° to the fsc.

3. SQ DET (Sequence Detector)

Fig. 3

The SQ DET detects the color alignment of the chrominance signal. The SQ PD is the phase detector which

operates for a burst period only. This detects the color alignment by comparing the phase of the fsc signal

inverted every 1H with the phase of the burst of the chrominance signal.

1/2f

fsc

P.D.

LPF3

Chrominance signal

Burst Flag Gate

17 SQ

180

135

112

+48

+90

+135

+180

+112

Output at Pin 17

Phase of the burst signal
(on the bias of fsc and fsc)

B-Y

fsc

135

Burst

B-Y

fsc

+135

Burst

CXA1203M/N

Fig. 7

The V-Invert circuit constructs the TH/DL APC loop that keep the phase difference between the burst of the

TH signal and the burst of the DL signal to be 90°. This circuit detects the phase of the bursts of the TH and

DL signals and varies the delay time of the phase shifter

with reference to the error current of APC loop.

In PAL-M mode, the APC is applied to the fsc and the DL signal. Therefore, the input burst signal has a

phase of 90° to the fsc. The CONV1 is a multiplier to obtain the DL signal.

The Dummy supplies the same gain loss and the same phase delay as produced in CONV1 to the TH

signal so that there is no gain and phase difference between the TH signal and the DL signal.

The main SW outputs the TH or DL signal according to the TH/DL select signal (output at Pin 17). When a

BF Xch pulse is supplied (in JOG mode only), the EX burst is output.

4. V-Invert (V Axis Inversion Circuit)

For color alignment, the DL signal which is produced by inverting the chrominance signal (TH signal) about

the B-Y axis is necessary.

The V-Invert block produces the DL signal from the TH signal. Fig. 6 shows the principle of the V-Invert

block.

Fig. 6

Define the B-Y axis of the playback chrominance signal as cos

t and input the playback chrominance

signal and the 2fsc (cos 2

t) to the multiplier. By means of the frequency conversion of the 2fsc, the input

chrominance signal is inverted about the B-Y axis. The three fold frequency component (cos 3

t) is also

output, but this component is rejected by the BPF in a later stage.

Fig. 7 shows the actual V-Invert block.

fsc (cos

cos 2

DL: cos (

)

cos (3

)

TH: cos (

)

To
Y/C MIX BLOCK

Rejected by the BPF.

BPF

Playback chrominance
signal

cos (

)

V-I

LPF2

CONV1

Dummy

2fsc

BF Gate

EX Burst

fsc

PAL-M

PAL

TH/DL
BF Xch

Main
SW

SWD
1/2f

C OUT

Playback chrominance
signal

CXA1203M/N

Fig. 8

The AFC ID compares the C Sync frequency with the VCO frequency. When a frequency difference is

present, the AFC ID outputs an up or down error and roughly compensates the VCO frequency. In this

case, the AFC ID detects if the frequency difference continues for a period of 15H

6 (5760µs), and AFC

ID error is available only when the frequency difference continues for that period.

The AFC ID also detects the existence of C Sync. When the C Sync is missing in various speed mode, the

AFC ID cuts off its output and maintains the state immediately before the output cutout.

The phase lock of the C Sync and VCO frequencies is carried out in the PLL loop composed of the S/H and

LPF circuits.

6. BELL and C-BELL Filters

The Bell Filter is applied to the SECAM color TV signal to suppress the level near the chrominance subcarrier

, F

). In REC mode, the CXA1203 employs the BELL filter (having the inverted characteristics from the

Bell Filter) to obtain the chrominance subcarrier of the same amplitude at every hue. The output signal from

the BELL filter is sent to the record signal processing block of chrominance signal in the CXA1200.

In playback mode, the chrominance signal processed in the CXA1200 is input to the C-BELL (having the

same characteristics as the Bell Filter) filter of the CXA1203 to equalize the input signal with the SECAM

color TV signal. The output from the C-BELL Filter is mixed with the Y signal in the CXA1200 and sent to

the CXA1201. The typical input level of the BELL Filter is 32mVp-p, and that of the C-BELL Filter is 83mVp-p.

7. SECAM Detector Circuit

The SECAM detector circuit employed in the CXA1203 converts the chrominance subcarrier frequency

a voltage, and detects the color system by the voltage variation: PAL system if no voltage variation is

present, or SECAM system if the voltage varies every 1H. When the color alignment is carried out in

SECAM mode, the SECAM ACK output (Pin 3) is always set to HIGH by inputting the SECAM JUMP output

(Pin 7) to the DLDP (Pin 6).

PAL system:

color burst signal (4.43361875MHz)

SECAM system: line ID signal

: 4.40625MHz

: 4.25000MHz

5. f

PLL

VCO

S/H

XSHP

C Sync

AFC

LPF

1/2

1/2f

SWD 1/2f

CXA1203M/N

Fig. 9. Application Circuit 1 (for PAL/SECAM mode)

BPF

0.01

20k

33k

2.2k

22k

1.5k

20k

100k

100p

0.01

10p

1500p

15k

390k

27k

33p

0.1

110p

0.01

0.022

820

100k

1.2k

3.3

4.7

1000p

4.7k

10k

JOG

REC/PB

BELL IN

SECAM IN

fsc IN

PB
CHROMA
OUT

REC (Se)

PB (PAL)

PB (Se)

REC

TH/DL

SWD
1/2FHM

TH/DL

(1/2FHTA)

PAL-M

PAL

BF Xch

TH/DL
(1/2FHTA)

XPB

MASK 75 1

MASK
75 2

U ERRI

1/2FHM

PAL-M

TH/DL

XFHM

1/2FHM

SA CONT

CLG PLS

CLP PLS

SWD

1/2FHT

1/2
FHT

SECAM
DETPLS

TEST
RST
Normal

SECAM

BELL IN

SECAM IN

H ID

Normal

1/2FHTAB

SWD1/2FHM

SWD1/2FHT

D ERRI

XSHP

MODE

C-BELL

BELL

AMP

VCO

S/H

Peak

Hold

LPF2

S/H

75%

MASK2

75%

MASK1

EDGE

TRIG

EDGE

TRIG

Secam

P. D.

Jump

P. D.

AFC

V-I1

P.D.

LPF1

LPF

CONT

Clamp

LPF1

DEMOD

LPF3

CONV1

Dummy

LIM

LIM1

LIM2

V-I2

LPF2

MAIN

Gen

75%

150%

1/2

BELL

FILTER

ADJ

BELL IN

MODE

SECAM

DL GAIN

ADJ

fsc IN

SQ ID

DL APC

LPF

C OUT

IREF

VREG

PB C IN

SECAM

ACK

1/2FHMP

75% C

DLDP

SECAM

JUMP

SECAM

LPF

AFC

LPF

C Sync

GND

PB CHROMA IN

SECAM ACK

C Sync

Vcc

20k

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXA1203M/N

Fig. 10. Application Circuit 2 (for PAL mode only)

BPF

0.01

20k

33k

2.2k

22k

1.5k

20k

100k

100p

0.01

10p

1500p

110p

0.01

20k

100k

4.7

1000p

4.7k

10k

JOG

REC/PB

fsc IN

PB
CHROMA
OUT

20k

REC (Se)

PB (PAL)

PB (Se)

REC

TH/DL

SWD
1/2FHM

TH/DL

(1/2FHTA)

PAL-M

PAL

BF Xch

TH/DL
(1/2FHTA)

XPB

MASK 75 1

MASK
75 2

U ERRI

1/2FHM

PAL-M

TH/DL

XFHM

1/2FHM

SA CONT

CLG PLS

CLP PLS

SWD

1/2FHT

1/2
FHT

SECAM
DETPLS

TEST
RST
Normal

SECAM

BELL IN

SECAM IN

H ID

Normal

1/2FHTAB

SWD1/2FHM

SWD1/2FHT

D ERRI

XSHP

MODE

C-BELL

BELL

AMP

VCO

S/H

Peak

Hold

LPF2

S/H

75%

MASK2

75%

MASK1

EDGE

TRIG

EDGE

TRIG

Secam

P. D.

Jump

P. D.

AFC

V-I1

P.D.

LPF1

LPF

CONT

Clamp

LPF1

DEMOD

LPF3

CONV1

Dummy

LIM

LIM1

LIM2

V-I2

LPF2

MAIN

Gen

75%

150%

1/2

BELL

FILTER

ADJ

BELL IN

MODE

SECAM

DL GAIN

ADJ

fsc IN

SQ ID

DL APC

LPF

C OUT

IREF

VREG

PB C IN

SECAM

ACK

1/2FHMP

75% C

DLDP

SECAM

JUMP

SECAM

LPF

AFC

LPF

C Sync

GND

PB CHROMA IN

C Sync

Vcc

CXA1203M/N

Notes on Use

1. Phase Adjustment in PAL Playback Mode

The phase of the EX burst signal can be adjusted with the phase of the input fsc (chrominance subcarrier).

The phase of the DL signal can be adjusted by applying a current to Pin 16.

Adjust the phase of the fsc so that the phase of the EX burst signal in JOG playback mode matches the

phase of the color burst signal in normal playback mode at the PB CHROMA output (Pin 15).

Then, adjust the current to be applied to Pin 16 so that the DL signal becomes symmetrical to the TH signal

about the B-Y axis.

2. PAL-M Mode

Fig. 11

Input an NTSC signal to Pin 2, the fsc signal (3.58MHz) to Pin 18 and the C Sync signal (15.75MHz) to Pin 11.

Then the PAL-M playback signal is obtained at PB CHROMA output (Pin 15).

To adjust the phase, first input a burst signal with the same phase as the B-Y axis, and adjust the phase of

the fsc to be input so that the phase of the TH signal matches the center phase of the EX burst at Pin 15.

Then adjust the current to be applied to Pin 16 so that the phase of the DL signal matches the center phase

of the EX burst. In PAL-M mode, Pin 17 (SQ ID) should be fixed to "L".

3. PAL Only Mode

In PAL only mode, a part of the SECAM detector block is turned off by fixing Pin 22 (BELL IN) to "H". This

reduces the current consumption to 1.2mA. The connections for other pins are the same as shown in "Fig. 10

Application Circuit 2 (for PAL mode only)".

B-Y

R-Y

fsc

TH and DL
signals

EX burst

B-Y

R-Y

Output

Input

fsc

Input signal

CXA1203M/N

Example of Representative Characteristics

VREG supply voltage characteristic

Vcc (Pin 1) [V]

4.50

4.21

4.22

4.23

4.24

4.25

4.75

5.00

5.25

5.50

VREG (Pin 13) [V]

TH/DL/EX burst output level vs. Ambient temperature

Ta Ambient temperature [

100

120

140

160

Output level [mVp-p]

BELL Filter characteristic

f Frequency [MHz]

3.786

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

4.286

4.786

Vcc = 5.0V
SECAM/REC mode
Input level: 32mVp-p (BELL IN)
Output: C OUT (Pin 15)

Gain [dB]

C-BELL Filter characteristic

f Frequency [MHz]

3.786

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

4.286

4.786

Vcc = 5.0V
SECAM/PB mode
Input level: 83mVp-p (BELL IN)
Output: C OUT (Pin 15)

Vcc = 5.0V
PAL/PB mode
Input level: 150mVp-p (PB C IN)
fsc: 350mVp-p
Output: 4.43MHz BPF OUT
(The output level is the average during 2H.)

Gain [dB]

EX burst

CXA1203M/N

Phases of the HD and EX burst vs. Ambient temperature

Relation of the phase of each pulse to the C Sync signal

Ta Ambient temperature [

1.0

2.0

3.0

5.0

4.0

Time [

SQ DET input/output vs. Ambient temperature

Ta Ambient temperature [

100

120

Phase of the input signal [deg]

TH/DL/EX burst phases vs. Ambient temperature

Ta Ambient temperature [

106

104

102

100

112

110

108

Phase [deg]

Vcc = 5.0V
PAL/PB mode
Input level: 150mVp-p

(PB C IN)

fsc: 350mVp-p
Output: C OUT (Pin 15)

EX burst

Vcc = 5.0V
PAL/RESET mode
Input level: 150mVp-p

(PB C IN)

fsc: 350mVp-p
Output: SQ ID (Pin 17)

Output at Pin 17
L

Output at Pin 17
H

The phase is the absolute value
determined by measuring the
center angle of the TL, DL or EX
burst during 2H with reference to
the fsc (at Pin 18).

The phase of the input
signal is the absolute value
of the phase delay to the
fsc. This is determined by
delaying the phase of the
input signal to the fsc and
measuring the phase delay
when the output changes.

C Sync
(Pin 11)

HD
(Pin 10)

EX burst
(Pin 15)

CXA1203M/N

CXA1203M

Kokubu Ass'y

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42/COPPER ALLOY

24PIN SOP (PLASTIC)

15.0 0.1

+ 0.4

0.45

0.1

5.3

0.1

+ 0.3

7.9

0.4

0.2 0.05

+ 0.1

0.5

0.2

0.1 0.05

+ 0.2

0.15

1.85 0.15

+ 0.4

6.9

0.24

SOP-24P-L01

SOP024-P-0300

0.3g

1.27

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42/COPPER ALLOY

24PIN SOP (PLASTIC)

15.0 0.1

+ 0.4

0.45

0.1

5.3

0.1

+ 0.3

7.9

0.4

0.2 0.05

+ 0.1

0.5

0.2

0.1 0.05

+ 0.2

0.15

1.85 0.15

+ 0.4

6.9

0.24

SOP-24P-L01

SOP024-P-0300

0.3g

1.27

LEAD PLATING SPECIFICATIONS

ITEM

LEAD MATERIAL

COPPER ALLOY

SOLDER COMPOSITION

Sn-Bi Bi:1-4wt%

PLATING THICKNESS

5-18

SPEC.

Package Outline

Unit: mm

CXA1203M/N

CXA1203N

Sony Corporation

SONY CODE

EIAJ CODE

JEDEC CODE

SSOP-24P-L01

P-SSOP24-7.8x5.6-0.65

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

PALLADIUM PLATING

COPPER ALLOY

PACKAGE STRUCTURE

0.1g

24PIN SSOP (PLASTIC)

0.1

to 10

0.5

0.2

DETAIL A

5.6

0.1

7.8

0.1

0.65

7.6

0.2

0.1

1.25 0.1

+ 0.2

0.13 M

NOTE: Dimension "

" does not include mold protrusion.

0.15

0.01

DETAIL B : PALLADIUM

+ 0.03

b=0.22

0.03

Package Outline

Unit: mm

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1203M/N

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1203M/N