Description

The CXA1391Q/R is a bipolar IC developed for

signal processing in complementary color mosaic

CCD cameras.

Features

· Low power consumption (170mW)

· Number of delay lines used for signal processing

can be selected according to the system

requirements

· The LPF peripheral to 1H delay line is built in

Structure

Bipolar silicon monolithic IC

Applications

Complementary color mosaic CCD cameras

Absolute Maximum Ratings

· Supply voltage

Vcc

· Storage temperature Tstg

55 to +150

°C

· Allowable power dissipation

690

(LQFP: Ta = 25°C, without P.C.B)

Recommended Operating Conditions

· Supply voltage

Vcc

4.75 to 5.25

· Ambient temperature Topr

20 to +75

°C

CXA1391Q/R

E89Z18-ST

Processing IC for Complementary Color Mosaic CCD Camera

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA1391Q

64 pin QFP (Plastic)

CXA1391R

64 pin LQFP (Plastic)

C Y

C DL

VAP O

VAP G

I
N

P C

VAP

VAP SL

I
C

C CS

B-

G-

R-

CLP

(CLP2)

MPX

B
G
R

-CB

Y0
Y1

CS VAP

CS-Y

MAX

V-

APC

V-

APC

YH1

YH0

YH1

V-APCN

-
Y

B-

R-

LPF

(
C

LPF

CLP

(CLP4)

APCN

LPF

CLP

(CLP2)

CLP

(CLP4)

LPF

I
C

(
C

ue &

LPF

WB AMP

MATRIX

LPF

WB CONTROL

B-

R-

G-

R-

B-

CLP

(CLP2)

LPF

B-

R-

G-

C SLICE

WB DC

WB B

WB G

WB R

C-r CONT

GND 1

YL OUT

CS OUT

CS GAIN

R Y HUE

B Y HUE

R Y OUT

B Y OUT

B Y GAIN

R Y GAIN

LPF

ABS

S2 IN

S1 IN

CLP C YO

DLY0 OUT

DLY1 OUT

Y1 GAIN

DLY1 IN

DLY2 IN

Y2 GAIN

GND 2

LPF ADJ 1

LPF ADJ 2

LPF ADJ 3

Y-r CONT

YH IN

R M

P C

PX1

P C

PX2

B M

B G

I
N

R CO

R G

I
N

C B

C G

C R

EVEL

I
C

CLP

(CLP4)

(
C

CLP

(CLP4)

Block Diagram and Pin Configuration

(Top View)

CXA1391Q/R

Pin Description

No.

Symbol

CLP C Y

Pin voltage

3 to 3.5V

Equivalent circuit

Description

Capacitor connecting pin
for Y

clamp

(Clamp at CLP2)

DL Y

signal input pin

(Input from 1H delay line)

Sig: Typ. 200mV

(Positive polarity)

Capacitor connecting pin
for DL Y

clamp

(Clamp at CLP4)

DL Y

signal output pin

(To 1H delay line)

Sig: Typ. 400mV

Max. 600mV
(Negative polarity)

2.4k

180µA

80µA

147

800

80µA

147

2.6k

180µA

40µA

147

400µA

200

DL Y

3.65V

CLP C
DL Y

2.6 to 3.8V

DL Y

OUT

2.7 to 3.1V

Note) Pin voltage for input and output pins indicate black level.

CXA1391Q/R

OUT1

1.9 to 2.3V

1 signal output pin

Sig: Typ. 1V

Max. 1.5V
(Positive polarity)

160µA

100

400µA

100

80µA

500

30k

147

100k

30k

40µA

8 54

OUT2

1.9 to 2.3V

2 signal output pin

Sig: Typ. 1V

Max. 1.5V
(Positive polarity)

2.6 to 3.0V

)

2.5 to 2.9V

(G)

TP OUT (adjusting pin)
1H mode: Outputs Y

0H mode: Outputs Gch

C-slice OUT

(Mode selection is executed
through Pin 8)

DL Y

GAIN

(0H Mode)

1.8 to 5V

(1H Mode)

DL Y

signal gain control

pin
(For 1H delay line gain
compensation of Y

)

TP (Pin 7) mode selection

0H Mode: 0V
1H Mode: 1.8 to 5V

Y1 GAIN

0V:

Common

control by

Pin 57

1.8 to 5V

Independent

control

DLY

signal gain control pin

(1H delay line gain
compensation)
0V: DLY

signal gain

control is executed in
common with DLY

signal gain control.

1.8 to 5V: DLY

signal gain

control is executed
independently from
DLY

signal gain

control.

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1391Q/R

WB R

1.4 to 2V

R signal output pin
WB Mode:
Sig: Typ. 400mV

Mode:

Sig: Typ. 500mV

WB G

1.4 to 2V

G signal output pin
WB Mode:
Sig: Typ. 400mV

Mode:

Sig: Typ. 500mV

WB B

1.4 to 2V

B signal output pin
WB Mode:
Sig: Typ. 400mV

Mode:

Sig: Typ. 500mV

WB DC

1.4 to 2V

When used as output pin,
it is an Auto WB DC output
pin.
Pin 28, 29 and 30 turn
to WB mode.

When connected to Vcc:
Pins 28, 29 and 30 turn to

mode.

200µA

431

67µA

40µA

30k

18k

100k

200µA

431

100k

300

C SLICE

0V:

Slice OFF

Chroma (R.G.B) signals
dark slice level adjustment
pin

C LEVEL

1.8 to 5V

(Control)

Chroma (R.G.B) gain
control pin
(Chroma modulation factor
control for all 3 channels)

GAIN

1.8 to 5V

(Control)

DL C

signal gain control

pin
(1H delay line gain
compensation)

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1391Q/R

CLP C R

3.0 to 3.6V

Capacitor connecting pin
for R WB amplifier clamp
(Clamp at CLP2)

CLP C G

3.0 to 3.6V

Capacitor connecting pin
for G WB amplifier clamp
(Clamp at CLP2)

CLP C B

3.0 to 3.6V

Capacitor connecting pin
for B WB amplifier clamp
(Clamp at CLP2)

R GAIN

1.8 to 5V

(Control)

Rch WB amplifier gain
control pin
(Pre-WB)

B GAIN

1.8 to 5V

(Control)

Bch WB amplifier gain
control pin
(Pre-WB)

2.2k

125µA

40µA

10µA

80µA

15k

147

34 35 36

R CONT

2.5 to 4.6V

Rch WB amplifier gain
control pin

B CONT

2.5 to 4.6V

Bch WB amplifier gain
control pin

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1391Q/R

R MTX

1.8 to 5V

(Control)

(Preset)

R signal operations MTX
coefficient adjustment pin
(Coefficient 0.617)
Refer to Note 2.

2.6k

150µA

11µA

147

300k

147

100k

30k

40µA

100k

147

7.5k

40µA

40µ

48 55 56

DLC

C-Couple

input

3.1 to 3.5V

DL C

signal input pin

Sig: Typ. 150mVp-p

(Negative polarity)

DLY

C-Couple

input

3.6 to 4.0V

DL Y

signal input pin

Sig: Typ. 150mVp-p

(Negative polarity)

DLY

C-Couple

input

3.6 to 4.0V

DL Y

signal input pin

Sig: Typ. 150mVp-p

(Negative polarity)

S2 IN

1.9V

S2 signal input pin

Sig: Typ. 500mV

Max. 1500mV

S1 IN

1.9V

S1 signal input pin

Sig: Typ. 500mV

Max. 1500mV

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1391Q/R

CLP C Y

3.3 to 3.7V

Capacitor connecting pin
for Y

clamp

(Clamp at CLP4)

20k

10µA

300

80µA

147

15k

147

2.6k

40µA

150µA

59 60

GAIN

1.8 to 5V

(3H Mode)

(2H Mode)

DL Y

signal gain control

pin
(1H delay line gain
compensation)
V-APCON mode selection
0V: 2H Mode
1.8 to 5V: 3H Mode

LPF Adj. 1

1.8 to 2.2V

Connecting pin of the
external resistor that
determines the
characteristics of the LPF
for 1H DL.
(External resistor in the
range of 15 to 27k

)

LPF Adj. 2

1.8 to 2.2V

Connecting pin of the
external resistor that
determines the
characteristics of the
chroma LPF
(LPF for R, G, B, CS).
(External resistor in the
range of 15 to 62k

)

GND2

GND

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1391Q/R

Electrical Characteristics

Item

Current consumption

S2S1 Amp Gain

DLC

gain control

S1+S2 Amp

Chroma matrix
(Gch)

Note 3)

Chroma matrix
(Rch)

Note 3)

Chroma matrix
(Bch)

Note 3)

Max.

Min.

Gch Y

Rch C

Y
(Preset)

Y (Max.)

Y (Min.)

BchC

Y
(Preset)

Y (Max.)

Y (Min.)

SSG

DLC

SAG

RYP

RYH

RYL

BYP

BYH

BYL

Input: S1 IN = 62.5mV, S2 IN = 62.5mV
Calculations: DLC

OUT/S1 IN

Input: DLC

IN = 100mV

Conditions: C

Gain = 5V

C-level = 5V

Calculations: (WB-R/DLC

IN) CG Note2)

Conditions: C

Gain = 0V

(Others same as DLC

Input: S1 IN = 500mV
Calculations: DLY

OUT/S1 IN

Input: S1 IN = S2 IN = 300mV
Conditions: C-level = 5V
Calculations: WB-G (ID = H, L average)

Input: S1 IN = S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-G/GY (ID = L)

ID = H (Others same as GC

)

Input: S1 IN = 62.5mV, S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-R (ID = L)

Input: S1 IN = S2 IN = 500mV
Conditions: C-level = 5V
Calculations: WB-R/RC

(ID = H)

RMTX = 5V (Others same as RYP)

RMTX = 1.8V (Others same as RYP)

Input: S1 IN = 62.5mV, S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-B (ID = H)

Input: S1 IN = S2 IN = 500mV
Conditions: C-level = 5V
Calculations: WB-B/BC

(ID = H)

BMTX = 5V (Others same as BYP)

BMTX =1.8V (Others same as BYP)

0.9

1.1

0.15

0.22

0.11

0.2

0.31

0.13

34.5

1.95

0.85

100

0.168

0.25

0.125

100

0.22

0.34

0.15

120

1.1

0.9

100

0.186

0.27

0.14

120

0.24

0.37

0.17

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

WB
GAIN

RCONT Max.

RCONT Min.

BCONT Max.

BCONT Min.

RGAIN Max.

BGAIN Max.

RCH

RCL

BCH

BCL

RGH

BGH

Input: DLC

IN = 200mV

Conditions: C-level = 5V

RCONT = 4.6V (ID = H)

Calculations: WB-R/WB-RTyp. Note 4)
WB-R Typ. is the tested output of WB-R
when RCONT is set to 4V (Other inputs,
conditions same as RCH)

Test: RCONT = 2.5V

(Others same as RCH)

Input: DLC

IN = 150mV

Conditions: C-level = 5V

BCONT = 4.6V (ID = L)

Calculations: WB-B/WB-BTyp. Note 4)
WB-B Typ. is the tested output of WB-B
when BCONT is set to 4V (Other inputs,
conditions same as BCH)

Test: BCONT = 2.5V

(Others same as BCH)

Input: DLC

IN = 200mV

Conditions: RCONT = 2.5V RGAIN = 5V

C-level = 5V (ID = H)

Calculations: WB-R/WB-RMin.
WB-R Min. is the tested WB-R, when
tested under the same conditions as RCL.

Input: DLC

IN = 150mV

Conditions: BCONT = 2.5V BGAIN = 5V

C-level = 5V (ID = L)

Calculations: WB-B/WB-BMin.
WB-B Min. is the tested WB-B, when
tested under the same conditions as BCL.

7.5

8.4

7.5

8.4

8.6

11.4

8.2

7.9

8.2

7.9

9.2

12.2

8.5

7.4

8.5

7.4

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

Bch
color
difference
matrix

Note 5)

Gch
color
difference
matrix

Note 5)

RG OUT/
WB-B

RY OUT/
WB-B

BY GAIN
Max.

BY Hue Max.

BY Hue Min.

RY/RG

BY/BG

BMBY

BMRY

BMG

BMHH

BMHL

GMR

GMB

Input: S1IN = 200mV S2IN = 160mV

DLC

IN = 220mV

Conditions: C-

CONT = WB DC =

C-Slice = C-level = 5V
RCONT = 2.5V
BCONT = 4.6V (ID = L)

Calculations: BY OUT/WB-B

Conditions: RY GAIN = 1.8V
Calculations: RY OUT/WB-B

(Others same as BMBY)

Conditions: BCONT = 4V

1. BY OUT is tested when BY

gain = 0V and taken as A. (Other
conditions are the same as BMBY)

2. BY OUT is tested when BY

gain = 5V and taken as B. (Other
conditions are the same as BMBY)

Calculations: B/A

Conditions: BY HUE = 1.8V

(Others same as BMBY)

Calculations: RY OUT/BY Typ.
BY Typ. is the value of the tested BY
OUT when BY hue=0V (Other conditions
are the same as BMBY). Note 6)

BY HUE = 5V
(Others same as BMHH)

Input: S1IN = 830mV S2IN = 660mV

DLC

IN = 230mV

Conditions: WB-DC = C-level = 5V

RCONT = BCONT = 2.5V

1. RY OUT is tested when RY

gain = 0V and taken as A.

2. RY OUT is tested when RY

gain = 1.8V and taken as B.

Calculations: B/A

Input: (The same as GMR)
Conditions:

1. BY OUT is tested when BY

gain = 0V and taken as A.

2. BY OUT is tested when RY

gain = 1.8V and taken as B.
(Others same as GMR)

Calculations: B/A

0.4

0.24

3.0

0.58

0.81

0.63

0.44

0.21

3.3

0.68

0.67

0.85

0.66

0.48

0.17

0.58

0.89

0.7

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

C-Slice

Gch

curve

Typ.Min.

Typ.Max.

C-

CONT=0V

Gch-WB=400mV

C-

CONT=0V

Gch-WB=800mV

C-

CONT=0V

Gch-WB=100mV

C-

CONT=1.8V

Gch-WB=400mV

C-

CONT=1.8V

Gch-WB=800mV

C-

CONT=1.8V

Gch-WB=100mV

C-

CONT=5V

Gch-WB=400mV

C-

CONT=5V

Gch-WB=800mV

C-

CONT=5V

Gch-WB=100mV

CSLL

CSLH

Typ.

Input: DLY

IN = 400mV

Conditions: C-level = 5V

GAIN = 1.8V

C-Slice = 1.8V (ID = H)

Calculations: C-Slice Typ. -TP
C-Slice Typ. is the TP output of
C-Slice = 0V.

Conditions: C-Slice =5V

(Others same as CSLL)

Input: DLY

IN = 200mV

S1IN = S2IN = 500mV

Conditions: Y

GAIN = 1.8V

C-level is valied and
adjusted to obtain 400mV at
WB-G.
After that C-level is fixed
during test.

WB-DC is set to OPEN during C-level
adjusted and set to 5V during test.
Calculations: WB-G is tested.

Input: DLY

IN = 400mV

S1IN = S2IN = 1000mV

Conditions: Same as

Typ.

Calculations: WB-G/

Typ.

Input: DLY

IN = 50mV

S1IN = S2IN = 125mV

(Others same as

L8)

Input: DLY

IN = 200mV

S1IN = S2IN = 500mV

Conditions: C

CONT = 1.8V

Calculations: WB-G/

Typ.

Input: DLY

IN = 400mV

S1IN = S2IN = 1000mV

(Others same as

M4)

Input: DLY

IN = 50mV

S1IN = S2IN = 125mV

(Others same as

M4)

Input: DLY

IN = 200mV

S1IN = S2IN = 500mV

Conditions: C

CONT = 1.8V

Calculations: WB-G/

Typ.

Input: DLY

IN = 400mV

S1IN = S2IN = 1000mV

(Others same as

H4)

Input: DLY

IN = 50mV

S1IN = S2IN = 125mV

(Others same as

H4)

450

1.13

0.36

0.9

1.13

0.45

0.9

1.13

0.26

120

500

1.2

0.4

1.2

0.5

1.2

0.3

145

550

1.25

0.44

1.1

1.25

0.55

1.1

1.25

0.35

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

AMP

Chroma level Max./Min.

WB DC

1.0 (Typ.)

2.0/Y

1.0

0.5/Y

1.0

0.5 (Max.)/

1.0

0.5 (Min.)/

1.0

TP (YH)

TP (DLY

)

TP (GWBS)

Min. Gain

Max. Gain

2.0

0.5

TPY

TPDY

TPG

YLG

YHG

GCL

WDDC

Input: Y

IN = 220mV

Calculations: DLY

OUT

Input: Y

IN = 440mV

Calculations: DLY

OUT/Y

Input: Y

IN = 110mV

Calculations: DLY

OUT/Y

Input: Y

IN = 110mV

Conditions: Y

CONT = 1.8V

Calculations: DLY

OUT/Y

Input: Y

IN = 110mV

Conditions: Y

CONT = 5V

Calculations: DLY

OUT/Y

Input: Y

IN = 220mV

Conditions: DLY

GAIN = 1.8V

Calculations: TP/DLY

OUT

Input: DLY

IN = Y

0.7

Conditions: Same as TPY
Calculations: TP/DLY

OUT Note 7)

Input: S1IN = S2IN = 500mV

DLY1IN = 200mV

Conditions: Y1GAIN = 1.8V
Calculations: TP/WB-G

Input: Y

IN = 220mV

DLY

IN = [Y

3.5dB]

Conditions: DLY

GAIN = 1.8V

Calculations: TP is tested to check that

the signal level is below
0mV in relation to black
level. Note 8)

Input: Y

IN = 220mV

DLY

IN = [Y

12dB]

Conditions: DLY

GAIN = 5V

Calculations: TP

is tested to check that

the signal level is over
0mV in relation to black
level. Note 8)

Input: DLC

IN = 200mV

Conditions:

1. WB-G is tested when C-level = 5V

and taken as GC-level Min.

2. WB-G is tested when C-level = 1.8V

and taken as GC-level Max.
(Both 1 and 2 test at ID-H.)

Calculations: GC-level Max. /

GC-level Min.

Test: WB-DC

440

1.23

0.59

0.64

0.54

1.55

1.4

400

1.37

0.66

0.71

0.6

1.65

1.6

360

1.51

0.73

0.78

0.66

3.5

1.75

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

Note 5)

OUT1 (OH mode)

OUT1 1H/0H

OUT2 (0H) /Y

OUT1

OUT2 (1H) /Y

OUT1

VAP Typ.

Note 9)

VAP Slice

Note 9)

OUT/

OUT

OUT/

OUT

OUT/

OUT

YH1Z

YH1O

YH2Z

YH2O

VAPT

Input: S1IN = 150mV S2IN = 450mV
Conditions: C-

CONT = WB

DC = C-Slice =
C-level = 5V
RCONT = 4.6V BCONT = 2.5V
BGAIN = 1.8V (ID = L)

Calculations: Y

OUT/WB-R

Input: S1IN = 200mV S2IN = 160mV

DLC

IN = 220mV

Conditions: C-

CONT = WB

DC = C-Slice =
C-level = 5V RCONT = 2.5V
BCONT = 4.6V (ID = L)

Calculations: Y

OUT/WB-B

Input: S1IN = 830mV S2IN = 660mV

DLC

IN = 230mV

Conditions: WB-DC = C-level = 5V

RCONT = BCONT = 2.5V

Calculations: Y

OUT/WB-G

Input: Y

IN = 220mV

Calculations: Y

OUT1 is tested.

Input: DLY

IN = (Y

4dB)

Conditions: DLY

GAIN = 1.8V

Calculations: Y

OUT1/YH1Z Note 8)

Input: Y

IN = 220mV

Calculations: Y

OUT2/YH1Z

Input: Y

IN = 220mV

Conditions: DLY

GAIN = 1.8V

Calculations: Y

OUT2/Y

OUT2Typ.

OUT2Typ. is Y

OUT2 output tested at

YH2Z.

Input: S1IN = S2IN = 125mV
Conditions: VAP GAIN = 1.8V

VAP Slice = 1.8V
Y

GAIN = 1.8V

Calculations: VAP OUT is tested.

Input: S1IN = S2IN = 1000mV
Conditions: Y

GAIN = 1.8V

1. VAP OUT is tested when VAP

Slice=1.8V and taken as SMin.

2. VAP OUT is tested when VAP

Slice=5V and taken as SMax.

Calculations: SMax.SMin. Note 10)

0.27

0.08

0.54

900

6.5

250

256

0.3

0.1

0.6

1000

200

320

0.34

0.12

0.66

1100

5.5

150

384

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

DLY

gain

Note 11)

DLY

gain

Note 11)

Note 12)

Min.

Max.

Min.

Max.

VCS Typ.

VCS Min.

VCS Max.

VCS Typ.

VCST

VCSL

VCSH

CST

Input: S1IN = S2IN = 500mV

DLY

IN = 200mV

Conditions: VAP GAIN = VAP

Slice = Y

GAIN = 1.8V

Calculations: VAP-OUT is tested to check

that the signal level is over
0mV in relation to black
level.

Input: S1IN = S2IN = 500mV

DLY

IN = 110mV

Conditions: VAP GAIN = VAP Slice =

1.8V

GAIN = 5V

Calculations: VAP-OUT is tested to check

that the signal level is below
0mV in relation to black
level.

Input: S1IN = S2IN = 167mV

DLY

IN = 66.7mV

Conditions: VAP GAIN = VAP

Slice = Y

GAIN = Y

GAIN = 1.8V

Calculations: VAP-OUT is tested to check

that the signal level is over
0mV in relation to black
level.

Input: S1IN = S2IN = 167mV

DLY

IN = 37.5mV

Conditions: Y

GAIN = 5V

(Others same as DY

Calculations: VAP-OUT is tested to check

that the signal level is below
0mV in relation to black
level.

Input: S1IN = S2IN = 167mV
Conditions: Y

GAIN = Y

GAIN = 1.8V

CS GAIN = 5V

Calculations: CS OUT is tested.

Conditions: CS GAIN = 0V

(Others same as VCST)

Calculations: CS OUT/VCST

Conditions: CS GAIN = 1.8V

(Others same as VCSL)

Input: CS-IN = 500mV

4.4

440

120

465

150

0.05

490

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA1391Q/R

Note 1) For pins without specific instructions regarding input, feed the DC value shown on the Test Circuit.

Calculations are mentioned utilizing the pin name or the electrical characteristics symbols. Otherwise,
for exceptional notations explanatory notes, are given with every case.

Note 2) In this item, the gain of DLC

amplifier exclusively is calculated. CG is the gain of the system from

DLC

IN to WB-R from which DLC

GC amplifier gain has been excluded.

--CG calculating method--
In the actual calculation, the system on C

side is utilized.

Input: S1IN = 62.5mV

S2IN = 62.5mV

Condition: Same as DLC

Calculations: CG = 20log (WB-R/DLC

OUT)

Note 3) Chroma matrix operations

R = 2 [C

: Control with RMTX (Preset 0.167)

G = Y (C

+ C

)

B = 2 [C

+ ß (Y C)]

ß: Control with BMTX (Preset 0.22)

Note 4) With the typical gain taken when R CONT is at 4V, compare with the gain during Max. and Min. The

same for B CONT.

Note 5) Adjustment and testing is performed so that signals are output only for each of R, G, B channels

respectively.

Note 6) Comparison with BY OUT when RY HUE = 0V (HUE OFF).

The same for BY HUE.

Note 7) The compensation of difference in gain of Y

0 andY

1 is as follows.

1) At DLY

GAIN = 1.8V, DLY

amplifier gain is 3dB.

2) Test DLY

OUT (tested at YrT) when Y

IN = 220mV signal is input.

3) The difference in gain between Y

0 and Y

1 is compensated by inputting the signal as 3dB to

DLY

IN.

Note 8) The amplifier input is varied and the gain confirmed.

Note 9) VAP (Vertical Aperture Compensation)

Note 10) Dark slice variable volume. (Output level difference between the value slice volume at Max. and slice

volume at Min.)

Note 11) Utilizing V-APCN 2H mode, DLY

amplifier exclusive gain is obtained through operations. However,

as the amplifier gain cannot be tested directly, only the upper and lower limits of the gain control are
checked according to the following method.

(a) Lower limit check

S1 IN = S2 IN = 500mV (At that time KNEE circuit input turns to 200mV)
DLY

IN = 200mV (For others refer to the conditions chart)

In this condition, if we have VAP OUT

0, this indicates that DLY

amplifier is below 0dB.

(b) Upper limit check

S1 IN = S2 IN = 500mV
DLY

IN = 110mV (in (a) the 5dB of 200mV)

In this condition, if we have VAP OUT

0, this indicates that DLY

amplifier is above 5dB.

Note 12) CS (Chroma Suppress)

CXA1391Q/R

CLP

C YH

CLP

C DLY

DLY

H O

YH O

CLP

VAP OU

VAP GA

P C VAP

VAP SLIC

CLP

C CS

C S

I
C

C-

r
CO

ND 1

R-

HUE

B-

Y H

R-

B-

Y O

B-

Y G

I
N

R-

I
N

C Y

ND 2

-
r
CO

DLC1

DLCO

R MT

P C M

PX1

P C M

PX2

B MT

B GA

B CO

R CONT

R GA

CLP

C B

CLP

C G

CLF

C R

C L

EVEL

27k

62k

95V

.
1

3.65V

.
1

62k

B-r

G-r

R-r

(
C

-C

VAP

-
Y

V-APC

V-

APC

G c

h S

LIC

CS-Y

B-Y

R-Y

CLP

LP4)

(
C

APC

KNEE

(
C

CLP

SLIC

CLP

LP4)

YL M

MTX

Hue &

I
X

B-Y
R-Y

G-W

R-W

B-W

(
C

B-r

R-r

G-r

KNEE

ABS

KNEE

SLIC

(
C

CLP

LP4)

(
C

Test Circuit

(Typ. setting)

Note 1)

is unit of capacitor

Note 2)

indicates testing pin. (AC, DC test)

Note 3)

Input pin DC value indicates input signal black level.

Note 4)

indicate relay, side, normal close.

CXA1391Q/R

RY/BY GAIN voltage (V)

GAIN

RY/BY GAIN control characteristics

Y1/Y2 GAIN voltage (V)

GAIN

Y1/Y2 GAIN control characteristics

C-SLICE control characteristics

GAIN

1.5

0.5

C-LEVEL voltage (V)

C-SLICE control characteristics

C-SLICE power supply (V)

(mV)

150

100

BLACK DC difference between sliced
signal and during sliced OFF

RY/BY HUE control characteristics

RY/BY HUE voltage (V)

40°

30°

20°

10°

0°

20°

30°

CS GAIN control characteristics

CS GAIN voltage (V)

400

(mV)

300

200

100

CS output during
S1 = S2 = 125mV input
(3H_Mode)

CXA1391Q/R

Chroma

curve (standardize)

1.2

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

input (standardize)

output (standardize)

curve (standardize) (mV)

output (standardize)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

input (standardize)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

V-APCN Knee (standardize) (mV)

Knee output (standardize)

1.0

0.2

Knee input (standardize)

Standardize at typical input (S1 = S2 = 500mV)

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.8

0.6

0.4

0.2

2.0

Standardize at typical input (220mV)
1: Y

CONT=1.6V (Max.)

2: Y

CONT=0V (Typ.)

1: Y

CONT=5V (Min.)

Standardize at typical input (400mV)
1: C

CONT=1.6V (Max.)

2: C

CONT=0V (Typ.)

1: C

CONT=5V (Min.)

Standard Design Data

CXA1391Q/R

-
I
N

XSP3

XSP2

XSP1

-
C

XSH

CLP

XSHD

XSHP

AGC

-SEL

AGC

-M

C-CO

OP-O

OPIN

-N

OPIN

-P

AGC

-O

C-CL

DET

LEVEL

XSH1

DC-O

GY-O

F1-O

F2-O

F3-O

CS-C

CS-CCD-

CS-O

-AG

C-G

CS-A

-
G

I
R

I
S

-
L

EVEL

-
CL

-
C

-
O

PBL

1390 Q

/
R

-
O

-
G

-
I
N

-
G

-
A

-
I
N

YO-

CLP

S1-I

S2-I

DLC1

-IN

C1-G

AIN

DLCO

-O

R-M

MPX2

-C

MPX1

-C

B-M

B-G

AIN

B-CO

R-CO

R-G

AIN

B-C

G-C

R-CL

LEVEL

YH-

CLP

DLY

H-I

DLY

H-C

DLY

H-O

YH-O

YH-G

AIN

CLP

VAP-O

VAP-G

AIN

VAP-C

VAP-SL

CS-C

CS-I

R-Y

B-Y G

AIN

B-Y O

C-

I
C

-
D

-
B

-
G

-
R

-
C

-
O

S-

I
N

R-

HUE

B-

Y H

R-

1391 Q

/
R

I
SE-

I
C

-
C

-
I
N

-
Y

H CL

-
Y

B-

EVEL

B-

Y I

B-

SHP-

LEVEL

DLE

SHP-

DLD

SHP-

Y-L

EVEL

DER-

SIG

SETU

SYNC

-L

EVEL

SYNC

R-Y

CLP

4FS

LALT

FSC

-O

BFG

CBL

CTB

SET

V-

I
D

O-

CHRO

-
O

C-

I
N

C-

-
Y

-
A

1392 Q

/
R

DR-O

CT-B

DY-O

YT-B

DY-C

DY-I

YG-I

YR-I

YB-IN

YT-G

CT-G

CLP

DB-O

DB-I

DR-IN

GND

CB-I

CG-I

CR-IN

HYS-

CONT

TH-C

COM

P-I

COM

P-

OUT

DET

ECT

I
HDL

BPF

1393A

/
A

CCD

XSH

XSP1

XSP2

XSH

HD.

XSH

I
D

PBL

SYN

f
S

CXA

Series System Diagram

CXA1391Q/R

Package Outline

Unit: mm

CXA1391Q

CXA1391R

SONY CODE

EIAJ CODE

JEDEC CODE

23.9 ± 0.4

20.0 0.1

1.0

0.4 0.1

+ 0.15

14.

0.15 0.05

+ 0.1

2.75 0.15

16.

0.1 0.05

+ 0.2

8 ±

± 0.12

0.15

+ 0.4

17.9 ±

0.4

+ 0.35

64PIN QFP(PLASTIC)

QFP64PL01

QFP064P1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER/PALLADIUM

COPPER /42 ALLOY

PACKAGE STRUCTURE

PLATING

1.5g

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY / PHENOL RESIN

SOLDER PLATING

42 ALLOY

PACKAGE STRUCTURE

12.0 ± 0.2

10.0 ± 0.1

(0.22)

0.18 0.03

+ 0.08

0.5 ± 0.08

0.5 ±

0.2

(11.0)

0.127 0.02

+ 0.05

1.5 0.1

+ 0.2

0.1 ± 0.1

0.5 ±

0.2

0° to 10°

64PIN LQFP (PLASTIC)

LQFP-64P-L01

QFP064-P-1010-A

0.3g

DETAIL A

0.1

NOTE: Dimension "

" does not include mold protrusion.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1391R

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1391R