High-Speed Sample-and-Hold IC

Description

The CXA1843Q is a bipolar IC designed to sample-

and-hold video and various other signals with high

speed. It is ideal for video and other signal

conversions.

Features

· Maximum operating rate = 33MHz (min.)

· Low power consumption: 320mW

· S/H clock pulse generator circuit

· Built-in clock pulse generator for A/D converter

Applications

When used in combination of the CXA1844Q, the

CXA1843Q achieves A/D conversion.

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage V

· Input voltage

(VIN pin)

to AV

+ 0.3

(REFIN pin)

REFIN

+1 to AV

+ 0.3

(CLKIN pin)

CLK

GND 0.5 to DV

+ 0.3 V

(REX 2, 3, 4 pins) V

REX2, 3, 4

GND to GND + 4

· Reference voltage

(REFFB pin)

REFFB

to +3

(REFOUT pin)

REFOUT

to AV

+ 0.3

· Output current

(REFFOUT pin) I

REFOUT

1 to +1

(SHOUT pin)

SHOUT

12 to +12

(CLKOUT pin)

ADC

1.5 to +1.5

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

1.1

Operating Conditions

· Supply voltage

4.75 to 5.25

· Operating temperature

opr

20 to +75

°C

Structure

Bipolar silicon monolithic IC

Block Diagram and Pin Configuration

E92855B7Y

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA1843Q

32 pin QFP (PIastic)

A/D CONVERTER

PULSE

GENERATOR

SAMPLE HOLD

PULSE

GENERATOR

REF DC

SHIFT

REFFB

REFOUT

SHOUT

REX3

REX4

CLK IN

HGND

VIN

CGND

CLKOUT

GND

REX2

REF IN

SAMPLE

HOLD

For the availability of this product, please contact the sales office.

CXA1843Q

No.

Symbol

CC3

EE3

REFOUT

REFFB

CC4

REFIN

REX2

5V (Typ.)

2.8V
As shown in the
Application
Circuit, PNP TR.
is connected
and 2.5V is
applied to
Pin18.

Pin voltage

Equivalent circuit

Description

Analog positive power supply.

Analog negative power supply.

Connect the base of the
external PNP transistor to
create a 2V power supply.

Connect the emitter of the
external PNP transistor to
create a 2V power supply.

Connect to AGND.

Analog positive power supply.

External DC input for adjusting
the 2V power supply.

Connect external resistor that
determines the time interval (T

)

between master clock (MCLK)
rise and A/D converter clock
(A/D CLK) fall.
(Normally connect to 1.6k

)

Connect to AGND.

2V
As shown in the
Application
Circuit, PNP TR.
is connected
and 2.5V is
applied to
Pin18.

5V (Typ.)

2.5V (Typ.)

Approx. 0.5V
When external
resistor is
connected
between Pin 19
and AGND

EE3

CC4

130

400µ

REFFB

REFOUT

EE2

GND

REFIN

CC4

130

300µ

CC2

REX2

GND

EE2

130

0.5V

CXA1843Q

No.

Symbol

GND

CLKOUT

CC1

CC2

EE1

REX3

REX4

EE2

CC3

CLKIN

H:
DV

CC2

0.78V

L:
DV

CC2

1.52V

(Typ.)

Approx. 0.5V
When external
resistor is
connected
between Pin 27
and DGND

Pin voltage

Equivalent circuit

Description

GND

A/D converter clock (A/D CLK)
output.

Digital positive power supply.

Connect to DGND

Digital negative power supply.

Connect external resistor that
determines the time interval (T

)

between master clock (MCLK)
rise and sample-and-hold
internal clock (S/H CLK) rise.
(Normally connect 2.7k

)

Connect external resistor that
determines the time interval (T

)

between master clock (MCLK)
rise and sample-and-hold
internal clock (S/H CLK) rise.
(Normally connect 1.5k

)

Digital negative power supply.

Digital positive power supply.

Master clock (MCLK) input.
TTL level.
(Vth = 1.5V)

Connect to DGND.

5V (Typ.)

Approx. 0.5V
When external
resistor is
connected
between Pin 28
and DGND

5V (Typ.)

EE2

GND

CC2

600

2.2mA

CLKOUT

EE2

GND

REX4

REX3

130

0.5V

CC2

300µ

130

EE2

GND

CLKIN

CC3

CXA1843Q

Electrical Characteristics

(Ta = 25°C, V

= 5V, V

= 5V)

= 1kHz, distortion factor

55dB

20Log (V

(16.5MHz)/V

(200kHz)),

Sampling time = 14ns

= 50pF

REFIN

= 2.5V

REFIN

= 2.5V

CLKIN

= 0V

CLKIN

= 5V

= 1V

= 2V to 0V

= 16.5MHz (2Vp-p)

= 1V, F

CLK

= 33MHz

= 1kHz (2Vp-p),

CLK

= 33MHz

Maximun operating rate

VIN

HMDR

HMTH

OFFSET

Gsh

Fsh

REFIN

REFFB

CLKL

CLKH

CLKL

CLKH

PWH

PWL

ADCL

ADCH

Current consumption

S/H Amplifier Block

input current

input voltage range

Droop

Feed through

S/H output offset voltage

S/H output gain

S/H output frequency
response

S/H output slew rate

Reference Amplifier Block

REFIN input current

REFFB output voltage

Digital I/O Block

CLKIN input current

CLKIN input voltage

CLKIN clock width

A/D clock low level

A/D clock high level

Item

Symbol

Conditions

Min.

Unit

MHz

µA

2.2

0.2

mV/µs

120

0.5

0.3

0.5

0.2

140

160

200

V/µs

µA

2.2

2.0

1.8

µA

0.8

2.0

1.52 V

1.40

0.90 V

0.78

Typ.

Max.

CXA1843Q

Timing Chart

MCLK(Pin 31)
(TTL)

(Pin 3)

(0 to 2V)

S/H CLK
(Not output to outside)

S/H OUT (Pin 11)
(0 to 2V)

A/D CLK (Pin 22)
(PECL)

A/D output (CXA1844Q)
(TTL)

MCLK
(Clock pulse for the
device next to the ADC
in order to latch the
A/D output)

N + 1

N + 2

Tsd

PWL

PWH

Hold

taqr

tdr

N 1

tdf

taqf

2Vp-p

90%

10%

6ns

(min)

(max)

DN 3

Threshold
voltage =
1.5V

Threshold
voltage =
V

1.2V

Threshold
voltage =
1.5V

Threshold
voltage

DN 2

DN 1

10%

90%

N + 2

N + 1

Hold

Sample

Hold

Sample

Hold

Tsd

Sample

MCLK:

System master clock.

S/H CLK:

This clock actuates the internal sample-and-hold circuit.
The internal clock pulse circuit generates the S/H CLK, which is not output outside the IC.

A/D CLK:

This clock actuates the A/D converter. The internal clock buffer circuit generates the A/D CLK.
This clock has the level where +5V is shifted from the ECL level.

PWH

, T

PWL

S/H CLKIN input clock width

Tsd:

S/H sampling delay for the S/H internal clock

Fixed time interval between master clock rise and A/D CLK rise, T

= 6ns (typ.)

Time interval between MCLK rise and A/D CLK fall

Time interval between MCLK rise and S/H CLK rise

Time interval between MCLK rise and S/H CLK fall

aqf,

df:

10%/90% falling output delay of S/H from MCLK rise

aqr,

dr:

10%/90% rising output delay of S/H from MCLK rise

(min., max.): Minimum/maximum output delay of A/D converter (Refer to the CXA1844Q specification.)

Ts:

Setup time of A/D output and MCLK

Th:

Hold time of A/D output and MCLK

CXA1843Q

(NC)

REX3

REX4

CLKIN

(NC)

VINL

VINH

(NC)

AGND

(NC)

UNDER

OVER

DGND1

HGND

VIN

CGND

(NC)

REFFB

REFOUT

SHOUT

(NC)

CLKOUT

GND

(NC)

REX2

REFIN

DGND

REX3 0.1µ DGND

REX4 0.1µ DGND

DGND

0.1µ

DGND

0.1µ

DGND

0.1µ

DGND

MCLK

AGND

0.1µ

VIN

AGND

0.1µ

AGND

0.1µ

AGND

0.1µ

AGND

0.1µ

AGND

47µ

AGND

25A1005

AGND

0.1µ

47µ

0.1µ

AGND

430

REX2

DGND

0.1µ

DGND

CXA1843Q

200

0.1µ

AGND

0.1µ

AGND

0.1µ

DGND

0.1µ

DGND

0.1µ

ENABLE

MINV

LINV

DGND

0.1µ

AGND

DGND

AGND

0.1µ

AGND

47µ

ENABLE

CLK

MINV

LINV

(NC)

DGND2

DGND1

(NC)

REFBS

REFB

REF3

REF2

REF1

REFT

REFTS

(NC)

DGND3

DGND4

DGND1

UNDER

OVER

CXA1844Q

TTL

VIN = 2Vp-p (max) DC 1V

Application Circuit

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Symbol

REX2

REX3

REX4

External resistance

1.6k

2.7k

1.5k

Metal film resistors must be connected

to the REX2 to REX4 pins.

CXA1843Q External Resistance

CXA1843Q

Notes on Operation

(1) In circuit board layout, it is necessary that the AGND and DGND patterns be as large as possible and that

double or more layer pattern be used to make low impedance.

(2) To prevent digital system noise interference with the analog system, the AGND and DGND, AV

and

, AV

and DV

on the PCB must be separated from each other. However, connect the AV

and

with coil and others to prevent the generation of differential voltage.

(3) The AV

, DV

, AV

and DV

pins must be connected to the AGND or DGND respectively via ceramic

chip capacitors those are 0.1µF or more, as close to the pin as possible.

(4) The length of the wiring between the S/H SHOUT and A/D converter V

should be as short as possible.

(5) The range of the signal input to V

(Pin 3) of the sample-and-hold circuit is 0 to 2V.

(6) Adjust the V

REFIN

applied voltage so that V

REFFB

= f 2V.

(7) As shown in the Block Diagram, the amplifier input and output are internally connected to the REFOUT

and REFFB pins. To generate REFFB voltage for the reference voltage of A/D converter, the connection

of an external PNP transistor (hFE

100 (typ.)) is required as shown in the Application Circuit.

(8) Make the S/H DV

CC2

voltage equal to the A/D converter DV

CC1

voltage.

CXA1843Q

[ns]

vs. REX2

0.5

Ta [°C]

A/D clock width Tpwh variation [ns]

A/D clock width Tpwh (T

-T

) variation vs. Ta

(Ta = 25°C typ.)

0.5

5.25

4.75

[V]

0.5

REX2 [k

]

For normal use. REX = 21.6k

A/D clock width Tpwh (T

-T

) variation vs. V

= 5.0V typ.)

0.5

4.75

5.25

[V]

0.5

A/D clock width Tpwh (T

-T

) variation vs. V

= 5.0V typ.)

tdr, tdf, taqr, taqf [ns]

S/H output delay (tdr, tdf) vs. REX3

(taqr, taqf) vs. REX4

1.5

Ta [°C]

S/H output delay variation [ns]

0.5

S/H output delay variation vs. Ta

(Ta = 25°C typ.)

0.5

2.8

1.1

For normal use, REX3 = 2.7k

REX4 = 1.5k

REX3 [k

]

REX4 [k

]

taqf

taqr

tdr

tdf

A/D clock width Tpwh variation [ns]

CXA1843Q

S/H + A/D EVALUATION BOARD

The S/H + A/D Evaluation Board is a printed circuit board for evaluating the 10-bit 33MSPS high speed

sample-and-hold IC (CXA1843Q) and 2-step A/D converter (CXA1844Q). This board is designed to enable

users to make full use of the performance of CXA1843Q + CXA1844Q and evaluate them easily.

Features

· Resolution

10bit

· Maximum operating conversion speed

33MSPS

· 2 types analog input

input (OP AMP input) and DIR. IN input (AC coupled input) are available.

· Analog input dynamic range

2Vp-p

· Digital output level

TTL

· Power supply voltage

±5V

· Built-in D/A converter (For evaluation)

Generates the analog waveform.

Block Diaram

Counter

CLK/8

CLK/16

CLK/4
CLK/2

CLK

Buffer

DGND

CLK input
(CON4)

Latch

CON

TTL

ECL

10bit D/A

CLK/N

AGND

FULSCAL ADJ

D/A OUT
(CON3)

(5V)

GND V

(+5V)

MCLK

OFFSET ADJ

VR1

AGND

Analog input
VIN (CON1)

AGND

VIN

Analog input
DIR.IN (CON2)

OP
AMP

AGND

2.5V

REX2

REX3

REX4

1.6k

2.7k

1.5k

A/D OUT

A/D CLK

S/H OUT

2.0V

VREFBS

SW1

Latch

ENABLE

MINV

LINV

DAINV

S/H + A/D Evaluation Board Block Diagram

VR2

CLK/N

VRBS

VRB

VIN L VIN H

10bit A/D

REF IN REFB

S/H

CXA1843Q

Connection and Setting for S/H + A/D Evaluation Board

1. Power supply voltage (CON6)

Item

Min.

Typ.

Max.

Unit

Vcc

+4.75

+5.0

+5.25

5.25

5.0

4.75

Typical current

220

400

Unit

2. Analog input (CON1, CON2) and offset adjustment (VR1)

Input] (CON1)

When the amplitude of an analog input signal supplied to the sample-and-hold is 1Vp-p and its input range is

within 1.0V to 0.9V, the board is able to amplify its amplitude by two times using the operation amplifier. The

S1 selector should be short-circuited at side A and opened at side B, and the analog input is added from

CON1. In this case, offset adjustment is required at the VR1, so that the dynamic range of the analog input

signal can be set to a value between 0V to 2V by monitoring the V

pin.

[DIR IN. Input] (CON2)

When the input supplied to the sample-and-hold is a recurring signal (sine wave, etc.) without offset, it is

added using the AC coupled input from CON2 by connecting a 10k

resistor to side A and a 0.1µF capacitor

to side B of the S1 selector. In this case, offset adjustment is required at the VR1, so that the dynamic range

of the analog input signal can be set to a value between 0V to 2V by monitoring the V

pin.

Item

Min.

Typ.

Max.

DIR. IN input (CON2)

2.0

input (CON1)

0.9

1.0

Amplitude

2.0

1.0

Unit

10k

short

0.1µF

open

S1 setting

3. Clock input (CON4)

TTL compatible

Use in the 30 to 70% CLK duty range

(CON4 is terminated to DGND at 50

on the board.)

4. Digital output (CON5)

TTL compatible

C-MOS (ACT series) output

(CON1 and CON2 are terminated to AGND at 50

on the board.)

CXA1843Q

S/H + A/D Evaluation Board Parts List

(No.)

(Product Name)

(Function)

(No.)

(Product Name)

(Function)

IC.1

CXA1843Q

Sample Hold

R1, 13, 38

FRD-25SR (0.25W)

IC.2

CXA1844Q

10bit ADC

R21, 25

FRD-25SR (0.25W)

100

IC.3

CLC505

OP-AMP

R2, 22

FRD-25SR (0.25W)

270

IC.4

CX20201A-1

DAC

R3, 4

FRD-25SR (0.25W)

470

IC.5

74ACT34

Buffer R23

FRD-25SR

(0.25W)

IC.6 74ACT163

Counter

R12

FRD-25SR

(0.25W)

4.7k

IC.7

74ACT16821

Latch

R5, 8, 15, 16, 18, 19

FRD-25SR (0.25W)

10k

IC.8, 9

MB767

ECL

TTL level translator

R24

FRD-25SR (0.25W)

51k

D1, 3

TL431CP

3-pin shunt regulator

R11

FRD-25SR (0.25W)

150k

1S1555

Diode

SN14C2F

1.5k

P1 2SA1175

PNP

transistor

R14

SN14C2F

1.6k

SW.1

DSS-105

Switch

R10

SN14C2F

2.7k

CON.1 to 4 TMA5502-10

SMA connector

R6, 7, 17, 20

Chip resistor

CON.5

FAP-2601-1201

Flat cable connector

RN1 to 3

RGLD 4X621J

620

CON.6

TJ-563

Power supply connector

C2, 9 to 17, 19, 23 to 32

Chip capacitor

0.1µF

S1.3

JX-1

Short-pin

34 to 40, 42 to 60

VR1.2

RJ-6P

volume resistor

C1, 6 to 8, 33, 41

Tantalum capacitor

1µF (Voltage proof of 35V)

C1 to 11

LS-2S

Check pin

C3 to 5, 20 to 22

33µF (Voltage proof of 35V)

C18

Ceramic capacitor

100pF

L1 to 4

SF-T5-30-03

30µF

Precautions

1. The monitoring pins are designed to be easily grounded in order to minimize distortions occurring when

monitoring waveforms on an oscilloscope. Waveform monitoring is facilitated by using the grounded tip

(part No. 013-1185-00) made by Tektronix at the end of the probe.

2. VR1 and VR2 are optimally adjusted and set before the board is shipped.

3. REX2, REX3, REX4 (R14, R10, R9) on the board use metal-oxide resistor, and T2, T3, T4 are optimally

adjusted and set within the range of 1MHz to 33MHz.

CXA1843Q

2Q7

AGND

Vref

R2 270

C1 1µ

0.1µ

AGND

R3 470

R5 10k

VR1 2K

OFFSET

ADJ

AGND

C6 1µ

C8 1µ

AGND

C15 0.1µ

R8 10k

R4 4.7k

R1 51

AGND

CON.1

VIN

AGND

C7 1µ

AGND

C14 0.1µ

IC.3

C18 100P

R11 150k

R12 47

AGND

CON.2

DIR.in

C13

0.1µ

DGND

C12 0.1µ

R10 2.7k

0.1µ

DGND

R9 1.5k

C11 0.1µ C10 0.1µ

DGND

C19 0.1µ

C23 0.1µ

CXA1843Q

C32

0.1µ

C31 0.1µ

C30 0.1µ

C29 0.1µ

C28 0.1µ

AGND

C16

0.1µ

C17 0.1µ

DGND

C24 0.1µ

R14 1.6k

DGND

AGND

C25 0.1µ

C26 0.1µ

EE1

REX3

REX4

EE2

CC3

CLK IN

REFFB

REFOUT

EE3

CC3

SHOUT

EE2

CC2

CC1

CLK OUT

GND

REX2

REFIN

CC4

CC1

HGND

VIN

EE1

CGND

100

R21

C39

DGND

AGND

R17

R20

AGND

0 .1µ

C38

0 .1µ

C44

0 .1µ

OVER

UNDER

0.1µ

C27

C33 1µ

VREFBS

AGND

C34

0.1µ

C35

0.1µ

C36

0.1µ

AGND

DGND

VREFTS

0 .1µ

C40

0 .1µ

C45

DGND

0 .1

C37

R18

10k

R15

10k

R19

10k

R16

DVCC

ENABLE

MINV

LINV

DAINV

DGND

SW1

CXA1844Q

ENABLE

CLK

MINV

LINV

DGND2

DGND1

CC1

GND1

VINL

VINH

AVF

CC2

UNDER

OVER

GND1

DGND4

VREFTS

VRFET

DGND3

VRFEB

VRFE1

VRFE2

VRFE3

VREFBS

GND1

0.1µ

C47

1µ

C41

VR2 2K

C43 0.1µ

FULL

SCALE ADJ

R23

AGND

DGND

AGND

0 .1µ

C46

C42

0.1µ

51k

R24

CON.3

D/A out

AGND

INV

DGND

AGND1

OUT

VREF

AGND2

CLKB

CLK

D10

CX20201A-1

620

R27

620

R28

620

R29

0.1µ

C49

DGND

620

R31

620

R32

620

R33

0.1µ

C50

DGND

620

R35

620

R36

620

R37

0.1µ

C51

DGND

620

R30

RN3

620

R34

100

R25

0 .1

C48

DGND

MCLK

VIN

S/H out

IC.2

IC.1

CC2

DGND2

CON.5

CLK

LSB

MSB

DGN

DGND2

CC2

0.1µ

C60

OUT1

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

OUT2

OUT3

OUT4

GND

OUT5

OUT6

OUT7

OUT8

IC.9

MB767

DGND2

C57

0.1µ

CC2

DGND2

C58

0.1µ

DVEE2

OUT1

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

OUT2

OUT3

OUT4

GND

OUT5

OUT6

OUT7

OUT8

IC.8

MB767

DGND2

C52

0.1µ

CC2

DGND2

C53

0.1µ

EE2

1OE_

IC.7

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

1Q7

GND

1Q8

1Q9

1Q10

2Q1

2Q2

2Q3

GND

2Q4

2Q5

2Q6

GND

2Q9

2Q10

2OE_

1CLK

1D1

1D2

GND

1D3

1D4

1D5

1D6

1D7

GND

1D8

1D9

1D10

2D1

2D2

2D3

GND

2D4

2D5

2D6

2D7

2D8

GND

2D9

2D10

2CLK

DGND2

0.1µ

C59

DGND2

LSB

MSB

DGND2

0.1µ

C59

DGND2

CLK

MSB

LSB

GND

74ACT34

IC.5

CC2

DGND2

0.1µ

C54

DGND2

R38

DGND2

CC2

DGND2

0.1µ

C56

1/1

1/2

1/4

1/8

1/16

CLK

CLEAR

A IN

B IN

C IN

D IN

EN P

GND

RCarry

A OUT

B OUT

C OUT

D OUT

EN T

LOAD

CLK

CON.4

DGND2

74ACT163

IC.6

CC2

620

R26

Vref

AGND

R13 51

RN2

RN1

AGND

DGND

DGND2

7µ

GND

DGND2

EE2

(5V)

EE2

33µ

7µ

(5V)

33µ

AGND

(5V)

33µ

DGND

DGND2

CC2

(+5V)

CC2

33µ

C22

7µ

(+5V)

33µ

AGND

C20

(+5V)

33µ

C21

DGND

7µ

CON.6

C10

C11

ADCLK

CLK

DGN

ACT1682

2Q8

10k

S/H + A/D Evaluation Board

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1843Q

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1843Q