--1--
E94X27-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25C)
Supply voltage
V
CC
7
V
Operating temperature Topr
20 to +75
C
Storage temperature
Tstg
65 to +150
C
Allowable power dissipation
P
D
960
mW
Operating Conditions
Supply voltage
V
CC
50.5
V
Operating temperature Topr
20 to +75
C
Description
The CXA1875AP/AM is developed as a 8-bit 5 ch
D/A converter compatible with I
2
C bus.
Features
Serial control through I
2
C bus
4 built-in general purpose I/O ports (Digital I/O)
I/O can be specified to respective ports
independently
Selection of 8 slave addresses possible through
address select pins (3 pins)
Applications
I
2
C bus can control ICs that do not correspond to
I
2
C bus by connecting the DC control pins of them.
Structure
Bipolar silicon monolithic IC
8-bit D/A Converter Compatible with I
2
C Bus
CXA1875AP/AM
16 pin DIP (Plastic)
16 pin SOP (Plastic)
--2--
CXA1875AP/AM
Pin Configuration (Top View)
Block Diagram
16
15
14
13
12
9
10
11
3
4
5
6
7
8
2
1
SW1
SW0
DAC4
DAC3
DAC2
DAC1
DAC0
GND
V
CC
SCL
SDA
SAD2
SAD1
SAD0
SW3
SW2
I
2
C bus
Slave address select pin
SW I/O
SW I/O
DAC output
SAD2 SAD1 SAD0
LATCH
DAC
AMP
DAC4
LATCH
DAC
AMP
DAC3
LATCH
DAC
AMP
DAC2
LATCH
DAC
AMP
DAC1
LATCH
DAC
AMP
DAC0
V
CC
Power
on
Reset
Level
Conv-
ersion
I
2
C BUS
SDA
SCL
Level
Conversion
LATCH
Level
Conversion
SW0-3
Open collector
I
2
C Decoder
V
CC
REG
GND
--3--
CXA1875AP/AM
Pin Description
Electrical Characteristics (Ta=25 C, V
CC
=5 V)
D/A Converter Block
No.
Item
Symbol
Test
Test contents
Min. Typ. Max. Unit
circuit
6
9
12
mA
1
Circuit current
I
CC
1
DAC 0 to 4=127
1
0
+1
LSB
0.1
0.4
0.7
V
4.3
4.6
4.9
V
1
+1
mA
0
3
6
2
3
4
5
6
Differential
linearity
Minimum output
voltage
Maximum
output voltage
Output current
Output
impedance
DLE
Vmin
Vmax
Iout
Z
0
1
1
1
2
2
V(DAC0 to 4=n+1)V(DAC0 to 4=N)
1281
V(DAC0 to 4=191)V(DAC0 to 4=63)
n=0 to 127
DAC 0 to 4=0
DAC 0 to 4=255
Current that can be flowed from Pins 3
to 7
DAC 0 to 4=127,
V(1 mA) V(1 mA)
2 mA
No.
Symbol
Equivalent circuit
Description
I/O pin for general purpose I/O port
V
IL
max: 1.5 V
V
IH
min: 3 V
V
OL
max: 0.4 V
SDA I/O pin for I
2
C bus
D/A converter output pin
GND pin
Slave address input pin
Input at positive logic
V
IL
max: 1.5 V
V
IH
min: 3 V
Power supply pin
V
CC
150
4.5k
V
CC
56
V
CC
20k
20k
22k
V
CC
150
4.5k
V
CC
1
2
9
10
14
15
3
4
5
6
7
8
11
12
13
16
SW1
SW0
SW2
SW3
SDA
SCL
DAC4
DAC3
DAC2
DAC1
DAC0
GND
SAD0
SAD1
SAD2
V
CC
--4--
CXA1875AP/AM
SW, SAD Pins
No.
Item
Symbol
Min. Typ. Max. Unit
3.0
--
5.0
V
0
--
1.5
V
--
--
10
A
--
--
10
A
0
--
0.4
V
3
--
--
mA
--
--
10
pF
0
--
100
kHz
4.7
--
--
s
4.0
--
--
s
4.7
--
--
s
4.0
--
--
s
4.7
--
--
s
5
--
--
s
250
--
--
ns
--
--
1
s
--
--
300
ns
4.7
--
--
s
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
High level input voltage
Low level input voltage
High level input current
Low level input current
Low level output voltage
At 3 mA flow to SDA (Pin 14)
Maximum flowing current
Input capacitance
Maximum clock frequency
Data change minimum waiting time
Data transfer start minimum waiting time
Low level clock pulse width
High level clock pulse width
Minimum start preparation waiting time
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum stop preparation waiting time
V
IH
V
IL
I
IH
I
IL
V
OL
I
OL
C
I
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
I
2
C bus load conditions: Pull up resistance 4 k
(Connected to +5 V)
Load capacitance 200 pF (Connected to GND)
No.
Item
Symbol
Text
Test contents
Min. Typ. Max. Unit
circuit
--
--
1.5
V
3.0
--
--
V
10
0
+10
A
10
0
+10
A
0
0.2
0.4
V
7
8
9
10
11
Low level input
voltage
High level input
voltage
Low level input
current
High level input
current
Low level input
voltage
V
IL
V
IH
I
IL
I
IH
V
OL
3
3
3
3
4
ST 0 to 3 an input voltage that turns to `0'
ST 0 to 3 an input voltage that turns to `1'
Input current when 0.4 V is applied
Input current when 4.5 V is applied
SW 0 to 3=1, Output voltage when 1 mA
flows in
I
2
C Bus Block Items (SDA, SCL)
--5--
CXA1875AP/AM
I
2
C Bus Control Signal
Electrical Characteristics Test Circuit
Test circuit 1
Test circuit 2
Test circuit 3
Test circuit 4
t
BUF
SCL
SDA
P
S
t
HD:STA
t
LOW
t
R
t
HD:DAT
t
F
t
HIGH
t
SU:DAT
Sr
t
HD:STA
t
SU:STA
P
t
SU:STO
I
2
C BUS
A
0.022
+5V
10
5V
100p
100p
100p
100p
100p
V
3
4
5
6
7
8
2
1
16
15
14
13
12
9
10
11
I
2
C BUS
A
0.022
10
100p
3
4
5
6
7
8
2
1
100p
100p
100p
100p
V
+5V
16
15
14
13
12
9
10
11
1mA
I
2
C BUS
0.022
10
+5V
V
4
16
15
14
13
12
9
10
11
A
3
4
5
6
7
8
2
1
1.5 V (No. 7)
3.0 V (No. 8)
0.4 V (No. 9)
4.5 V (No. 10)
V
4
=
I
2
C BUS
0.022
10
+5V
1mA
3
4
5
6
7
8
2
1
15
14
13
12
9
10
11
16
V
--6--
CXA1875AP/AM
Definition of I
2
C Register
<Slave address>
<Register table>
With the IC reset all registers are reset to 0
: Not defined
: Don't care
Sub address is auto incremented
It can be used as a 6-bit D/A converter by setting the lower two bits of DAC 0-4 registors to 0, but take care
that the max. voltage of DA output will lower about 100 mV compared with the use of 8 bits.
Control Register
Status Register
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
REF
SW3
SW2
SW1
SW0
DAC0 (8)
DAC1 (8)
DAC2 (8)
DAC3 (8)
DAC4 (8)
Sub address
000
001
010
011
100
101
MSB
LSB
0
1
0
0
SAD2
SAD1
SAD0
R/W
R/W
0: SLAVE RECEIVER
1: SLAVE TRANSMITTER
SAD 0 to 2: 11 to 13 pin
0: "LOW"
1: "HIGH"
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
PONRES
0
0
0
ST3
ST2
ST1
ST0
--7--
CXA1875AP/AM
<Registers>
In brackets ( ) number of bits
REF
(1):
Switches D/A converter reference voltage
0:Standardizes the inner regulator
1:Standardizes voltage resistance divided from V
CC
SW0 to 3 (1):
Selects ON/OFF of Pins 1, 2, 9 and 10
(Each pin is the open collector output of NPN transistor)
0:OFF
1:ON
DAC0 to 4 (8):
Digital data input register of D/A converter
0:Output voltage turns to minimum
255:Output voltage turns to maximum
PONRES (1):
Detects POWER ON RESET
0:Master passes from the bus and is reset to 0 after having read this status
1:Set to 1 when power supply is turned on or when there has been a power dip
ST0 to 3
(1):
Detects and registers the voltage condition of Pins 1, 2, 9 and 10
0:1.5 V and below
1:3.0 V and above
Note) SW0 to 3 effective during 0
I
2
C Bus Signal
There are 2 signals in I
2
C bus. SDA (Serial DAta) and SCL (Serial Clock).
SDA is double-way.
As SDA is double-way it has 3 state outputs, H, L and HIZ.
I
2
C transfer begins with Start Condition and ends with Stop Condition.
L
H
HIZ
L
SDA
Start Condition S
SCL
Stop Condition P
--8--
CXA1875AP/AM
I
2
C data write (Write from I
2
C controller to IC)
I
2
C data read (Read from IC to I
2
C controller)
Read timing
Data read is performed with SCL rise.
SDA
SCL
1
2
3
4
5
6
7
8
9
1
8
9
MSB
HIZ
MSB
LSB
HIZ
AT L during write
Address
ACK
Sub Address
ACK
ACK
DATA (n)
DATA (n+1)
ACK
8
9
1
8
9
DATA (n+2)
8
9
1
8
9
ACK
DATA
DATA
ACK
P
MSB
HIZ
LSB
HIZ
1
HIZ
HIZ
S
SDA
SCL
1
6
7
8
9
1
8
9
HIZ
At H during read
Address
ACK
DATA
ACK
S
7
P
IC output SDA
SCL
1
2
3
4
5
6
7
8
9
9
MSB
LSB
DATA
ACK
ACK
Read timing
The number of data that can be
transferred at a time is confined
to units of 8-bit that can be set
as required.
Sub Address is incremented
automatically.
--9--
CXA1875AP/AM
Application Circuit
I
2
C BUS
0.022
10
10k
2SC2785
+5V
D/A converter output
General purpose
input port
10k
10k
14
15
13
16
9
10
11
12
General purpose
output port
2
3
4
5
6
7
8
1
10k
10k
10k
2SC2785
10k
CXA1875AP/AM
Slave address for 4 CH and 4 DH
10k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
19.2 0.1
+ 0.4
9
1
8
2.54
0.5 0.1
1.2 0.15
3
.
0
M
I
N
0
.
5
M
I
N
3
.
7
0
.
1
+
0
.
4
6
.
4
0
.
1
+
0
.
3
7
.
6
2
0
.
2
5
0
.
0
5
+
0
.
1
0 to 15
16
16PIN DIP (PLASTIC)
1.0 g
SONY CODE
EIAJ CODE
JEDEC CODE
DIP-16P-01
DIP016-P-0300
Similar to MO-001-AE
1.All mat surface type.
Two kinds of package surface:
2.All mirror surface type.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-16P-L01
SOP016-P-0300
COPPER ALLOY
SOLDER PLATING
EPOXY RESIN
16PIN SOP (PLASTIC)
9.9 0.1
+ 0.4
16
9
1
8
1.27
0.45 0.1
5
.
3
0
.
1
+
0
.
3
7
.
9
0
.
4
6
.
9
1.85 0.15
+ 0.4
0
.
5
0
.
2
0.2 0.05
+ 0.1
0.1 0.05
+ 0.2
0.2g
0.15
M
0.24
Package Outline Unit : mm
CXA1875AP
CXA1875AM
CXA1875AP/AM
--10--
Purchase of Sony's I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components in an I
2
C
system, provided that the system conforms to the I
2
C Standard Specifications as defined by Philips.
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