Description
The CXA1992AR is a bipolar IC developed for CD
player RF signal processing and servo control.
Features
Automatic focus bias adjustment circuit
Automatic tracking balance and gain adjustment
circuits
RF level control circuit
Interruption countermeasure circuit
Sled overrun prevention circuit
Anti-shock circuit
Defect detection and prevention circuits
RF 1-V amplifier, RF amplifier
APC circuit
Focus and tracking error amplifier
Focus, tracking and sled servo control circuits
Focus OK circuit
Mirror detection circuit
Single power supply and dual power supplies
Applications
CD players
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
CC
12
V
Operating temperature
Topr
20 to +75 C
Storage temperature
Tstg
65 to +150 C
Allowable power dissipation
P
D
600
mW
Recommended Operating Conditions
Operating supply voltage V
CC
V
EE
3.0 to 5.5
V
1
CXA1992AR
E96X16-PS
RF Signal Processing Servo Amplifier
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
52 pin LQFP (Plastic)
2
CXA1992AR
Block Diagram
PS1-4
TM1-7
TG1-2
FS1-4
IFB1-6
BAL1-4
TOG1-4
DFCTO
I
F
B
1
V
EE
FE AMP
FO. BIAS
WINDOW COMP.
T
G
F
L
TRK. GAIN
WINDOW COMP.
T
O
G
1
T
O
G
2
T
O
G
3
T
O
G
4
E-F BALANCE
WINDOW COMP.
B
A
L
1
F IV AMP
E IV AMP
V
CC
V
EE
V
CC
TG1
TM1
DFCT
TRACKING
PHASE COMPENSATION
IIL DATA REGISTER
INPUT SHIFT REGISTER
ADDRESS DECODER
SENS SELECTOR
OUTPUT DECODER
FZC
VC
TDFCT
TZC
V
EE
ATSC
LPFI
TEO
TEI
V
EE
FE_BIAS
E
F
EI
F
E
O
F
E
I
F
D
F
C
T
F
L
B
F
E
_
O
F
E
_
M
T
A
_
M
T
G
2
T
G
U
S
R
C
H
F
G
D
F
S
E
T
T
A
_
O
L
D
R
F
T
C
R
F
_
M
R
F
_
O
R
F
_
I
C
B
C
C
1
F
O
K
C
C
2
C
P
P
D
2
P
D
1
P
D
SL_P
SL_O
ISET
V
CC
CLK
DATA
XRST
SL_M
LOCK
C. OUT
XLT
SENS1
SENS2
PD2 IV
AMP
PD1 IV
AMP
V
CC
V
CC
V
EE
APC
V
EE
LASER POWER CONTROL
RF SUMMING AMP
V
CC
V
EE
LEVEL S
FZC
TZC
ATSC
BALL
BALH
TGL
TGH
FOL
FOH
L
D
O
N
L
P
C
L
L
P
C
T
G
F
L
V
EE
V
CC
TTL
M
I
R
R
D
F
C
T
1
V
EE
V
CC
DFCT
C
C
1
ISET
V
CC
V
EE
V
CC
TM5
TM6
V
EE
V
CC
TM3
TM4
FSET
TG2
FOCUS
PHASE COMPENSATION
TM7
V
EE
V
CC
FS1
Charge
up
FS2
DFCT
FS4
IIL
TTL
IIL
TTL
IIL
49
50
51
52
40
41
42
43
44
45
46
47
48
2
3
4
5
6
7
8
9
10
11
12
1
13
27
28
29
30
39
38
37
36
35
34
31
32
33
14
15
16
17
18
19
20
21
22
23
24
25
26
TM2
FZC COMP.
TZC COMP.
ATSC
WINDOW
COMP.
MIRR
FOK
B
A
L
2
B
A
L
3
B
A
L
4
I
F
B
6
I
F
B
5
I
F
B
4
I
F
B
3
I
F
B
2
3
CXA1992AR
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
1
FEO
O
Focus error amplifier output.
Connected internally to the window
comparator input for bias
adjustment.
2
FEI
I
3
FDFCT
I
Focus error input.
Capacitor connection pin for defect
time constant.
4
FGD
I
Ground this pin through a capacitor
for cutting the focus servo high-
frequency gain.
5
FLB
I
External time constant setting pin
for boosting the focus servo low-
frequency.
6
FE_O
O
13
TA_O
O
16
SL_O
O
Focus drive output.
Tracking drive output.
Sled drive output.
7
FE_M
I
Focus amplifier inverted input.
147
50k
90k
7
2
250
6
13
16
1
147
25p
174k
10
10
300
147
100k
147
2
3
3
147
130k
4
68k
4
40k
470k
330k
5
4
CXA1992AR
8
SRCH
I
External time constant setting pin for
generating focus search waveform.
9
TGU
I
External time constant setting pin
for switching tracking high-
frequency gain.
10
TG2
I
External time constant setting pin for
switching tracking high-frequency
gain.
11
FSET
I
Peak frequency setting pin for focus
and tracking phase compensation
amplifier.
12
TA_M
I
Tracking amplifier inverted input.
14
SL_P
I
15
SL_M
I
Sled amplifier non-inverted input.
Sled amplifier inverted input.
14
147
2
12
147
100k
11
147k
11
15k
15k
147
50k
8
11
20k
20k
9
110k
82k
147
10
470k
147
22
15
Pin
No.
Symbol
I/O
Equivalent circuit
Description
5
CXA1992AR
17
ISET
I
Connect an external capacitance to
set the current which determines
the Focus search, Track jump, and
Sled kick heights.
19
LOCK
I
20
CLK
I
22
DATA
I
The sled overrun prevention circuit
operates when this pin is Low.
(no pull-up resistance)
18
V
CC
I
Positive power supply.
Serial data input from CPU.
(no pull-up resistance)
Serial data transfer clock input from
CPU. (no pull-up resistance)
21
XLT
I
23
XRST
I
Latch input from CPU.
(no pull-up resistance)
Reset input; resets at Low.
(no pull-up resistance)
147
17
50
147
19
20
22
20
1k
23
147
20
21
2k
5p
24
C. OUT
O
25
SENS1
O
26
SENS2
O
Track number count signal output.
Outputs FZC, DFCT1, TZC, BALH,
TGH, FOH, ATSC, and others
according to the command from CPU.
Outputs DFCT2, MIRR, BALL, TGL,
FOL, and others according to the
command from the CPU.
100k
147
20k
24
25
26
18
V
CC
27
FOK
O
Focus OK comparator output.
147
20k
100k
40k
27
Pin
No.
Symbol
I/O
Equivalent circuit
Description
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