Description
The CXA1992BR is a bipolar IC developed for CD
player RF signal processing and servo control.
Features
Automatic focus bias adjustment circuit
Automatic tracking balance and gain adjustment
circuits
RF level control circuit
Interruption countermeasure circuit
Sled overrun prevention circuit
Anti-shock circuit
Defect detection and prevention circuits
RF I-V amplifier, RF amplifier
APC circuit
Focus and tracking error amplifier
Focus, tracking and sled servo control circuits
Focus OK circuit
Mirror detection circuit
Single power supply and dual power supplies
Applications
CD players
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
CC
12
V
Operating temperature
Topr
20 to +75 C
Storage temperature
Tstg
65 to +150 C
Allowable power dissipation
P
D
600
mW
Recommended Operating Conditions
Operating supply voltage V
CC
V
EE
4.5 to 5.5
V
1
CXA1992BR
E97216A84
RF Signal Processing Servo Amplifier
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
52 pin LQFP (Plastic)
2
CXA1992BR
Block Diagram
PS1-4
TM1-7
TG1-2
FS1-4
IFB1-6
BAL1-4
TOG1-4
DFCTO
I
F
B
1
V
EE
FE AMP
FO. BIAS
WINDOW COMP.
T
G
F
L
TRK. GAIN
WINDOW COMP.
T
O
G
1
T
O
G
2
T
O
G
3
T
O
G
4
E-F BALANCE
WINDOW COMP.
B
A
L
1
F IV AMP
E IV AMP
V
CC
V
EE
V
CC
TG1
TM1
DFCT
TRACKING
PHASE COMPENSATION
IIL DATA REGISTER
INPUT SHIFT REGISTER
ADDRESS DECODER
SENS SELECTOR
OUTPUT DECODER
FZC
VC
TDFCT
TZC
V
EE
ATSC
LPFI
TEO
TEI
V
EE
FE_BIAS
E
F
EI
F
E
O
F
E
I
F
D
F
C
T
F
L
B
F
E
_
O
F
E
_
M
T
A
_
M
T
G
2
T
G
U
S
R
C
H
F
G
D
F
S
E
T
T
A
_
O
L
D
R
F
T
C
R
F
_
M
R
F
_
O
R
F
_
I
C
B
C
C
1
F
O
K
C
C
2
C
P
P
D
2
P
D
1
P
D
SL_P
SL_O
ISET
V
CC
CLK
DATA
XRST
SL_M
LOCK
C. OUT
XLT
SENS1
SENS2
PD2 IV
AMP
PD1 IV
AMP
V
CC
V
CC
V
EE
APC
V
EE
LASER POWER CONTROL
RF SUMMING AMP
V
CC
V
EE
LEVEL S
FZC
TZC
ATSC
BALL
BALH
TGL
TGH
FOL
FOH
L
D
O
N
L
P
C
L
L
P
C
T
G
F
L
V
EE
V
CC
TTL
M
I
R
R
D
F
C
T
1
V
EE
V
CC
DFCT
C
C
1
ISET
V
CC
V
EE
V
CC
TM5
TM6
V
EE
V
CC
TM3
TM4
FSET
TG2
FOCUS
PHASE COMPENSATION
TM7
V
EE
V
CC
FS1
Charge
up
FS2
DFCT
FS4
IIL
TTL
IIL
TTL
IIL
49
50
51
52
40
41
42
43
44
45
46
47
48
2
3
4
5
6
7
8
9
10
11
12
1
13
27
28
29
30
39
38
37
36
35
34
31
32
33
14
15
16
17
18
19
20
21
22
23
24
25
26
TM2
FZC COMP.
TZC COMP.
ATSC
WINDOW
COMP.
MIRR
FOK
B
A
L
2
B
A
L
3
B
A
L
4
I
F
B
6
I
F
B
5
I
F
B
4
I
F
B
3
I
F
B
2
3
CXA1992BR
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
1
FEO
O
Focus error amplifier output.
Connected internally to the window
comparator input for bias
adjustment.
2
FEI
I
3
FDFCT
I
Focus error input.
Capacitor connection pin for defect
time constant.
4
FGD
I
Ground this pin through a capacitor
for cutting the focus servo high-
frequency gain.
5
FLB
I
External time constant setting pin
for boosting the focus servo low-
frequency.
6
FE_O
O
13
TA_O
O
16
SL_O
O
Focus drive output.
Tracking drive output.
Sled drive output.
7
FE_M
I
Focus amplifier inverted input.
147
50k
90k
7
2
250
6
13
16
1
147
25p
174k
10
10
300
147
100k
147
2
3
3
147
130k
4
68k
4
40k
470k
330k
5
4
CXA1992BR
8
SRCH
I
External time constant setting pin for
generating focus search waveform.
9
TGU
I
External time constant setting pin
for switching tracking high-
frequency gain.
10
TG2
I
External time constant setting pin for
switching tracking high-frequency
gain.
11
FSET
I
Peak frequency setting pin for focus
and tracking phase compensation
amplifier.
12
TA_M
I
Tracking amplifier inverted input.
14
SL_P
I
15
SL_M
I
Sled amplifier non-inverted input.
Sled amplifier inverted input.
14
147
2
12
147
100k
11
147k
11
15k
15k
147
50k
8
11
20k
20k
9
110k
82k
147
10
470k
147
22
15
Pin
No.
Symbol
I/O
Equivalent circuit
Description
5
CXA1992BR
17
ISET
I
Connect an external capacitance to
set the current which determines
the Focus search, Track jump, and
Sled kick heights.
19
LOCK
I
20
CLK
I
22
DATA
I
The sled overrun prevention circuit
operates when this pin is Low.
(no pull-up resistance)
18
V
CC
I
Positive power supply.
Serial data input from CPU.
(no pull-up resistance)
Serial data transfer clock input from
CPU. (no pull-up resistance)
21
XLT
I
23
XRST
I
Latch input from CPU.
(no pull-up resistance)
Reset input; resets at Low.
(no pull-up resistance)
147
17
50
147
19
20
22
20
1k
23
147
20
21
2k
5p
24
C. OUT
O
25
SENS1
O
26
SENS2
O
Track number count signal output.
Outputs FZC, DFCT1, TZC, BALH,
TGH, FOH, ATSC, and others
according to the command from CPU.
Outputs DFCT2, MIRR, BALL, TGL,
FOL, and others according to the
command from the CPU.
100k
147
20k
24
25
26
18
V
CC
27
FOK
O
Focus OK comparator output.
147
20k
100k
40k
27
Pin
No.
Symbol
I/O
Equivalent circuit
Description
6
CXA1992BR
28
CC2
I
29
CC1
O
30
CB
I
Input for the defect bottom hold
output with capacitance coupled.
Defect bottom hold output.
Connected internally to the
interruption comparator input.
Connection pin for defect bottom
hold capacitor.
147
147
147
28
29
30
43k
11k
120k
31
CP
I
Connection pin for MIRR hold
capacitor.
MIRR comparator non-inverted
input.
32
RF_I
I
33
RF_O
O
34
RF_M
I
1.5k
31
100k
147
147
147
34
32
33
10k
10k
Input for the RF summing amplifier
output with capacitance coupled.
RF sunning amplifier output. Eye-
pattern check point.
RF summing amplifier inverted
input.
The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.
35
RFTC
I
External time constant setting pin
during RF level control.
147
50
10
50
35
Pin
No.
Symbol
I/O
Equivalent circuit
Description
7
CXA1992BR
36
LD
O
APC amplifier output.
37
PD
I
APC amplifier input.
38
39
PD1
PD2
I
I
RF I-V amplifier inverted input.
Connect these pins to the photo
diode A + C and B + D pins.
147
10k
11.6k
39
38
100
2k
8k
147
37
8
20
55k
10k
1k
10k
36
40
FE_BIAS
I
Bias adjustment of focus error
amplifier.
Leave this pin open for automatic
adjustment.
41
42
F
E
I
I
F I-V and E I-V amplifier inverted
input.
Connect these pins to photo diodes
F and E.
147
4k
6
40
147
260k
12p
500
41
42
10
Pin
No.
Symbol
I/O
Equivalent circuit
Description
8
CXA1992BR
43
EI
--
I-V amplifier E gain adjustment.
(When not using automatic balance
adjustment)
45
TEO
O
Tracking error amplifier output.
E-F signal is output.
46
LPFI
I
Comparator input for balance
adjustment.
(Input from TEO through LPF)
147
7
46
147
16k 7.5k
1.5k
7.5k
10k
150k
150k
3.3k
45
260k
6.8k
75k
110k 56k
13k
43
147
27k
44
V
EE
44
V
EE
--
Negative power supply.
47
TEI
I
50
TDFCT
I
Tracking error input.
Capacitor connection pin for defect
time constant.
147
100k
147
3
47
50
Pin
No.
Symbol
I/O
Equivalent circuit
Description
9
CXA1992BR
48
ATSC
I
49
TZC
I
51
VC
O
Window comparator input for ATSC
detection.
Tracking zero-cross comparator
input.
(V
CC
+ V
EE
)/2 direct voltage output.
147
75k
49
10
147
1k
100k
100k
1k
48
10
10
VC
50
120
120
51
52
FZC
I
Focus zero-cross comparator input.
147
10
52
300k
6k
54k
Pin
No.
Symbol
I/O
Equivalent circuit
Description
10
CXA1992BR
TEST
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
Current
consumption 1
Current
consumption 2
Center amplifier
output offset
Offset
Voltage gain
Max. output
amplitude - High
Max. output
amplitude - Low
Offset
Voltage gain 1
(PHD1)
Voltage gain 2
(PHD2)
Voltage gain
difference
Max. output
voltage High
Max. output
voltage Low
BIAS0
BIAS1
BIAS2
BIAS3
BIAS4
BIAS5
BIAS6
51
51
51, 51D
33S, 38, 39
33D, 38
33D, 39
1D
1S, 38
1S, 39
1S
1D, 39
1D, 38
1D
1D
1D
1D
1D
1D
1D
RST
RST
RST
RST
RST
RST
RST
39F
39F
39F
39F
39F
39F
3BF
3BE
3BD
3BB
3B7
3AF
39F
18
44
--
38
39
38
39
38
39
38
39
39
38
18
44
51
33
33
33
33
1
1
1
1
1
1
1
1
1
1
1
1
1kHz I/O ratio
V2 = 0.25VDC
V2 = 0.15VDC
1FB6: ON
1kHz I/O ratio
1kHz I/O ratio
V2 = 300mVDC
V2 = 300mVDC
IFB1, 2, 3, 4, 5, 6:
OFF
IFB1: ON, BIAS0:
reference
IFB2: ON, BIAS0: reference
Output gain difference with T15
IFB3: ON, BIAS0: reference
Output gain difference with V17
IFB4: ON, BIAS0: reference
Output gain difference with V18
IFB5: ON, BIAS0: reference
Output gain difference with V19
IFB6: ON, BIAS0: reference
Output gain difference with V20
17.2
33.1
100
20
25.1
1.2
--
120
17.4
17.4
3
1
--
560
31.3
5
5
5
5
5
23.3
23.3
0
50
28.1
1.3
1.1
0
20.4
20.4
0
1.3
1.3
801
25
6
6
6
6
6
33.1
17.2
100
120
31.1
--
1.0
120
23.4
23.4
3
--
1
1042
18.8
7
7
7
7
7
mA
mA
mV
mV
dB
V
V
mV
dB
dB
dB
V
V
mV
mV
dB
dB
dB
dB
dB
Item
SW conditions
(ON switches)
SD
Input
pin
Measurement
conditions
Min.
Typ.
Max.
Unit
Electrical Characteristics
(V
CC
= 1.5V, V
EE
= 1.5V, Topr = 25C)
RF amplifier
FE amplifier
Measure-
ment pin
VC
11
CXA1992BR
FOH threshold
FOL threshold
Offset
GAIN UP (F)
GAIN UP (E)
Voltage gain
F0
Voltage gain
F1
Voltage gain
F2
Voltage gain
F3
Voltage gain
F4
Voltage gain
E0
Voltage gain
E1
Voltage gain
E2
Voltage gain
E3
Voltage gain
E4
Max. output
voltage High
Max. output
voltage Low
Output voltage
1
Output voltage
2
Output voltage
3
Output voltage
4
LD OFF
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40
T41
T42
1D, 25D, 40
1D, 26D, 40
45D
41, 45S
42, 45S
41, 45S
41, 45S
41, 45S
41, 45S
41, 45S
42, 45S
42, 45S
42, 45S
42, 45S
42, 45S
41, 45D
42, 45D
36D, 37
36D, 37
36D, 37
36, 36D
36, 36D, 37
40
40
41
42
41
42
41
41
41
41
41
42
42
42
42
42
41
42
37
37
37
37
37
39F
39F
34F
308
36F
308
36F
308
34F
34E
30F
34D
34B
347
34F
30F
00
30E
30D
30B
307
34F
308
34F
308
3C4
3C4
3C4
3C4
3C0
1
1
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
36
36
36
36
36
I
FB6: ON
Pin 1 voltage when SENS1
(Pin 25) goes from High to Low
IFB6: ON
Pin 1 voltage when SENS2
(Pin 26) goes from High to Low
TOG: OFF,
BAL1, 2, 3: ON
V1 = 2 kHz, I/O ratio
TOG: OFF, BAL1, 2, 3: ON
V1 = 2 kHz, I/O ratio
TOG: OFF, BAL1, 2, 3: ON
V1 = 2kHz, TOG: OFF
I/O ratio
V1 = 2kHz, TOG1: ON
Reference to F0
V1 = 2kHz, TOG2: ON
Reference to F0
V1 = 2kHz, TOG3: ON
Reference to F0
V1 = 2kHz, TOG4: ON
Reference to F0
V1 = 2kHz, BAL: OFF
I/O ratio
V1 = 2kHz, BAL1: ON
Reference to E0
V1 = 2kHz, BAL2: ON
Reference to E0
V1 = 2kHz, BAL3: ON
Reference to E0
V1 = 2kHz, BAL4: ON
Reference to E0
V1 = 1VDC, TOG: OFF,
BAL1, 2, 3: ON
V1 = 1VDC, TOG: OFF,
BAL1, 2, 3: ON
I37 = 364A
I37 = 439A
I37 = 515A
0.8mA sink
I37 = 515A,
LD: OFF
5
35
25
8.6
8.6
2.5
2.6
4.4
7.7
12.2
0.33
0.17
0.6
1.46
3.03
0.5
--
900
900
100
200
1.1
20
20
0
11.6
11.6
5.5
2.1
3.9
7.2
11.7
2.67
0.47
0.9
1.76
3.33
0.7
0.8
694
538
367
130
1.3
35
5
25
14.6
14.6
8.5
1.6
3.4
6.7
11.2
5.67
0.77
1.2
2.06
3.63
--
0.5
500
100
800
500
--
mV
mV
mV
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
V
mV
mV
mV
mV
V
FE amplifier
TE amplifier
APC
TEST
Item
SW conditions
(ON switches)
SD
Input
pin
Measure-
ment pin
Measurement
conditions
Min.
Typ.
Max.
Unit
12
CXA1992BR
T43
T44
T45
T46
T47
T48
T49
T50
T51
T52
T53
T54
T55
T56
T57
T58
T59
T60
T61
T62
T63
T64
50% limit
17% limit
50% limit
17% limit
Direct voltage
gain
FCS total gain
Feed through
1
FZC threshold
Max. output
voltage High
Max. output
voltage Low
Search
voltage ()
Search
voltage (+)
Direct voltage
gain
TRK total gain
Feed through
1
Max. output
voltage High
Max. output
voltage Low
Jump output
voltage ()
Jump output
voltage (+)
ATSC
threshold ()
ATSC
threshold (+)
TZC threshold
32, 36D, 37
32, 36D, 37
36D, 37, 38,
39
36D, 37, 38,
39
2, 6D
2, 6S
26D, 52
2, 6D, 6S
2, 6D, 6S
6D
6D
13D, 47
13S, 47
13D, 47
13D, 47
13D
13D
10, 10D, 48
10, 10D, 48
25D, 49,
49B
3C7
3C5
3C7
3C5
08
--
00
08
00
08
08
02
03
25
--
20
25
20
25
20
25
2C
28
10
10
20
37
32
37
32
37
38
39
37
38
39
2
--
2
52
2
2
--
--
47
--
47
47
47
48
48
49
36
36
36
36
6
--
6
52
6
6
6
6
13
--
13
13
13
13
13
48
48
49
I37 = 273A
Output difference with LPC ON/OFF
I37 = 394A
Output difference with LPC ON/OFF
I37 = 742A
Output difference with LPC ON/OFF
I37 = 621A
Output difference with LPC ON/OFF
T9 + T47
Output gain difference between
SD = 00 and SD = 08.
Pin 52 voltage when SENS1
(Pin 25) goes from Low to High
V1 = 200mVDC
V1 = 200mVDC
T26 + T55
Output gain difference between
SD = 20 and SD = 25.
V1 = 0.5VDC
V1 = 0.5VDC
Input voltage when TG2
(Pin 10) goes from Vcc/2 to Vcc
Input voltage when TG2 (Pin 10)
goes from Vcc/2 to Vcc
Pin 49 voltage when
SENS1 (Pin 25) is 0V
300
230
1510
900
17.8
39.4
--
123
1
--
640
360
12.2
18.1
--
1
--
640
360
25
7
20
1020
610
970
580
20.8
41.6
--
150
1.3
1.3
540
540
14.6
20.1
--
1.3
1.3
540
540
15
15
0
1510
1050
300
80
23.8
43.4
30
177
--
1
360
640
17.6
22.1
39
--
1
360
640
7
25
20
mV
mV
mV
mV
dB
dB
dB
mV
V
V
mV
mV
dB
dB
dB
V
V
mV
mV
mV
mV
mV
RF level controll
Focus servo
Tracking servo
TEST
Item
SW conditions
(ON switches)
SD
Input
pin
Measurement
conditions
Min.
Typ.
Max.
Unit
Measure-
ment pin
13
CXA1992BR
T65
T66
T67
T68
T69
T70
T71
T72
T73
T74
T75
T76
T77
T78
T79
T80
T81
T82
BAL COMP
threshold High
BAL COMP
threshold Low
GAIN COMP
threshold High
GAIN COMP
threshold Low
FOK
threshold
Voltage gain
Feed through
Max. output
voltage High
Max. output
voltage Low
Kick voltage 1
Kick voltage 2
Max. operating
frequency 1
Min. input
operating voltage 1
Max. input
operating voltage 1
Min. operating
frequency 1
Max. operating
frequency 1
Min. input
operating voltage 1
Max. input
operating voltage 1
25D, 46,
46B
26D, 46,
46B
25D, 41,
45D
26D, 41,
45D
27D, 32
14, 14B, 15,
16S
14, 14B,
16S
14, 14B,
16D
14, 14B,
16D
16D
16D
26S, 32
26S, 32
26S, 32
25S, 38, 39
25S, 38, 39
25S, 38, 39
25S, 38, 39
300
300
308
34F
308
34F
--
25
20
25
25
25
20
20
20
20
20
10
10
10
10
46
46
41
41
32
14
14
14
14
--
--
32
32
32
38
39
38
39
38
39
38
39
46
46
45
45
32
16
16
16
16
16
16
26
26
26
25
25
25
25
Pin 46 voltage when SENS1
(Pin 25) goes from High to Low
Pin 46 voltage when SENS2
(Pin 26) goes from High to Low
Pin 45 voltage when SENS1
(Pin 25) goes from High to Low
Pin 45 voltage when SENS2
(Pin 26) goes from Low to High
Pin 32 voltage when
Pin 27 is 0V
V1 = 100Hz, I/O ratio
Output gain difference between
SD = 20 and SD = 25.
V1 = 400mVDC
V1 = 400mVDC
REV
1
FWD
1
Measures at SENS2
pin.
Measures at SENS2
pin.
Measures at SENS2
pin.
Measures at SENS1
pin.
Measures at SENS1
pin.
Measures at SENS1
pin.
Measures at SENS1
pin.
5
35
175
130
400
50
--
1
--
750
450
30
--
1.8
--
2.5
--
1.8
20
20
200
150
367
--
--
1.3
1.3
600
600
--
--
--
--
--
--
--
35
5
225
170
330
--
34
--
1
450
750
--
0.3
--
1
--
0.5
--
mV
mV
mV
mV
mV
dB
dB
V
V
mV
mV
kHz
Vp-p
Vp-p
kHz
kHz
Vp-p
Vp-p
Tracking servo
FOK
Sled servo
MIRROR
DEFECT
TEST
Item
SW conditions
(ON switches)
SD
Input
pin
Measurement
conditions
Min.
Typ.
Max.
Unit
Measure-
ment pin
14
CXA1992BR
S
1
9
S
2
6
D
R
4
0
1
0
k
R
4
7
1
0
k
S
2
6
S
R
5
3
1
0
0
R
3
5
1
0
k
S
3
7
S
4
6
B
S
4
6
S
4
7
FE
O
FE
I
FD
FC
T
FL
B
FE
_O
FE
_M
TA
_M
TG
2
TG
U
SR
CH
FG
D
FS
ET
TA
_O
S
1
3
D
S
1
3
S
R
3
0
1
0
0
k
R
3
3
2
0
0
k
R
3
4
1
3
k
R
2
8
5
1
0
k
C
8
0
.
0
1
S
1
0
D
S
1
0
S
9
R
2
7
1
0
k
R
2
9
1
0
k
R
3
2
1
0
0
R
2
6
1
0
k
S
6
S
S
6
D
R
2
0
1
0
0
k
R
2
3
2
0
0
k
R
1
9
1
0
0
R
2
2
1
0
k
S
1
2
S
7
S
8
D
R
1
6
1
3
k
C
4
1
0
0
0
P
S
5
S
4
R
1
3
4
7
k
C
3
1
0
0
0
P
A
3
S
3
S
2
R
8
1
0
k
S
1
D
S
1
S
R
7
1
0
k
R
1
0
1
0
0
S
5
2
S
5
1
D
S
5
1
I
I
5
1
0
m
A
C
1
1
0
0
0
P
A
5
0
S
5
0
S
5
1
A
4
9
S
4
9
B
S
4
9
S
4
8
A
4
6
S
4
3
R
4
1
3
k
S
4
2
R
5
3
9
0
k
S
4
1
R
6
3
9
0
k
S
4
0
I
4
0
0
m
A
S
3
9
R
9
3
0
k
S
3
8
R
1
1
3
0
k
V
2
A
C
D
C
R
1
2
3
3
0
I
3
7
0
m
A
S
3
6
S
3
6
D
I
3
6
0
m
A
R
1
4
1
0
k
R
1
5
1
M
C
5
0
.
1
R
1
7
6
6
k
R
1
8
1
0
k
S
3
3
D
R
2
1
1
0
0
S
3
3
S
R
2
4
1
0
k
S
3
2
C
6
3
3
0
0
p
C
7
0
.
0
1
C
9
0
.
0
3
3
R
3
1
1
0
0
k
S
2
8
S
2
5
D
R
3
9
1
0
k
R
4
6
1
0
k
S
2
5
S
R
5
2
1
0
0
S
2
4
D
R
3
8
1
0
k
R
4
5
1
0
k
S
2
4
S
R
5
1
1
0
0
S
2
7
D
R
4
8
1
0
k
S
2
7
S
R
5
4
1
0
0
S
1
6
S
1
5
R
4
4
5
.
1
k
A
1
4
S
1
4
B
S
1
4
C
1
1
4
7
R
3
6
6
0
k
R
4
1
1
0
k
S
1
6
S
S
1
6
D
R
4
2
1
3
k
R
4
9
1
0
0
R
2
1
0
0
R
1
1
0
k
R
3
1
0
k
S
4
5
D
S
4
5
S
S
4
5
V
1
A
C
D
C
G
N
D
R
5
0
1
0
k
S
1
7
R
4
3
1
2
0
k
C
1
0
3
3
A
1
8
A
4
4
C
2
3
3
X
R
S
T
D
A
T
A
X
L
T
C
L
K
D
_
G
N
D
S
T
O
R
A
G
E
1
G
N
D
G
N
D
D
C
O
U
T
P
U
T
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
S
T
O
R
A
G
E
2
V
C
C
G
N
D
V
E
E
F
Z
C
V
C
T
D
F
C
T
T
Z
C
V
E
E
A
T
S
C
L
P
F
I
T
E
O
T
E
I
F
E
_
B
I
A
S
E
F
E
I
4
9
5
0
5
1
5
2
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
1
3
2
7
2
8
2
9
3
0
3
9
3
8
3
7
3
6
3
5
3
4
3
1
3
2
3
3
LD
RF
TC
RF
_M
RF
_O
RF
_I
CB
CC
1
FO
K
CC
2
CP
PD
2
PD
1
PD
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
S
L
_
P
S
L
_
O
I
S
E
T
V
C
C
C
L
K
D
A
T
A
X
R
S
T
S
L
_
M
L
O
C
K
C
.
O
U
T
X
L
T
S
E
N
S
1
S
E
N
S
2
R
2
5
1
0
k
R
3
7
1
2
0
k
Electrical Characteristics Measurement Circuit
15
CXA1992BR
Application Circuit 1 (2.5V power supply)
0.1
680k
510k
0.015
Vcc
MICRO
COMPUTER
DSP
0.033
2200p
0.1
0.1
100k
4.7
DRIVER
0.033
Vcc
100k
15k
22
3.3
DRIVER
1
0
0
k
0.015
60k
V
EE
0
.
0
1
0
.
0
3
3
0.01
22k
Vcc
22
100
1
10H
100
500
V
EE
V
EE
100k
150k
0.047
0.1
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
F
E
O
F
E
I
F
D
F
C
T
F
G
D
F
L
B
F
E
_
O
F
E
_
M
S
R
C
H
T
G
U
T
G
2
F
S
E
T
T
A
_
M
SENS1
C. OUT
XRST
DATA
XLT
CLK
Vcc
ISET
SL_O
SL_M
SL_P
P
D
2
P
D
1
P
D
L
D
R
F
_
M
R
F
_
O
R
F
_
I
C
P
C
B
C
C
1
C
C
2
F
O
K
8
2
k
Vcc
1k
3.3
A
C
B
D
F
E
T
A
_
O
DRIVER
8.2k
LOCK
SENS2
R
F
T
C
PD
LD
1
M
1
V
EE
V
EE
FE_BIAS
47k
330k
470p
10k
10k
0.022
0.022
FZC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
39
38
37
36
35
34
31
32
33
41
42
45
46
47
48
49
50
51
52
1
40
44
43
0.01
0.01
Application Circuit 2 (Single +5V power supply)
0.1
680k
510k
0.015
Vcc
MICRO
COMPUTER
DSP
0.033
2
2
0
0
p
0.1 0.1 100k
4.7
DRIVER
0.033
Vcc
100k
15k
22
3.3
DRIVER
1
0
0
k
0.015
60k
0
.
0
1
0
.
0
3
3
0.01
22k
Vcc
22
100
1
10H
100
500
100k
150k
0.047
0.1
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
F
E
O
F
E
I
F
D
F
C
T
F
G
D
F
L
B
F
E
_
O
F
E
_
M
S
R
C
H
T
G
U
T
G
2
F
S
E
T
T
A
_
M
SENS1
C. OUT
XRST
DATA
XLT
CLK
Vcc
ISET
SL_O
SL_M
SL_P
P
D
2
P
D
1
P
D
L
D
R
F
_
M
R
F
_
O
R
F
_
I
C
P
C
B
C
C
1
C
C
2
F
O
K
8
2
k
Vcc
1k
3.3
A
C
B
D
F
E
T
A
_
O
DRIVER
8.2k
LOCK
SENS2
R
F
T
C
PD
LD
1
M
1
FE_BIAS
47k
330k
470p
10k
10k
0.022
0.022
FZC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
39
38
37
36
35
34
31
32
33
41
42
45
46
47
48
49
50
51
52
1
40
44
43
0.01
0.01
10
10
V
CC
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
16
CXA1992BR
Description of Functions
RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58k
equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the
photo diode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check
can be performed at this pin.
The low frequency component of the RFO output voltage is V
RFO
= 2.2
(V
A
+ V
B
) = 127.6k
(iPD1 + iPD2).
V
RFO
= (VA + VB 2V3) +V3
= 2.2 {58k
(iPD1 + iPD2) + V1 + V2 2V3} + V3.
V1 = V2 = V3 are set , and V
RFO
= 127.6k
(iPD1 + iPD2) + V3
1k
3.3
A
C
B
D
PD1
iPD1
PD2
iPD2
58k
VA 10k
VC
PD1 IV AMP
58k
VB 10k
VC
PD2 IV AMP
RF_M
RF_O
22k
V3
RF SUMMING AMP
39
38
34
33
V1
V2
FOK
DEFECT
22k
10k
17
CXA1992BR
Focus Error Amplifier
FE_BIAS
FEO
FEI
FE_O
FE_M
PD2
PD1
SENS1
SENS2
R8
100k
V
EE
20mV
FOCUS
PHASE
COMPENSATION
SENS
SELECTOR
VH
VIN > VH L
VIN < VH H
FOH
20mV
VL
VIN > VL H
VIN < VL L
FOL
VC
VC
VC
R11
100k
DRIVER
GND
GND
C1
2200p
R9
10k
R10
10k
R1
4k
VC
VC
R4
32k
R2
58k
V
CC
R7
174k
VC
R5
32k
R3
58k
PD2 IV AMP
PD1 IV AMP
I
F
B
6
32
I
F
B
5
16
I
F
B
4
8
I
F
B
3
4
I
F
B
2
2
I
F
B
1
1
RESET : IFB1 to IFB6 ON
25mV/STEP
B + D
A + C
40
39
38
2
6
7
25
26
1
VIN
R6
174k
VB
FE AMP
V2
VA
V1
RF
RF
The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C B D).
The FEO output voltage:
174k
V
FEO
=
32k
(VA VB)
174k
=
32k
{(58k
iPD1) (58k
iPD2)}
= 315.4k
(iPD2 iPD1)
The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment.
The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and
OFF.
The 6-bit focus bias adjustment switches are controlled with commands.
IFB1 to IFB6 are all ON after a reset.
The voltage is varied by approximately 25mV per step.
18
CXA1992BR
Focus error amplifier offset adjustment (when adjusting the IC offset)
The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference
level.
The FEO and reference level are compared by the window comparator, and the comparison results are output
from SENS1 and SENS2. (ADDRESS
D11
001110
D6
)
Adjust the offset so that SENS1 and SENS2 are both High.
Set the reference level to the center 20mV.
25mV < 40mV < 50mV
Reference level width
Variable voltage per step
Variable voltage per 2 steps
Focus bias fine adjustment
Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while
monitoring a DSP jitter meter with the microcomputer.
The 6-bit focus bias adjustment switches are controlled with commands.
When performing conventional focus bias adjustment
Fix the focus bias adjustment switches to the desired settings. (for example, IFB6 ON)
In this condition, adjust the focus bias by turning a volume connected to FE_BIAS (Pin 40).
[Example circuit]
3.9k
V
CC
V
EE
FE_BIAS
Volume 47k
40
19
CXA1992BR
The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO.
The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at the E I-V amplifier.
E I-V AMP feedback resistance = R1 + R4 +
F I-V AMP feedback resistance = R2 + R5 + = 403k
Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance
adjustment switches (BAL1 to BAL4).
The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches
(TOG1 to TOG4).
The balance and gain adjustment switches are controlled with commands.
Set the cut-off frequency of the external LPF between 10Hz to 100Hz.
Tracking Error Amplifier
LPFI
TEO
F
CLK
DATA
XRST
XLT
SENS1
SENS2
VIN > VH L
VIN < VH H
BALH
VH
20mV
VC
VIN
20mV
VC
VL
VIN > VL H
VIN < VL L
BALL
VIN > VH L
VIN < VH H
TGH
VH
200mV
VC
VIN
150mV
VC
VL
VIN > VL H
VIN < VL L
TGL
SENS
SELECTOR
COMAND
CONTROL
CPU
R23
100k
R24
150k
C3
0.01
C4
0.01
GND
GND
VC
R
2
1
3
.
3
k
R
2
0
7
.
5
k
R
1
9
1
6
k
R
1
7
1
0
k
R22
1.5k
R18
7.5k
R16
96k
TE AMP
NORMAL
R14
13k
R9
17k
GAIN UP
GAIN UP
R8
17k
VC
R12
96k
R13
13k
V
NORMAL
TGFL
TGFL
C2
12p
R2
260k
R5
13k
R3
26k
VC
VC
C1
12p
R1
260k
R4
6.8k
VC
EI
E
VF
VE
F I-V AMP
E I-V AMP
R
7
1
1
0
k
R
1
0
5
6
k
R
1
1
2
7
k
R
1
5
1
3
k
R
6
7
5
k
RE
VC
+
20
21
22
23
25
26
41
42
43
45
46
COMAND
CONTROL
B
A
L
1
B
A
L
2
B
A
L
3
B
A
L
4
T
O
G
4
T
O
G
3
T
O
G
2
T
O
G
1
R1
R4
RE
R2
R5
R3
20
CXA1992BR
Balance adjustment
The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external
LPF, extracting the offset DC, and comparing it to the reference level.
However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete offset DC can not be extracted.
To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency
that can lower a sufficient gain appears on the LPF.
Use the C.OUT output to check this frequency.
The offset DC and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS
D11
001100
D6
)
Adjust the balance so that the SENS1 and SENS2 pins are both High.
Gain adjustment
Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component
to the reference level.
The AC component is generated by taking the difference between TE and the offset DC input to Pin 46.
The AC component and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS
D11
001101
D6
)
The comparison signal is as follows.
SENS1 pin
BALH
SENS2 pin
BALL
H
L
H
H
L
H
V
IN
< V
L
< V
H
V
L
< V
IN
< V
H
V
L
< V
H
< V
IN
V
H
: High level threshold value
V
IN
: Window comparator input signal
V
L
: Low level threshold value
SENS1 pin
TGH
H
H
L
SENS2 pin
TGL
V
H
V
L
V
IN
(1)
(2)
(3)
The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2).
When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the
TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL
(SENS2 pin).
21
CXA1992BR
APC & Laser Power Control
LD
R
F
T
C
RF_O
RF_I
PD
V
EE
V
CC
R8
10k
V
EE
R5
55k
R10
56k
R12
56k
R11
10k
R4
10k
R6
1k
LDON
R14
12.5k
V
L
VREF
LPC ON/OFF
50%/17%
670mV
R9
41k
VC
R7
13k
V
EE
RF
3V: 1.2V
5V: 1.52V
1.1Vpp
R13
1M
V
EE
V
EE
C4
1
R1
22
C2
100
C1
1
V
EE
R3
100
R2
500
130mV
GND
LD
PD
L1
10H
V
CC
C3
0.01
37
36
35
32
33
APC
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics.
The APC circuit is used to maintain the optical power output at a constant level.
The laser diode current is controlled according to the monitor photo diode output.
Laser power control
The RF level is stabilized by attaching an offset to the APC V
L
and controlling the laser power in sync with the
RF level fluctuations.
The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR.
This signal is then compared with the reference level.
The laser power is controlled by attaching an offset to V
L
according to the results of comparison with the
reference level.
Set the reference level to 670mV. (center voltage reference)
LPC ON/OFF and LD ON/OFF control is performed with commands.
The laser power control limit can also be switched between 50% and 17% with commands.
LPC
OFF
ON
ON
--
50%
17%
Approximately 1.27V
Approximately 1.27V 625mV
Approximately 1.27V 208mV
LPCL
V
L
variable range
22
CXA1992BR
Center Voltage Generation Circuit
(The figure below shows a single voltage application; Connect to GND for dual power supplies.)
Maximum current is approximately 3mA. Output impedance is approximately 50
.
50
V
CC
V
EE
VC
Connected internally to the V
EE
pin.
30k
30k
V
CC
GND
VC
51
23
CXA1992BR
Focus Servo
6k
54k
FE
2200p
10k
FEO
FEI
100k
DFCT
FS4
Focus
phase
Compensation
68k
100k
FE_O
FOCUS COIL
FE_M
100k
ISET
60k
11
22
FS2
FS1
50k
50k
4.7
0.015
510k
0.1
FSET
FLB
40k
0.1
0.1
680k
FDFCT
FGD
SRCH
SENS
SELECTOR
2
3
4
5
6
7
8
11
17
1
FS3
52
10k
0.022
FZC
300k
FZC
25 SENS1
Charge
up
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68k
resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100k
resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 5 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510k
is
connected to Pin 11.
The focus search height is approximately 1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and V
EE
. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 10% of Vcc and VC (Pin 51); (Vcc VC)
10%.
510k
resistance is recommended for Pin 11.
24
CXA1992BR
Tracking and Sled Servo
+
TE
TEO
BUFFER AMP
LPFI
0
.
0
1
0
.
0
1
150k
100k
DFCT
TEI
100k
TDFCT
0
.
1
ATSC
4
7
0
p
3
3
0
k
47k
0.047
0.022
TZC
TZC
TGU
TG2
0.033
470k
TG2
20k
510k
0.015
FSET
Tracking Phase
Compensation
10k
90k
TM4
TM3
11A
11A
100k
TRACKING
COIL
82k
15k
22
3.3
SL_P
TM2
TM6
TM5
22A
22A
100k
1k
1k
100k
ATSC
8.2k
1
2
0
k
0
.
0
1
5
M
SLED MOTOR
SL_O
SL_M
TM1
680k
680k
66p
TA_M
TA_O
TG1
TM7
9
10
11
12
13
14
15
16
19
45
46
47
48
49
50
GAIN
WINDOW
COMPARATOR
BALANCE
WINDOW
COMPARATOR
SENS
SELECTOR
SLED ON/OFF
CONTROL
BALH
BALL
TGH
TGL
47k
25
26
LOCK
SENS1
SENS2
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to cut the high-frequency gain when TG2 is
OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510k
resistance is connected to Pin 11. In the CXA1992AR, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current
feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 (or TM6) current
feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and V
EE
.
When this resistance is 60k
:
TM3 (or TM4) = 11A, and TM5 (or TM6) = 22A.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100k
) and the capacitance connected to Pin 50.
The ISET pin is used to connect external resistance. This external resistance sets the current which
determines the focus search, track jump, and sled kick heights.
Focus search current
I
1
=
(V
BG
: approximately 1.27V)
I
2
= 2I
1
Track jump current (TM3 and TM4 current)
I =
Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands)
I =
Use external resistance of between 30k
to 240k
.
Using external resistance outside this range may cause oscillation.
25
CXA1992BR
FS1
I
2
I
1
V
BG
R
1
2
V
BG
R
V
BG
R
1
2
26
CXA1992BR
Focus OK Circuit
RF
15k
92k
VG
54k
20k
V
CC
0.63V
RF_O
RF_I
FOK
1
FOCUS OK AMP
FOCUS OK
COMPARATOR
C5
0.01
27
32
33
DEFECT
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 32 from Pin 33 (RF signal), and the LPF output (opposite phase) of the focus
OK amplifier output is also obtained.
The focus OK output is inverted when V
RFI
V
RFO
0.37V.
Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK
amplifier. Ordinarily, with a C5 equal to 0.01F selected, the fc is equal to 1kHz, and block error rate
degradation brought about by RF envelope defects caused by scratched discs can be prevented.
Defect Circuit
After inversion, RF_O signal is bottom held by means of the long and short time constants.The long time
constant bottom hold keeps the mirror level prior to the defect.
The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1msec, and this is
defferentiated and level-shifted through the AC coupling circuit.
The long and short time-constant signals are compared to generate at mirror defect detection signal.
RF_O
a
2
b
DEFECT AMP
CC1
CC2
SENS1
CB
0.01
0.033
DEFECT SW
DEFECT COMPARATOR
DEFECT BOTTOM
HOLD
e
c
d
25
26
28
30
33
SENS2
SENS
SELECTOR
DFCT1
FLIP
FLOP
DFCT2
29
INTERRUPTION
COMPARATOR
f
RF
FOK
e
d
c
b
a
BOTTOM
HOLD (1)
solid line
CC1
DEFECT
AMP
RFO
DFCT1
BOTTOM
HOLD (2)
dotted line
CC2
H
L
f
INT
H
L
27
CXA1992BR
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1992AR, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP with MIRR input pin, input the C.OUT output to the MIRR input of
the DSP.
RF
0.033
RF_O
RF_I
CP
MIRROR
COMPARATOR
PEAK &
BOTTOM
HOLD
1.4
K
MIRROR HOLD AMP
J
H
I
1
G
MIRROR AMP
32
33
SENS
SELECTOR
26
31
MIRR
SENS2
DEFECT
FOK
RF_O
H
L
0V
0V
0V
0V
G
(RF_I)
H
(PEAK HOLD)
I
(BOTTOM HOLD)
(MIRROR HOLD)
J
K
MIRR
28
CXA1992BR
SENS Selector
25 SENS1
FZC
DFCT1
TZC
BALH
TGH
FOH
ATSC
SENS2
HIGH-Z
DFCT2
MIRR
BALL
TGL
FOL
26
What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin.
DATA (Pin 22) 8-bit transfer
SENS1
SENS2
ADDRESS
D7
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FZC
DFCT1
TZC
H
(HIGH-Z)
H
(HIGH-Z)
DFCT2
MIRR
H
(HIGH-Z)
D6
D5
D4
D3
D2
D1
D0
DATA
DATA (Pin 22) 12-bit transfer
SENS1
SENS2
ADDRESS
D11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BALH
TGH
FOH
ATSC
BALL
TGL
FOL
H
(HIGH-Z)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
Notes)
12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and
SENS2 are switched according to the D3 and D2 data.
SENS1 and SENS2 are switched without latching.
29
CXA1992BR
Commands
The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is
represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0
and F/$XXX for 12-bit.
Commands for the CXA1992AR can be broadly divided into four groups ranging in value from $0X, $1X, $2X,
$3XX.
1. $0X (FZC at SENS1 pin (Pin 25), H (Hi-Z) at SENS2 pin (Pin 26))
These commands are related to focus servo control.
The bit configuration is as shown below.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
FS4
--
FS2
FS1
Four focus related switches exist: FS1, FS2, FS4 and DFCT.
$00
When FS1 = 0, Pin 8 is charged to (22A 11A)
50k
= 0.55V.
If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
$02
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.
(22A 11A)
50k
.... Equation 1
The SRCH DOWN speed can be increased by the charge up circuit.
$03
From the state described above, FS1 becomes 1, and a current source of +22A is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.
Fig. 1. Voltage at Pin 8 when FS1 goes from 0
1
This time constant is obtained with the 50k
resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)
resistance between Pins 6 and 7
50k
0V
0V
$
00 02
03
02
03
00
02
30
CXA1992BR
The instant when the signal is brought into focus.
$08
$03
($00)
$02
(20ms) (200ms)
Drive voltage
Focus error
SENS1
(FZC)
Focus OK
The broken lines in the figure
indicate the voltage assuming
the signal is not in focus.
1-1. FS4
This switch is provided between the focus error input and the focus phase compensation, and is in charge of
turning the focus servo ON and OFF.
$00
$08
Focus off Focus on
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
Fig. 3. S-curve
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig.
3. To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 25) as the point A transit signal.
In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
t
A
Fig. 4. Focus ON timing chart
31
CXA1992BR
2. $1X (DFCT1 at SENS1 pin (Pin 25), DFCT2 at SENS2 pin (Pin 26))
These commands deal with switching TG1/TG2, brake circuit ON/OFF,
and the sled kick output.
The bit configuration is as follows:
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
TG1, TG2 Break
Sled kick
circuit
height
ON/OFF ON/OFF
TG1, TG2, TM7
The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track
jump has been performed actually though a 100-track jump was intended to be done due to the extremely
degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump.
For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to
the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between
the RF envelope and the tracking error is 180 out-of-phase to cut the unneeded portion of the tracking error
and apply braking.
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC
?
NO
YES
F. OK ?
NO
Transfer $08
Latch
FZC
?
NO
F. OK ?
NO
Transfer $08
Latch
(A)
(B)
YES
YES
YES
Fig. 5. Poor and good software command sequences
D1
(PS1)
0
0
1
1
D0
(PS0)
0
1
0
1
1
2
3
4
Relative
value
Sled kick height
32
CXA1992BR
Envelope
Detection
Waveform
Shaping
Waveform
Shaping
Edge Detection
[
B]
[
E]
RF_I
TZC
CXA1992
(Latch)
Q
D
CK
(MIRR)
[
C]
[
F]
[
G]
BRK
D2
TM7
Low: open
High: make
[
A]
[
D]
[
H]
32
49
Fig. 6. TM7 movement during braking operation
From inner to outer track
0V
From outer to inner track
("MIRR")
("TZC")
Braking is applied
from here.
[
A]
[
B]
[
C]
[
D]
[
E]
[
F]
[
G]
[
H]
Fig. 7. Internal waveform
3. $2X (TZC at SENS1 pin (Pin 25), MIRR at SENS2 pin (Pin 26))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Tracking
Sled
control
control
00
off
00
off
01
Servo ON
01
Servo ON
10
F-JUMP
10
F-FAST FORWARD
11
R-JUMP
11
R-FAST FORWARD
TM1, TM3, TM4,
TM2, TM5, TM6
33
CXA1992BR
4. $3XX
These commands mainly control the balance and gain control circuit switches used during automatic tracking
adjustment and the bias circuit switch used during automatic focus bias adjustment.
In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to 6
switches are ON.
Balance adjustment
The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches
are set using D0 to D3.
At this time, SENS1 outputs BALH and SENS2 outputs BALL.
Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0.
Sending a latch pulse with D6, D7
0 does not change the balance switch settings.
START
C.OUT
is the frequency high
enough ?
SENS1/2
Balance OK ?
Adjustment Completed
BAL1 to BAL4
Switch Control
YES
NO
Gain adjustment
The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches
are set using D0 to D3.
At this time, SENS1 outputs TGH and SENS2 outputs TGL.
In a fashion similar to the method used with the balance adjustment, set the data by specifying switch
conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.
START
SENS1/2
GAIN OK ?
Adjustment Completed
TOG1 to TOG4
Switch control
YES
NO
Balance adjustment
Gain adjustment
34
CXA1992BR
Focus bias adjustment
The focus bias adjustment switches IFB1 to 6 can be controlled by setting D6 = 0 and D7 = 1. The switches
are set using D0 to D5.
At this time, SENS1 outputs FOH and SENS2 outputs FOL.
Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.
START
SENS1/2
BIAS OK ?
Adjustment Completed
IFB1 to 6
Switch Control
YES
NO
Focus bias adjustment method
TGFL
The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0.
The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0.
The TEO signal level can be made higher by approximately 6dB for GAIN UP.
When the TEO signal level is low and TGH (SENS1 pin) does not go Low during tracking adjustment, the
gain should be raised with the TGFL command for adjustment.
LPC
The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1.
The circuit is ON with D0 = 1 and OFF with D0 = 0.
LPCL
The laser power control limit can be switched between 17% and 50% by setting D1 with D6 = 1 and D7 = 1.
The control limit is 17% with D1 = 0 and 50% with D1 = 1.
LDON
The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1.
The laser diode is ON with D2 = 1 and OFF with D2 = 0.
35
CXA1992BR
ATSC
The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1.
This function is disabled with D3 = 1 and enabled with D3 = 0.
At this time, SENS1 outputs ATSC.
Even if ATSC is disabled, ATSC is output to SENS1.
When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode.
(In the Block Diagram, TG1 is set to the side and TG2 is OFF. Even if TG1 and TG2 are NORMAL mode,
they switch to GAIN UP mode in conjunction with ATSC.)
When the anti-shock function is not used, Pin 48 (ATSC) should be connected to VC.
RDFCT2
DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1.
DFCT2 is reset with D4 = 1.
After a reset, High is held when DFCT1 rises.
During $1X commands, DFCT2 is output from SENS2.
DFCT2 operates even if DFCT is disabled.
Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed.
INT
The interruption (scratched disc) countermeasure circuit can be set to operating status by setting D5 with D6
= 1 and D7 = 1.
This circuit is enabled when D5 = 1 and disabled when D5 = 0.
Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise.
When MIRR rises, the DFCT switch is routed through the low-pass filter.
The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking
gain is increased. (including when the gain is increased by ATSC or LOCK)
Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.
Parallel direct interface
LOCK (Sled overrun prevention circuit)
This circuit operates when LOCK is low.
When LOCK is low, the sled is OFF, and TG1 and TG2 are UP (TRACKING GAIN UP).
SLED
LOCK
TM2 SW: side
SLED ON
NORMAL
TG1 SW: side
TG2 ON
UP
TG1 SW: side
TG2 OFF
TM2 SW: side
SLED OFF
TRACKING GAIN
When LOCK is not used, Pin 19 (LOCK) should be pulled up to V
CC
with the resistor of approximately 47k
.
36
CXA1992BR
CPU Serial Interface Timing Chart
t
WCK
D0
D1
D2
D3
D4
D5
D6
D7
D0
t
WCK
t
SU
1/fck
t
h
t
CD
t
WL
t
D
DATA
CLK
XLT
Item
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
Data transfer interval
Low level input voltage
High level input voltage
Symbol
fck
fwck
t
su
t
h
t
D
t
WL
t
CD
V
IL
V
IH
Min.
500
500
500
500
1000
1000
0.0
(V
CC
V
EE
)
0.9
Typ.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
V
V
1
(V
CC
V
EE
)
0.1
V
CC
(V
CC
= 3.0V)
37
CXA1992BR
System Control
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
SLED MODE
D7
D6
D5
D4
FS4
Focus
1 = ON
0 = OFF
TG1, TG2
1 = GAIN UP
0 = NORMAL
0
0
0
0
0
0
0
0
1
0
1
0
--
BRAKE
1
=
ENABLE
0
=
DISABLE
FS2
SRCH
ON
1 = ON
0 = OFF
SLED
KICK + 2
FS2
SRCH
UP
1 = UP
0 = DOWN
SLED
KICK + 1
FZC
DFCT1
TZC
TRACKING MODE
1
SLED MODE
2
ADDRESS
D3
D2
D1
D0
DATA
DATA (Pin 22) 8-bit transfer
SENS1
H
(HIGH-Z)
DFCT2
MIRR
SENS2
1
TRACKING MODE
FWD JUMP
REV JUMP
D3
0
0
1
1
D2
0
1
0
1
OFF
ON
2
SLED MODE
FWD MOVE
REV MOVE
D1
0
0
1
1
D0
0
1
0
1
OFF
ON
Item
38
CXA1992BR
E-F
BALANCE
TRACKING
GAIN
FOCUS
BIAS
Others
D11
D10
D9
D8
DFCT
1 = DISABLE
0 = ENABLE
TGFL
1 = GAIN UP
0 = NORMAL
IFB6
1 = OFF
0 = ON
INT
1 = ENABLE
0 = DISABLE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
D7
D6
--
--
IFB5
1 = OFF
0 = ON
RDFCT2
1 = RESET
0 = NORMAL
BAL4
1 = OFF
0 = ON
TOG4
1 = OFF
0 = ON
IFB4
1 = OFF
0 = ON
ATSC
1 = DISABLE
0 = ENABLE
BAL3
1 = OFF
0 = ON
TOG3
1 = OFF
0 = ON
IFB3
1 = OFF
0 = ON
LDON
1 = ON
0 = OFF
BALH
TGH
FOH
ATSC
ADDRESS
D5
D4
D3
D2
BAL2
1 = OFF
0 = ON
TOG2
1 = OFF
0 = ON
IFB2
1 = OFF
0 = ON
LPCL
1 =
50%
0 =
17%
BAL1
1 = OFF
0 = ON
TOG1
1 = OFF
0 = ON
IFB1
1 = OFF
0 = ON
LPC
1 = ON
0 = OFF
D1
D0
DATA
DATA (Pin 22) 12-bit transfer
SENS1
BALL
TGL
FOL
H
(HIGH-Z)
SENS2
Item
Notes)
When ATSC is enabled, even if TG1 and TG2 are NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC and LOCK
.
INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased b
y ATSC or LOCK)
When reset
SENS1 = FZC
SENS2 = High (Hi-Z)
RDFCT2 = 1 (Reset)
IFB1 to IFB6 = 0 (switch ON)
TOG1 to TOG4 = 0 (switch ON)
BAL1 to BAL4 = 1 (switch ON)
Other data is "0".
39
CXA1992BR
Serial Data Truth Table
Serial Data
FOCUS CONTROL
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
0001 1010
0001 1011
0001 1100
0001 1101
0001 1110
0001 1111
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
Functions
FS4
BRAK SLD KICK
KICK
+1
KICK
+2
Fig. 6
D2
TG1
TG2
TRACKING CONTROL
FS2
FS1
Notes) FS1
1: OFF
0: ON
FS2
1: ON
0: OFF
FS4
In the Block Diagram:
1: SW side
0: SW side
Notes) TG1
In the Block Diagram:
1: SW side
0: SW side
TG2
1: OFF
0: ON
BRAKE
When D2 in Fig. 6 is:
1: 1
0: 0
Sled kick height
D1
0
0
1
1
0
1
0
1
1
2
3
4
D0
Relative value
40
CXA1992BR
Serial Data
TRACKING/SLED MODE
0010 0000
0010 0001
0010 0010
0010 0011
0010 0100
0010 0101
0010 0110
0010 0111
0010 1000
0010 1001
0010 1010
0010 1011
0010 1100
0010 1101
0010 1110
0010 1111
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
HEX
Function
TM6 TM5 TM4 TM3
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
TM2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
TM1
Notes) TM1/TM2
In the Block Diagram:
1: SW side
0: SW side
TM3/TM4/TM5/TM6
1: ON
0: OFF
41
CXA1992BR
Serial Data
$3XX
0011 0000 0000
0011 0000 0001
0011 0000 0010
0011 0000 0011
0011 0000 0100
0011 0000 0101
0011 0000 0110
0011 0000 0111
0011 0000 1000
0011 0000 1001
0011 0000 1010
0011 0000 1011
0011 0000 1100
0011 0000 1101
0011 0000 1110
0011 0000 1111
0011 0001 0000
0011 0001 0001
0011 0001 0010
0011 0001 0011
0011 0001 0100
0011 0001 0101
0011 0001 0110
0011 0001 0111
0011 0001 1000
0011 0001 1001
0011 0001 1010
0011 0001 1011
0011 0001 1100
0011 0001 1101
0011 0001 1110
0011 0001 1111
0011 0010 0000
0011 0010 0001
0011 0010 0010
0011 0010 0011
0011 0010 0100
0011 0010 0101
0011 0010 0110
0011 0010 0111
0011 0010 1000
0011 0010 1001
0011 0010 1010
0011 0010 1011
0011 0010 1100
0011 0010 1101
0011 0010 1110
0011 0010 1111
$300
$301
$302
$303
$304
$305
$306
$307
$308
$309
$30A
$30B
$30C
$30D
$30E
$30F
$310
$311
$312
$313
$314
$315
$316
$317
$318
$319
$31A
$31B
$31C
$31D
$31E
$31F
$320
$321
$322
$323
$324
$325
$326
$327
$328
$329
$32A
$32B
$32C
$32D
$32E
$32F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
HEX
BAL SW
4 3 2 1 4 3 2 1
4
5
6
3 2 1
TOG SW
IFB SW
INT
RDF
CT2
ATSC LDON LPCL LPC DFCT
TGFL
42
CXA1992BR
Serial Data
$3XX
0011 0011 0000
0011 0011 0001
0011 0011 0010
0011 0011 0011
0011 0011 0100
0011 0011 0101
0011 0011 0110
0011 0011 0111
0011 0011 1000
0011 0011 1001
0011 0011 1010
0011 0011 1011
0011 0011 1100
0011 0011 1101
0011 0011 1110
0011 0011 1111
0011 0100 0000
0011 0100 0001
0011 0100 0010
0011 0100 0011
0011 0100 0100
0011 0100 0101
0011 0100 0110
0011 0100 0111
0011 0100 1000
0011 0100 1001
0011 0100 1010
0011 0100 1011
0011 0100 1100
0011 0100 1101
0011 0100 1110
0011 0100 1111
0011 0101 0000
0011 0101 0001
0011 0101 0010
0011 0101 0011
0011 0101 0100
0011 0101 0101
0011 0101 0110
0011 0101 0111
0011 0101 1000
0011 0101 1001
0011 0101 1010
0011 0101 1011
0011 0101 1100
0011 0101 1101
0011 0101 1110
0011 0101 1111
$330
$331
$332
$333
$334
$335
$336
$337
$338
$339
$33A
$33B
$33C
$33D
$33E
$33F
$340
$341
$342
$343
$344
$345
$346
$347
$348
$349
$34A
$34B
$34C
$34D
$34E
$34F
$350
$351
$352
$353
$354
$355
$356
$357
$358
$359
$35A
$35B
$35C
$35D
$35E
$35F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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--
--
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--
--
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--
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--
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--
--
--
--
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--
--
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--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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--
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--
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--
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--
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--
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--
--
--
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--
--
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--
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--
--
--
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--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HEX
BAL SW
4 3 2 1 4 3 2 1
4
5
6
3 2 1
TOG SW
IFB SW
INT
RDF
CT2
ATSC LDON LPCL LPC DFCT
TGFL
43
CXA1992BR
Serial Data
$3XX
0011 0110 0000
0011 0110 0001
0011 0110 0010
0011 0110 0011
0011 0110 0100
0011 0110 0101
0011 0110 0110
0011 0110 0111
0011 0110 1000
0011 0110 1001
0011 0110 1010
0011 0110 1011
0011 0110 1100
0011 0110 1101
0011 0110 1110
0011 0110 1111
0011 0111 0000
0011 0111 0001
0011 0111 0010
0011 0111 0011
0011 0111 0100
0011 0111 0101
0011 0111 0110
0011 0111 0111
0011 0111 1000
0011 0111 1001
0011 0111 1010
0011 0111 1011
0011 0111 1100
0011 0111 1101
0011 0111 1110
0011 0111 1111
0011 1000 0000
0011 1000 0001
0011 1000 0010
0011 1000 0011
0011 1000 0100
0011 1000 0101
0011 1000 0110
0011 1000 0111
0011 1000 1000
0011 1000 1001
0011 1000 1010
0011 1000 1011
0011 1000 1100
0011 1000 1101
0011 1000 1110
0011 1000 1111
$360
$361
$362
$363
$364
$365
$366
$367
$368
$369
$36A
$36B
$36C
$36D
$36E
$36F
$370
$371
$372
$373
$374
$375
$376
$377
$378
$379
$37A
$37B
$37C
$37D
$37E
$37F
$380
$381
$382
$383
$384
$385
$386
$387
$388
$389
$38A
$38B
$38C
$38D
$38E
$38F
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
HEX
BAL SW
4 3 2 1 4 3 2 1
4
5
6
3 2 1
TOG SW
IFB SW
INT
RDF
CT2
ATSC LDON LPCL LPC DFCT
TGFL
44
CXA1992BR
Serial Data
$3XX
0011 1001 0000
0011 1001 0001
0011 1001 0010
0011 1001 0011
0011 1001 0100
0011 1001 0101
0011 1001 0110
0011 1001 0111
0011 1001 1000
0011 1001 1001
0011 1001 1010
0011 1001 1011
0011 1001 1100
0011 1001 1101
0011 1001 1110
0011 1001 1111
0011 1010 0000
0011 1010 0001
0011 1010 0010
0011 1010 0011
0011 1010 0100
0011 1010 0101
0011 1010 0110
0011 1010 0111
0011 1010 1000
0011 1010 1001
0011 1010 1010
0011 1010 1011
0011 1010 1100
0011 1010 1101
0011 1010 1110
0011 1010 1111
0011 1011 0000
0011 1011 0001
0011 1011 0010
0011 1011 0011
0011 1011 0100
0011 1011 0101
0011 1011 0110
0011 1011 0111
0011 1011 1000
0011 1011 1001
0011 1011 1010
0011 1011 1011
0011 1011 1100
0011 1011 1101
0011 1011 1110
0011 1011 1111
$390
$391
$392
$393
$394
$395
$396
$397
$398
$399
$39A
$39B
$39C
$39D
$39E
$39F
$3A0
$3A1
$3A2
$3A3
$3A4
$3A5
$3A6
$3A7
$3A8
$3A9
$3AA
$3AB
$3AC
$3AD
$3AE
$3AF
$3B0
$3B1
$3B2
$3B3
$3B4
$3B5
$3B6
$3B7
$3B8
$3B9
$3BA
$3BB
$3BC
$3BD
$3BE
$3BF
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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--
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--
--
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--
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--
--
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--
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--
--
--
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--
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--
--
--
--
--
--
--
--
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--
--
--
--
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--
--
--
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--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
HEX
BAL SW
4 3 2 1 4 3 2 1
4
5
6
3 2 1
TOG SW
IFB SW
INT
RDF
CT2
ATSC LDON LPCL LPC DFCT
TGFL
45
CXA1992BR
Serial Data
$3XX
0011 1100 0000
0011 1100 0001
0011 1100 0010
0011 1100 0011
0011 1100 0100
0011 1100 0101
0011 1100 0110
0011 1100 0111
0011 1100 1000
0011 1100 1001
0011 1100 1010
0011 1100 1011
0011 1100 1100
0011 1100 1101
0011 1100 1110
0011 1100 1111
0011 1101 0000
0011 1101 0001
0011 1101 0010
0011 1101 0011
0011 1101 0100
0011 1101 0101
0011 1101 0110
0011 1101 0111
0011 1101 1000
0011 1101 1001
0011 1101 1010
0011 1101 1011
0011 1101 1100
0011 1101 1101
0011 1101 1110
0011 1101 1111
0011 1110 0000
0011 1110 0001
0011 1110 0010
0011 1110 0011
0011 1110 0100
0011 1110 0101
0011 1110 0110
0011 1110 0111
0011 1110 1000
0011 1110 1001
0011 1110 1010
0011 1110 1011
0011 1110 1100
0011 1110 1101
0011 1110 1110
0011 1110 1111
$3C0
$3C1
$3C2
$3C3
$3C4
$3C5
$3C6
$3C7
$3C8
$3C9
$3CA
$3CB
$3CC
$3CD
$3CE
$3CF
$3D0
$3D1
$3D2
$3D3
$3D4
$3D5
$3D6
$3D7
$3D8
$3D9
$3DA
$3DB
$3DC
$3DD
$3DE
$3DF
$3E0
$3E1
$3E2
$3E3
$3E4
$3E5
$3E6
$3E7
$3E8
$3E9
$3EA
$3EB
$3EC
$3ED
$3EE
$3EF
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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--
--
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--
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--
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--
--
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--
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--
--
--
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--
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--
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--
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--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
HEX
BAL SW
4 3 2 1 4 3 2 1
4
5
6
3 2 1
TOG SW
IFB SW
INT
RDF
CT2
ATSC LDON LPCL LPC DFCT
TGFL
Notes) 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values
of each bit for serial data.
"--" in the Truth Table indicates that the status does not change.
TGFL
In the Block Diagram:
1: SW side
0: SW side
ATSC E: enable/D: disable
DFCT E: enable/D: disable
46
CXA1992BR
Serial Data
$3XX
0011 1111 0000
0011 1111 0001
0011 1111 0010
0011 1111 0011
0011 1111 0100
0011 1111 0101
0011 1111 0110
0011 1111 0111
0011 1111 1000
0011 1111 1001
0011 1111 1010
0011 1111 1011
0011 1111 1100
0011 1111 1101
0011 1111 1110
0011 1111 1111
$3F0
$3F1
$3F2
$3F3
$3F4
$3F5
$3F6
$3F7
$3F8
$3F9
$3FA
$3FB
$3FC
$3FD
$3FE
$3FF
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
HEX
BAL SW
4 3 2 1 4 3 2 1
4
5
6
3 2 1
TOG SW
IFB SW
INT
RDF
CT2
ATSC LDON LPCL LPC DFCT
TGFL
47
CXA1992BR
Initial State (resetting state)
Item
FOCUS CONTROL
TRACKING CONTROL
TRACKING SLED MODE
ADDRESS
D7
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
$00
$10
$20
D6
D5
D4
D3
D2
D1
D0
DATA
HEX
Item
E-F BALANCE
TRACKING GAIN
FOCUS BIAS
Others
ADDRESS
D11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
$300
$340
$380
$3D0
D10 D9
D8
D7
D6
D5
D4
0
0
0
0
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
0
0
D0
DATA
HEX
The above data means the following operation modes.
FOCUS CONTROL
: FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN
TRACKING CONTROL
: TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative height value 1
TRACKING SLED MODE : TRACKING OFF, SLED OFF
E-F BALANCE
: BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE
TRACKING GAIN
: TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL
FOCUS BIAS
: IFB1 to IFB6 = 0 (switch ON)
Others
: INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL 17%, LPC OFF
48
CXA1992BR
2. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.
3. Focus/Tracking internal phase compensation and reference design material
Notes on Operation
1. Focus OK circuit
1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.
V
CC
20k
40k
100k
V
EE
V
EE
R
L
FOK
V
CC
27
The FOK and comparator output are as follows:
Output voltage High : V
FOKH
near Vcc
Output voltage Low : V
FOKL
Vsat (NPN) + V
EE
Item
SD
Measurement pin
Conditions
Typ.
Unit
1.2kHz gain
1.2kHz phase
1.2kHz gain
1.2kHz phase
2.7kHz gain
2.7kHz phase
08
08
25
25
25
13
25
13
6
C
FLB
= 0.1F
C
FGD
= 0.1F
21.5
63
13
125
26.5
130
dB
deg
dB
deg
dB
deg
C
TGU
= 0.1F
13
FCS
TRK
4. Laser power control
The RF level is stabilized by attaching an offset to the APC V
L
and controlling the laser power in sync with the
RF level fluctuations.
The laser life is shortened by increasing the laser power when the less light is reflected from the disc.
It is recommended that the typical laser power value is set lower to maintain the laser life.
Take care of the laser maximum ratings when using the laser power control circuit.
5. RF amplifier
The phase compensation value in the IC is set on condition that 20 to 30p capacitance of optical pickup and
line material is attached.
In case of voltage output-type pickup, resistor is inserted in series prior to PD1/PD2 pins. It looks capacitance
that attach to PD1/PD2 pins becomes smaller.
At this time, RF amplifier may oscillate. Connect a capacitance around 5 to 20p between PD1/PD2 pins and
GND, and use it.
49
CXA1992BR
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
LQFP-52P-L01
LQFP052-P-1010
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PALLADIUM PLATING
COPPER ALLOY
PACKAGE STRUCTURE
0.3g
52PIN LQFP(PLASTIC)
DETAIL A
NOTE: "
" Dimensions do not include mold protrusion.
(0.3)
0.32 0.07
+ 0.08
(
0
.
1
2
5
)
0
.
1
4
5
0
.
0
2
5
+
0
.
0
4
0 to 10
(
0
.
5
)
(
1
1
.
0
)
0
.
6
0
.
1
5
0.25
0.1 0.1
DETAIL B
0.1
0.13
M
10.0 0.1
12.0 0.2
1
13
14
26
27
39
40
52
0.32 0.07
+ 0.08
0.65
A
B
1.5 0
+ 0.1
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