Audio/Video Switch with Electronic Volume for 2 Scart
Description
The CXA2126Q is an I
2
C programmable audio, video
switch designed primarily for set top box applications. It
interfaces from digital encoder sources to TV and VCR
scart connectors.
Features
2 scart independent audio/video switching (TV, VCR)
Compatible with 3 scart Audio/Video switch,
CXA2125Q
0 to 63dB volume control with click noise reduction
3 stereo audio inputs
I
2
C control
Scart Function Switching input and output
Scart Fast Blanking for OSD
Mono switchable to stereo on TV and VCR outputs
On-chip +12V to +9V voltage regulator
Logic output
Selectable +6dB, +12dB gain on TV output
RGB input on VCR scart
Applications
Digital Set Top Box
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings
Supply voltage
V
CC
12
V
Operating temperature Topr
20 to +75
C
Storage temperature
Tstg
65 to +150
C
Allowable power dissipation
P
D
850
mW
Operating Conditions
Supply voltage
10.7 to 12
V
Operating voltage
9 0.5
V
1
E99339-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA2126Q
64 pin QFP (Plastic)
2
CXA2126Q
Block Diagram
2
2
ROUT1
34
LOUT1
36
8dB
1dB
0/6dB
MONO SWITCH
Selectable Gain Stage
MONO SWITCH
2
2
2
2
2
FBLK_IN1
DIG
Typical Connection
VCR
DIG BLUE
VCR BLUE
DIG GREEN/CVBS
VCR GREEN
DIG RED/CHROMA
DIG CHROMA
VCR RED/CHROMA
DIG CVBS/LUMA
DIG CVBS/LUMA
VCR CVBS/LUMA
TV CVBS
TV_FBLANK
+5V
0V
FBLK_IN2
FBLK_SW
100
VIN1
VIN2
VIDEO_SWITCH1 (TV)
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIDEO_SWITCH2 (VCR)
AUDIO_SWITCH1 (TV)
VOLUME CONTROL
& MUTE
8dB
ZCD
1dB
0/6dB
52
53
63
61
2
59
4
6
57
8
10
55
23
VID_V
CC
VID_BIAS
VID_GND
60
62
7
Bias
Mute
Bias
4.5V
Mute
Bias 1
4.05V
AUD_V
CC
DIG_V
CC
AUD_BIAS
AUD_GND
DIG_GND
20
19
26
Bias 2
4.5V
V
CC
_12V
VREG_BASE
VREG_9V
58
56
38
43
54
RIN1 (DIG)
3
RIN2 (VCR) 12
RIN3 (TV) 22
9V reg
6dB
6dB
LIN1 (DIG)
5
LIN2 (VCR) 14
LIN3 (TV) 24
6dB
6dB
SDA 11
SCL
9
FNC_VCR 64
HW_MUTE 45
Monitor
TV BLUE
TV GREEN
TV RED/C
TV CVBS/Y
VCR CHROMA
VCR CVBS/Y
Typical Connection
50
VOUT1
100
48
2
VOUT2
100
47
2
VOUT3
100
46
2
VOUT4
100
49
2
VOUT5
100
41
2
VOUT6
100
44
FNC_TV
30
LOGIC
28
2
MONO
33
PHONO_R
35
RTV
40
LTV
TV
42
PHONO_L
37
AUDIO_SWITCH2 (VCR)
I
2
C
Interface
LOGIC
P.O.D
VCR
TV
VCR
3.3V or 5V
3
CXA2126Q
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FBLK_IN1
FBLK_IN2
VREG_9V
VIN10
VREG_BASE
VIN7
V
CC
_12V
VIN4
VID_V
CC
VIN2
VID_BIAS
VIN1
FNC_VCR
N
C
V
I
N
3
R
I
N
1
V
I
N
5
L
I
N
1
V
I
N
6
V
I
D
_
G
N
D
V
I
N
8
S
C
L
V
I
N
9
S
D
A
R
I
N
2
N
C
L
I
N
2
N
C
N
C
17 18 19
N
C
N
C
A
U
D
_
B
I
A
S
N
C
T
V
_
F
B
L
A
N
K
V
O
U
T
4
V
O
U
T
1
V
O
U
T
2
V
O
U
T
3
H
W
_
M
U
T
E
V
O
U
T
6
D
I
G
_
G
N
D
L
T
V
V
O
U
T
5
R
T
V
N
C
D
I
G
_
V
C
C
P
H
O
N
O
_
L
L
O
U
T
1
33
34
35
P
H
O
N
O
_
R
R
O
U
T
1
M
O
N
O
NC
NC
FNC_TV
NC
LOGIC
NC
AUD_GND
NC
LIN3
VIN11
RIN3
NC
AUD_V
CC
NC = No connect
Pin Configuration
4
CXA2126Q
Pin Description
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
63
61
2
59
55
23
4
6
57
8
10
V
CC
= 12V
V
CC
= 9V
14
A
120k
147
60
A
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
4.6V
Video signal inputs.
An input coupling
capacitor is required.
(typ = 0.47F)
63
61
2
59
4
6
57
8
10
55
23
12
22
14
24
V
CC
= 12V
33k
33k
7
A
4.5V
RIN2
RIN3
LIN2
LIN3
4.5V
Audio signal inputs.
An input coupling
capacitor is required.
(typ = 2.2F)
12
22
14
24
48
47
46
49
41
44
V
CC
= 12V
V
CC
= 9V
140
A
280
A
200
100
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
3.9V
Video signal outputs.
48
47
46
49
41
44
35
37
33
40
34
42
36
V
CC
= 12V
V
CC
= 9V
55
20k
22k
20k
33
A
33
A
RTV
ROUT1
LTV
LOUT1
PHONO_R
PHONO_L
MONO
4.5V
Audio signal outputs.
A coupling capacitor may
be used.
(typ = 10F)
40
34
42
36
35
37
33
5
CXA2126Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
62
V
CC
= 12V
V
CC
= 9V
14
A
11k
9k
200
BIAS_
VIDEO
3.9V
Reference Bias for video
circuit.
Connected to GND with
capacitor.
(typ = 47F)
62
7
A
19
V
CC
= 12V
V
CC
= 9V
20k
20k
BIAS_
AUDIO
4.5V
Reference Bias for audio
circuit.
Connected to GND with
capacitor.
(typ = 22F)
19
30
V
CC
= 12V
120
3k
15k
FNC_TV
--
I
2
C controlled output
giving 0V, 6V or 12V.
30
120
A
54
V
CC
= 12V
77.7k
13.5k
VREG_9V
9V
Pin connected to emitter
of external regulator
transistor.
54
6
CXA2126Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
56
V
CC
= 12V
V
CC
= 12V
1mA
120
A
413
15pF
VREG_
BASE
9.7V
Connection to base of
external regulator
transistor.
Max I = 1mA
56
9
V
CC
= 9V
40
A
4k
10k
40k
SCL
--
I
2
C clock input.
9
11
V
CC
= 9V
40
A
4k
4.5k
40k
SDA
--
I
2
C data input/output.
11
V
CC
= 12V
45
147
28k
72k
HW_MUTE
--
HW MUTE: This pin is
active high > 2.5V < 9V.
When high, all audio
outputs are muted.
45
7
CXA2126Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
28
V
CC
= 12V
V
CC
= 9V
8
A
7.5k
3V
4.5k
40k
LOGIC
--
Open collector logic pins.
28
50
V
CC
= 12V
V
CC
= 9V
100
A
100
A
100
100
FBLK_
OUT
--
Fast Blank output set by
I
2
C to input FBLK_IN1 or
FBLK_IN2.
High = 5.3V
Low = 1.2V
Connected to external
emitter follower.
50
52
53
V
CC
= 12V
V
CC
= 9V
147
90
A
50
A
FBLK_IN1
FBLK_IN2
--
Fast Blank inputs.
Low = < 0.4V
High = > 1.0V, < 3.0V
52
53
80
A
64
12.5k
12.5k
10k
25k
V
CC
= 9V
FNC_VCR
--
Function switching input.
(Scart pin 8)
64
8
CXA2126Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
3
5
V
CC
= 12V
33k
7
A
4.5V
RIN1
LIN1
4.5V
Audio signal inputs.
A coupling capacitor is
required for these inputs.
(typ = 2.2F)
3
5
9
CXA2126Q
Electrical Characteristics
Nominal conditions (Ta = 25C)
V
CC
_12V = 12V, No signal, no load
Current consumption
I
CC
30
50
80
mA
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Video system
Nominal conditions (Ta = 25C, Vcc_12V = 12V, VREG_9V = 9V)
Input pin voltage
Output pin voltage with
output on.
Output pin voltage with
output off.
Gain
Bandwidth
Input dynamic range
Output dynamic range
Cross talk
S/N ratio
Input impedance
Non-linearity
Differential gain
Differential phase
Sync crush
V
VPin
V
VPout1
V
VPout2
GVv
f
V3dB
V
DRVI
V
DRVO
Vctv
S/N
V
Zin
V
Lin
DG
DP
SC
4.3
3.6
--
5.5
15
2.5
5.0
--
--
80
3
3
3
2
4.6
3.9
0
6.0
20
--
--
--
72
120
0.4
1.5
1
0
4.9
4.2
0.5
6.5
--
--
--
50
--
175
3
2
2
2
V
V
V
dB
MHz
Vp-p
Vp-p
dB
dB
k
%
%
Deg
%
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
V2
V1
2
No signal, no load (Fig.1)
No signal, no load (Fig.1)
No signal, no load (Fig.1)
f = 200kHz, 0.3Vp-p input (Fig.2)
0.3Vp-p input, frequency where output
level is 3dB with 200kHz serving as
0dB (Fig. 2)
200kHz input (Fig.2)
200kHz, 2.5Vp-p input (Fig.2)
f = 4.43MHz, 1Vp-p input (Fig.2)
Ratio of 0.7Vp-p white video signal to
"black line" noise. Weighted using CCIR
567. HPF @5kHz, LPF @5MHz. (Fig.2)
1Vrms 1kHz input through 56k
.
Attenuation measured to calculate Zin
V
(Fig.3)
(Fig.4)
V1 = Pin voltage +0.5V,
V2 = Pin voltage +1V
At output, non-linearity = 1
100
1.7Vp-p 5-step modulated staircase.
(Chroma and Burst are 150mVp-p
4.43MHz) (Fig.2)
as above. (Fig.2)
Percentage reduction in sync pulse
(0.4Vp-p), with tip at 1.2V input offset.
(Fig.4)
V
2
V
1
I
n
p
u
t
P
i
n
V
P
l
u
s
10
CXA2126Q
Audio system
Unless otherwise stated: input coupling capacitor 1F; output coupling capacitor of 10F; load of 10k
.
Nominal conditions (Ta = 25C, Vcc_12V = 12V, VREG_9V = 9V)
No signal, no load (Fig. 5)
f = 1kHz, 0.5Vrms input.
TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 0.5Vrms input.
TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 1Vrms input. (Fig. 6)
f = 1kHz, 0.5Vrms stereo input.
TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 0.5Vrms stereo input.
TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 0.5Vrms stereo input. (Fig. 6)
f = 1kHz, 1Vrms input.
TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 1Vrms input.
TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 1Vrms stereo input.
TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 1Vrms stereo input.
TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 1Vrms input. (Fig. 6)
f = 1kHz, 1Vrms stereo input. (Fig. 6)
0.3Vp-p input. Output level at 30kHz
with 1kHz serving as 0dB. (Fig. 7)
0.3Vp-p input; frequency where output
level is 3dB with 1kHz serving as 0dB.
No load (Fig. 7)
f = 1kHz, 0.5Vrms, unweighted response;
LPF @400Hz, HPF @80kHz. (Fig. 6)
f = 1kHz (Fig. 6)
f = 1kHz (Fig. 6)
f = 1kHz, 1Vrms input on one input,
measure on any other audio output.
(Fig.6)
Input/output pin voltage
Audio frequency response
Frequency B/W
Distortion
Input dynamic range
RIN2, 3 LIN2, 3
Input dynamic range
RIN1, LIN1
Cross talk
(Switch separation)
V
APIN
GV
A1
GV
A2
GV
A3
GV
A4
GV
A5
GV
A6
GV
A7
GV
A8
GV
A9
GV
A10
GV
A11
GV
A12
F
AF
F
BWA1
THD
V
dA1
V
dA2
V
ctA
4.2
5.5
11
--
--
--
--
0.5
5.5
0.7
5
0.5
0.7
0.3
--
--
2
1
--
4.5
6
12
6
6
12
6
0
6
0
6
0
0
0
1
0.003
--
--
--
4.8
6.5
13
--
--
--
--
+0.5
6.5
+0.3
7
+0.5
+0.3
+0.3
--
0.2
--
--
76
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
%
Vrms
Vrms
dB
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Output
TV/Phono
TV/Phono
VCR
TV mono
TV mono
VCR mono
TV/Phono
TV/Phono
TV mono
TV mono
VCR
VCR mono
Gain Input
RIN1/LIN1
RIN1/LIN1
RIN1/LIN1
RIN1 + LIN1
RIN1 + LIN1
RIN1 + LIN1
RIN2, 3
LIN2, 3
RIN2, 3
LIN2, 3
RIN2, 3
+ LIN2, 3
RIN2, 3
+ LIN2, 3
RIN2, 3
LIN2, 3
RIN2, 3
+ LIN2, 3
Voff
Zin1
Zin2
Zout
Vpda
S/N
A
A
EVC
A
EVF
Amute
VoffTV
11
CXA2126Q
Offset voltage between input and
output (Fig. 5)
(excluding any external series resistor)
(excluding any external series resistor)
(excluding any external series resistor)
f = 1kHz, 1Vrms input to two channels.
Phase difference of stereo output
measured
f = 1kHz, 1Vrms input (at maximum
volume).
HPF @20Hz, LPF@20kHz. (Fig. 6)
f = 1kHz, 0.5Vrms input. Set by I
2
C.
(Fig.6)
f = 1kHz, 0.5Vrms input. Set by I
2
C.
(Fig.6)
f = 1kHz, 1Vrms input. (Fig.6)
Offset voltage between any audio input
and RTV, LTV outputs. (Fig.5)
DC offset
Input impedance
RIN2, 3/LIN2, 3
Input impedance
RIN1/LIN1
Output impedance
Phase difference
S/N ratio
Electronic Volume Control
Fine volume attenuation
step
Coarse volume attenuation
step
Mute
DC Offset -RTV, LTV
30
--
--
--
--
80
0.6
7.5
--
30
--
66
33
10
0.05
90
1
8
--
0
+30
--
--
--
--
--
1.4
8.5
80
+30
mV
k
k
Deg
dB
dB
dB
dB
mV
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
12
CXA2126Q
High level input voltage
Low level input voltage
Low level output voltage
Maximum clock frequency
Minimum waiting time for
data change
Minimum waiting time for
data transfer start
Low level clock pulse width
High level clock pulse width
Minimum waiting time for
start preparation
Minimum data hold time
Minimum data preparation
time
Rise time
Fall time
Minimum waiting time for
stop preparation
I
2
C Electrical Characteristics
Nominal conditions (Ta = 25C, Vcc_12V = 12V, VREG_9V = 9V)
With SDA, 3mA current supplied
V
IH
V
IL
V
OL
f
SCL
t
BUF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
R
t
F
t
SU;STO
2.3
0
0
0
4.5
4.0
4.7
4.0
4.7
5
250
--
--
4.7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
5.0
1.5
0.4
100
--
--
--
--
--
--
--
1
300
--
V
V
V
kHz
s
s
s
s
s
s
ns
s
ns
s
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
13
CXA2126Q
47
F
BC547B
+12V
+9V
22
F
SDA
SCL
+9V
+9V
+9V
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
Measurement
point
Measurement
point
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
CXA2126Q
V
Fig. 1. Video system (d.c. test)
Signal applied to Pins 2, 4, 6, 8, 10, 23, 55, 57, 59, 61, 63
Output signal measured from Pins 41, 44, 46, 47, 48, 49
Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
2. All video outputs are loaded with emitter follower during tests.
14
CXA2126Q
2.2
F
Input
signal
47
F
75
2.2
F
75
2.2
F
75
2.2
F
BC547B
+12V
+9V
75
2.2
F
75
22
F
2
.
2
F
7
5
7
5
7
5
7
5
7
5
2
.
2
F
2
.
2
F
2
.
2
F
2
.
2
F
SDA
SCL
+9V
+9V
+9V
1k
+12V
BC547B
75
2.2
F
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
Measurement
point
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
CXA2126Q
V
Signal applied to Pins 2, 4, 6, 8, 10, 23, 55, 57, 59, 61, 63
Output signal measured from Pins 41, 44, 46, 47, 48, 49
Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
2. For tests requiring video measuring equipment with 75
input impedance, an external video line
driver or buffer is used.
3. All video outputs are loaded with emitter follower during tests.
Fig. 2. Video system (gain, dynamic range, bandwidth, differential gain, differential phase,
crosstalk, signal to noise)
15
CXA2126Q
2.2
F
47
F
56k
2.2
F
56k
2.2
F
56k
2.2
F
BC547B
+12V
+9V
56k
2.2
F
56k
22
F
2
.
2
F
5
6
k
5
6
k
5
6
k
5
6
k
5
6
k
2
.
2
F
2
.
2
F
2
.
2
F
2
.
2
F
SDA
SCL
+9V
+9V
+9V
56k
2.2
F
Input
signal
1kHz
Measurement
point
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
CXA2126Q
Fig. 3. Video system (input impedance)
Signal applied and measured from Pins 2, 4, 6, 8, 10, 23, 25, 55, 57, 59, 61, 63
Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
2. Voltage measurements carried out with a high input impedance DVM. Typically 10G
.
16
CXA2126Q
47
F
BC547B
+12V
+9V
22
F
SDA
SCL
+9V
+9V
+9V
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
1k
+12V
BC547B
Measurement
point
Input
signal
PSU
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
CXA2126Q
V
Fig. 4. Video system (linearity)
Signal applied to Pins 2, 4, 6, 8, 10, 23, 55, 57, 59, 61, 63
Output signal measured from Pins 41, 44, 46, 47, 48, 49
Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
2. All video outputs are loaded with emitter follower during tests.
17
CXA2126Q
47
F
BC547B
+12V
+9V
22
F
SDA
SCL
+9V
+9V
+9V
Input
measurement
point
Output
measurement
point
V
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
CXA2126Q
HW
mute
+5V
1k
SW1
Fig. 5. Audio system (d.c. tests)
d.c. measured from pins: 3, 5, 12, 14, 22, 24, 33, 34, 35, 36, 37, 40, 42
Note) All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
18
CXA2126Q
47
F
BC547B
+12V
+9V
2
2
F
2
.
2
F
6
0
0
6
0
0
6
0
0
6
0
0
6
0
0
2
.
2
F
2
.
2
F
SDA
SCL
+9V
+9V
2
.
2
F
2
.
2
F
6
0
0
2
.
2
F
600
600
2.2
F
2.2
F
Input
signal
Measurement
point
V
CXA2126Q
10k
1
0
F
1
0
F
1
0
F
1
0
F
1
0
F
1
0
F
1
0
F
+9V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
HW
mute
+5V
1k
SW1
Signal applied to Pins, 3, 5, 12, 14, 22, 24
Output signal measured from Pins 33, 34, 35, 36, 37, 40, 42
Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
2. When muting audio using hardware mute, SW1 is closed.
Fig. 6. Audio system (gain, dynamic range, signal to noise, crosstalk, distortion, volume control)
19
CXA2126Q
47
F
BC547B
+12V
+9V
2
2
F
2
.
2
F
6
0
0
6
0
0
6
0
0
6
0
0
2
.
2
F
2
.
2
F
SDA
SCL
+9V
+9V
2
.
2
F
600
600
2.2
F
2.2
F
Input
signal
Measurement
point
V
CXA2126Q
1
0
F
1
0
F
1
0
F
1
0
F
1
0
F
1
0
F
1
0
F
+9V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
17 18 19
33
34
35
HW
mute
+5V
1k
SW1
Signal applied to Pins, 3, 5, 12, 14, 22, 24
Output signal measured from Pins 33, 34, 35, 36, 37, 40, 42
Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
2. When muting audio using hardware mute, SW1 is closed.
Fig. 7. Audio system (bandwidth and frequency responce)
20
CXA2126Q
G
R
E
E
N
D
i
g
i
t
a
l
E
n
c
o
d
e
r
2
.
2
F
2
.
2
F
1
F
1
F
10
F
1
0
F
5
6
0
1
0
F
5
6
0
1
F
1
F
4
7
F
1
0
n
F
1
0
F
7
5
7
5
1
k
2
.
2
F
+
1
2
V
+
1
2
V
+
1
2
V
2
.
2
F
2
.
2
F
2
.
2
F
B
C
5
4
7
B
C
X
A
2
1
2
6
Q
B
C
5
4
7
B
B
C
5
4
7
B
B
C
5
4
7
B
2
.
2
F
2
.
2
F
2
.
2
F
2
.
2
F
2
2
F
1
0
F
2
.
2
F
1
0
k
1
0
n
F
1
0
F
1
0
n
F
R
E
D
C
H
R
O
M
A
A
U
D
I
O
R
A
U
D
I
O
L
F
A
S
T
B
L
A
N
K
B
L
U
E
C
V
B
S
L
U
M
A
I
2
C
1
F
T
V
S
C
A
R
T
V
C
R
S
C
A
R
T
1
k
1
0
k
7
5
56
0
7
5
1
9
1
7
2
1
1
5
1
3
1
1
9
7
5
3
1
2
0
1
8
1
6
1
4
1
2
1
0
8
6
4
2
1
9
1
7
2
1
1
5
1
3
1
1
9
7
5
3
1
2
0
1
8
1
6
1
4
1
2
1
0
8
6
4
2
7
5
1
k
7
5
7
5
7
5
10
F
56
0
10
F
56
0
10
F
56
0
1
0
F
B
C
5
4
7
B
7
5
1
k
R
F
M
o
d
u
l
a
t
o
r
P
h
o
n
o
O
u
t
p
u
t
s
L
R
B
C
5
4
7
B
7
5
1
k
B
C
5
4
7
B
7
5
1
k
B
C
5
4
7
B
+
1
2
V
7
5
1
k
1
F
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
F
B
L
K
_
I
N
1
F
B
L
K
_
I
N
2
V
R
E
G
_
9
V
V
I
N
1
0
V
R
E
G
_
B
A
S
E
V
I
N
7
V
C
C
_
1
2
V
V
I
N
4
V
I
D
_
V
C
C
V
I
N
2
V
I
D
_
B
I
A
S
V
I
N
1
F
N
C
_
V
C
R
NC
VIN
3
RIN
1
VIN
5
LIN
1
VIN
6
VID
_G
ND
VIN
8
SC
L
VIN
9
SD
A
RIN
2
NC
LIN
2
NC
NC
1
7
1
8
1
9
NC
NC
A
UD
_B
IA
S
NC
TV
_F
BL
AN
K
VO
UT
4
VO
UT
1
VO
UT
2
VO
UT
3
HW
_M
UT
E
VO
UT
6
DIG
_G
ND
LT
V
VO
UT
5
RT
V
NC
DIG
_V
CC
PH
ON
O_
L
LO
UT
1
3
3
3
4
3
5
PH
ON
O_
R
RO
UT
1
MO
NO
N
C
N
C
F
N
C
_
T
V
N
C
L
O
G
I
C
N
C
A
U
D
_
G
N
D
N
C
L
I
N
3
V
I
N
1
1
R
I
N
3
N
C
A
U
D
_
V
C
C
Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo
r
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same
.
21
CXA2126Q
Description of Operation
1. Explanation of Video Section
The video section comprises of 11 high impedance inputs switched through to 6 video outputs. A +6dB internal
amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation which
occurs at the external emitter follower stage used for driving video loads. All video outputs have an integrated
100
series protection resistor. The typical external configuration is shown in Fig. 1-1.
Amp
Switch
1k
120k
75
75
0.47
F
Vbias
Vbias
Video Element
75
75
Load
+12V
Scart Out
Scart In
BC547B
100
VID_V
CC
= 9V
Fig. 1-1. Video Circuit Element: 6dB gain amplifier with external emitter follower
Switching the Video Outputs Off
Each video output can be individually turned off using the I
2
C. When turned off, the output is high impedance
and hence the current consumption of the external emitter followers is reduced.
22
CXA2126Q
2. Explanation of Audio System
Inputs and Outputs
The audio system consists of 3 stereo inputs, 2 stereo outputs and separate mono and phono outputs. The
stereo outputs can be connected to any one of the 3 stereo inputs. All audio inputs have a 6dB attenuator
except RIN1 and LIN1. Thus, the net gain of the audio system is 0dB, as the internal switch is followed by an
audio amplifier having +6dB of gain. The stereo input RIN1/LIN1 does not have an input attenuator and
therefore the net gain from input to output is +6dB. The output impedance of each audio amplifier is near zero,
and can be capacitively coupled directly to the external scart circuit. The output circuitry is typically a 10F
capacitor, and an optional 560
series compliance resistor. Depending on the length and type of cable used in
the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pF to
400pF) and mandatory 10k
resistor connected to ground. The customer may chose to place an alternative
audio filter at the AV switch output.
TV Audio Output
The TV audio section is composed of an audio switch followed by two variable gain stages, corresponding to
the coarse and fine electronic volume control. The coarse volume control gives a 0 to 56dB range in 8dB
steps. Similarly the fine control gives a 0 to 7dB range in 1dB steps. The volume control section is followed by
a switchable 0/+6dB amplifier which allows compensation for low level signals from a DAC. Finally, a mono
switch allows the mixed R + L signal to be switched to the R and L output channels. (Fig. 2-1)
Fig. 2-1. TV Audio Output
TV Mute
The I
2
C mute function acts only on the TV, phono and mono audio circuit. Audio mute can be implemented
after a audio zero cross detection to reduce click noise, or immediately depending on the I
2
C setting of ZCD. It
can be seen from the I
2
C write format that the same mute bit occurs in DATA 1 and DATA 7. This allows the
software to action an immediate mute, make any suitable changes to the audio source or electronic volume
control and after a minimum period of 6
90s (540s) un-mute the output buffer. Such a period provides
ample time to allow any transient ac voltages to settle during an audio source change.
10
F
560
C
Scart Pin
Optional
Low Pass Filter
TV Audio Output
Volume 0, 63dB + mute
Switchable Amp
8dB
1dB
0/6dB
Mono Switch
2
2
2
2
8dB
ZCD
1dB
0/6dB
RIN1
1
F
Audio
Source
3
RIN2 12
RIN3 22
6dB
6dB
LIN1
5
LIN2 14
LIN3 24
6dB
6dB
Mute
PHONO_R
35
RTV
40
LTV
42
PHONO_L
37
23
CXA2126Q
Zero Cross Detector (ZCD)
The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio
mute. The change volume or mute instruction sent by I
2
C will only be implemented when a minimal (ie zero
cross) signal amplitude is detected.
The zero cross detection circuit can be turned off by setting the "ZCD" bit low in the I
2
C write mode.
Hardware Mute
A hardware mute pin is provided which will mute all audio outputs when the pin voltage exceeds 2.5V. This
muting is instantaneous.
VCR Output
The outputs ROUT1 and LOUT1 have a fixed gain of 0dB from the input. If any attenuation is required then it is
possible to insert a series resistance on the input. (Fig. 2-2)
10
F
560
C
Scart Pin
Optional
Low Pass Filter
VCR Audio Output
MONO
SWITCH
2
2
1
F
Audio
Source
3
RIN2 12
RIN3 22
34
36
6dB
6dB
LIN1
5
LIN2 14
LIN3 24
6dB
6dB
ROUT1
LOUT1
RIN1
Mute
Fig. 2-2. VCR Audio Output
Phono Outputs
There is a stereo phono output which carries the same signal as the TV output. This is typically used for
connection to a hi-fi. The user may connect an external attenuator which is a.c. coupled to the outputs.
Mono Output
The mono output is a mix of the TV right and left channels.
24
CXA2126Q
I
2
C Data Interface Table
IC Control Data Format
Slave address A
DATA1
A
DATA2
A
DATA3
A
DATA4
A
DATAn
A
P
S
S: Start condition
A: Acknowledge
P: Stop condition
Address = 90H
I
2
C Data Structure (write mode)
Address
Data1
Data2
Data3
Data4
Data5
Data6
Data7
b7
1
EVC
Vid_Switch 1
TV
Vid_Switch 2
VCR
mono
VCR
mono
TV
Not used
FBLK
FNC
LOGIC
TV Aud
Gain
Vout5
Mute
TV Aud
Mute
b6
0
b5
0
b4
1
EVF
b3
0
b2
0
b1
0
b0
0 = Write
TV Aud
Mute
Z.C.D
Aud_Switch 1
TV
Aud_Switch 2
VCR
Vout2
on/off
Vout3
on/off
Vout4
on/off
Vout1
on/off
Vout6
on/off
Vout5
on/off
Key
EVC:
Electronic Volume Course (8dB steps)
EVF:
Electronic Volume Fine (1dB steps)
TV Aud Mute: TV Audio mute. Controls the TV audio output buffer. (Same bit appears in data 1 & 7)
Z.C.D:
Zero cross detector active. When ZCD = 1 volume and mute change at zero cross.
Vid_Switch 1: Selects the input video sources for Vout1, Vout2, Vout3, Vout4
Vid_Switch 2: Selects the input video sources for Vout5, Vout6
Aud_Switch 1: Selects one of 3 stereo inputs for RTV, LTV. PHONO_L, PHONO_R, MONO
Aud_Switch 2: Selects one of 3 stereo inputs for Rout1, Lout1
FNC:
Video function switch control
FBLK:
Video Fast Blanking control
LOGIC:
Logic outputs (open collector). 0 = high impedance. 1 = current sink mode.
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
25
CXA2126Q
I
2
C Data Format (read mode)
Slave address A
DATA8
P
NA
S
NA: No Acknowledge
I
2
C Data Structure (read mode)
Address
Data
b7
1
x
b6
0
x
b5
0
ZC Status
b4
1
P.O.D.
x
b3
0
b2
0
b1
0
b0
1 = Read
FNC_VCR
Key
FNC_VCR:
At Pin 64, AV switch monitors the voltage of pin 8 from VCR scart, and records status.
ZC Status:
ZC Status = 1 indicates that zero cross condition has been achieved after the ZCD is turned on.
P.O.D.:
Power On Detect. P.O.D. = 1 when DIG_V
CC
voltage rises above a threshold level of
approximately 5V.
26
CXA2126Q
3. Video Input I
2
C Control
Switch 1 (TV Output) Data 2 Bits 3, 4, 5
Vout1
(B)
Switch setting
Vout2
(Green)
Vout3
(R/C)
Vout4
(CVBS/Y)
Comment
VIN1
Bias
VIN2
Not used
Bias
Bias
Not used
Bias
0
x x 0 0 0 x x x
1
x x 0 0 1 x x x
2
x x 0 1 0 x x x
3
x x 0 1 1 x x x
4
x x 1 0 0 x x x
5
x x 1 0 1 x x x
6
x x 1 1 0 x x x
7
x x 1 1 1 x x x
VIN3
Bias
VIN4
Not used
Bias
Bias
Not used
Bias
VIN5
VIN6
VIN7
Not used
VIN5
Bias
Not used
Bias
VIN8
VIN9
VIN10
Not used
VIN3
VIN11
Not used
Bias
Digital encoder
Digital encoder
VCR
Not used
Digital encoder
TV
Not used
Video mute
Vout5
(Chroma (C))
Switch setting
Vout6
(CVBS/Y)
Comment
VIN5
VIN6
VIN7
Not used
VIN5
Not used
Not used
Bias
0
x x 0 0 0 x x x
1
x x 0 0 1 x x x
2
x x 0 1 0 x x x
3
x x 0 1 1 x x x
4
x x 1 0 0 x x x
5
x x 1 0 1 x x x
6
x x 1 1 0 x x x
7
x x 1 1 1 x x x
VIN8
VIN9
VIN10
Not used
VIN3
VIN11
Not used
Bias
Digital encoder
Digital encoder
VCR
Not used
Digital encoder
TV
Not used
Video mute
Note) After power on all TV outputs are off and muted.
Switch 2 (VCR Output) Data 3 Bits 3, 4, 5
Note) After power on VCR outputs are off and muted.
VCR Chroma Mute
Data 3 Bit 7
0 x x x x x x x = Vout5 active. Connected to input specified in above table.
1 x x x x x x x = Vout5 muted (the output dc bias still remains).
Standby Mode Control
Data 6 Bits 0, 1, 2, 3, 4, 5
Each video output can individually be turned off using data byte 6.
0 = Video Output off
1 = Video Output on
Note) When switched off, the video outputs are high impedance to prevent d.c. driving of the external emitter
follower stage.
The reduction of overall current consumption will depend on how many video outputs are turned off.
After power on all video outputs are in the off state.
27
CXA2126Q
4. Fast Blanking Operation (Pin 16 on SCART), FBLK
The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB
information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a
CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and
is defined as follows,
Fast blanking output at scart,
1. CVBS mode
Scart pin voltage = 0 to 0.4V
2. RGB mode
Scart pin voltage = 1 to 3.0V
Threshold voltage is approximately 0.75V at the scart input.
Fast Blanking I
2
C Control
In the CXA2126Q, there are two fast blanking inputs, one associated with the VCR RGB/CVBS input
(FBLANK_IN2), and another associated with the Digital Encoder input (FBLANK_IN1). These can be selected
by I
2
C. In addition to the two blanking inputs, the fast blank pin output can be set to a constant 0V or 5V by
means of the I
2
C control. Hence there are four possible states. These are controlled according to the following
table.
FBLK Control Data 5 Bits 3, 4, 5
Note) After power on the output is 0V.
Fast Blank output circuit
The output requires an external buffer stage to drive the required 75
scart termination.
The levels at the IC output are 0V and +5V.
Fast Blank Output
I
2
C Setting
0V
+5V
Same level as Fast Blank in 1 (0/+5V)
Same level as Fast Blank in 2 (0/+5V)
Not used
0V
0V
0V
0
x x 0 0 0 x x x
1
x x 0 0 1 x x x
2
x x 0 1 0 x x x
3
x x 0 1 1 x x x
4
x x 1 0 0 x x x
5
x x 1 0 1 x x x
6
x x 1 1 0 x x x
7
x x 1 1 1 x x x
1k
75
75
Scart line 16
V
CC
TV
Fast Blank
0V/5V
CXA2126Q
Fig. 4-1. Fast Blanking Interface to TV SCART
28
CXA2126Q
5. Function Switch, FNC.
The function switch facility is designed to read the status of the SCART function pin 8 from the VCR input. The
read register holds the status of the input function line.
The function output is controlled by I
2
C and is used to change the voltage on the function line to the TV. The
output can be connected directly to the scart pin. (Fig. 5-1)
Read Mode
Reads the status of the input FNC_VCR.
0
0
1
b1
0
1
1
b0
0 to +2V (default)
+4.5 to +7V
+9.5 to +12V
FNC_VCR
(Internal TV)
(16:9 External)
(4:3 External)
Level (SCART Defn.)
Read Data8
Input Pin Voltage
Write Mode
Controls the voltage at the TV function line (pin 8)
Mode/(Typical pin Voltage)
I
2
C Control (Data 5)
Internal TV/(1V)
External scart input 16:9 mode/(6V)
External scart input 4:3 mode/(11V)
External scart input 4:3 mode/(11V)
0
x x x x x 0 0 x
1
x x x x x 0 1 x
2
x x x x x 1 0 x
3
x x x x x 1 1 x
Note) After power on output is internal TV mode ie. 0V at the pin.
10k
Scart Pin 8
< 2V
> 4.5V < 7V
> 10V
FNC_TV
CXA2126Q
Fig. 5-1. TV Function Switch Output
29
CXA2126Q
6. Logic Output
A single logical output pin is provided. This is controlled via the I
2
C and is an open collector output.
Specification
I
2
C bit 0 = open collector/high output impedance
I
2
C bit 1 = Vsat (to 0.2V)
Vmax at logic pin = 12V
Imax during current sink = 1mA
Logic
cct.
I
2
C
LOGIC
Open collector logic
outputs
Fig. 6-1. Logic Output Interface
30
CXA2126Q
7. I
2
C Audio Signal Control
Outputs TV, VCR
Data 2, 3 Bits 0, 1, 2
Rin1
Rin2
Not used
Rin3
Audio mute
Audio mute
Audio mute
Audio mute
Lin1
Lin2
Not used
Lin3
Audio mute
Audio mute
Audio mute
Audio mute
RTV, ROUT1
LTV, LOUT1
0dB
1dB
1dB
3dB
4dB
5dB
6dB
7dB
Volume Control Fine
Data 1 Bits 2, 3, 4
Volume Control Coarse
Data 1 Bits 5, 6, 7
Switch Setting
0
x x x x x 0 0 0
1
x x x x x 0 0 1
2
x x x x x 0 1 0
3
x x x x x 0 1 1
4
x x x x x 1 0 0
5
x x x x x 1 0 1
6
x x x x x 1 1 0
7
x x x x x 1 1 1
Note) After power on the audio outputs are muted.
Setting
Volume Fine Control Gain
0
x x x 0 0 0 x x
1
x x x 0 0 1 x x
2
x x x 0 1 0 x x
3
x x x 0 1 1 x x
4
x x x 1 0 0 x x
5
x x x 1 0 1 x x
6
x x x 1 1 0 x x
7
x x x 1 1 1 x x
0dB
8dB
16dB
24dB
32dB
40dB
48dB
56dB
Setting
Gain
0
0 0 0 x x x x x
1
0 0 1 x x x x x
2
0 1 0 x x x x x
3
0 1 1 x x x x x
4
1 0 0 x x x x x
5
1 0 1 x x x x x
6
1 1 0 x x x x x
7
1 1 1 x x x x x
31
CXA2126Q
TV output amplifier
Data 7 Bit 6
x 0 x x x x x x = 0dB
x 1 x x x x x x = +6dB
Note) After power on the gain is set to 0dB.
TV Mono Switch
Data 7 Bit 3
x x x x 0 x x x = Normal stereo output
x x x x 1 x x x = Mono signal switched onto R + L Iine.
VCR Mono Switch
Data 7 Bit 4
x x x 0 x x x x = Normal stereo output
x x x 1 x x x x = Mono signal switched onto R + L Iine.
Mute and Zero Cross Operation
For TV, phono and mono outputs.
There are two mute control bits in the bus map to allow the TV outputs to be muted before the channel change
instruction occurs. The normal structure for a click free audio channel change is as follows:
Data 1 Mute the TV audio output with the ZCD switched on
Data 2 Change the TV audio source.
Data 7 Un-mute the TV audio output again with the ZCD switched on.
TV Aud Mute Data 1 Bit 1
Data 7 Bit 7
ZCD Data 1 Bit 0
RTV, LTV, Phono_R, Phono_L, Mono outputs
0
0
1
1
0
1
0
1
Un-mute immediately
Un-mute on next zero cross
Mute immediately
Mute on next zero cross
Note) After power on TV mute and ZCD are set to 0.
32
CXA2126Q
Notes on operation
1) Supply de-coupling capacitors, 10nF and 4.7F in parallel should be inserted as close to the supply pins,
20, 38, 60 as possible.
2) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB
track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the
video.
3) Attention should be given to the electrolytic capacitors on the input and output signal pins. As the pin's
voltage is between 3.7V and 4.7V dc the positive terminal on the capacitor should be orientated towards the
pin.
4) The audio outputs may be muted at any time after power up by connecting the HW_MUTE pin (45) to a
voltage > 2.5V and < 9V.
5) When driving video loads with impedance = 75
an emitter follower or video line driver is required to be
connected at the video outputs as shown in the application schematic.
Stray capacitance on pins Vout1-8 must be kept to a minimum by placing loads as close to the pins as
possible.
6) The supply voltage on pin 58 "V
CC
_12V" should not exceed +12V. If the supply has poor regulation then a
series diode or zener diode may be used to limit the voltage at this pin.
33
CXA2126Q
Inputs RIN1, LIN1 selected
Input [Vrms]
0
1
0.1
0.01
0.001
0.5
1
1.5
T
H
D
[
%
]
Audio frequency characteristics
Frequency [Hz]
Input = 0.3Vp-p
100
4
0
2
4
2
6
1k
10k
100k
1M
10M
A
u
d
i
o
O
u
t
p
u
t
/
I
n
t
p
u
t
g
a
i
n
[
d
B
]
Inputs RIN2, 3/LIN2, 3 selected
Input [Vrms]
0
0.1
0.01
0.001
0.0001
1
2
3
3.3
T
H
D
[
%
]
Video frequency characteristics
Frequency [Hz]
100k
4
6
8
0
2
1M
10M
50M
V
i
d
e
o
O
u
t
p
u
t
/
I
n
p
u
t
g
a
i
n
[
d
B
]
Typical audio output distortion
34
CXA2126Q
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
23.9 0.4
20.0 0.1
0.4 0.1
+ 0.15
1
4
.
0
0
.
1
1
19
20
32
33
51
52
64
0.15 0.05
+ 0.1
2.75 0.15
1
6
.
3
0.1 0.05
+ 0.2
0
.
8
0
.
2
M
0.2
0.15
+ 0.4
1
7
.
9
0
.
4
+
0
.
4
+ 0.35
64PIN QFP(PLASTIC)
QFP-64P-L01
QFP064-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
PACKAGE STRUCTURE
PLATING
1.5g
1.0
0 to10
PDF 
ZIP