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Электронный компонент: CXA3328TN/EN

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1
E00738D24-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA3328TN/EN
16 pin TSSOP (Plastic)
16 pin VSON (Plastic)
Analog Signal Processor RX-IF IC for W-CDMA Cellular Phones
Description
The CXA3328TN/EN is an analog signal processor
RX-IF IC for W-CDMA cellular phones. This IC contains
a gain control amplifier and quadrature demodulator.
Features
Wide gain control range
Linear gain slope
Wide band (100 to 600MHz)
Small package
16-pin TSSOP (CXA3328TN)
16-pin VSON (CXA3328EN)
Low voltage operation (2.7 to 3.3V)
Absolute Maximum Ratings
Supply voltage
V
CC
0.3 to 5.5
V
Operating temperature
Topr
55 to +125
C
Storage temperature
Tstg
65 to +150
C
Operating Conditions
Supply voltage
V
CC
2.7 to 3.3
V
Operating temperature
Ta
25 to +85
C
Structure
Bipolar silicon monolithic IC
Block Diagram
1/2
SWITCH
AGC
CONT
1/4
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
VCONT
V
CC
_BUF
GND_BUF
QX
Q
GND_BUF
IX
I
IN
INX
GND_IF
GND_IF
V
CC
_IF
LOCAL SW
LOCAL IN
GND_R
2
CXA3328TN/EN
Pin Description
20k
20k
Vcc_IF
GND_IF
1
2
Vcc_IF
30k
GND_IF
6
2k
0.5k
Vcc_IF
50
GND_IF
GND_R
7
2k
Vcc_BUF
GND_BUF
9
10
12
13
Pin
No.
Symbol
Typical pin
voltage [V]
Equivalent Circuit
Pin Description
1, 2
IN, INX
2.85
IF differential input.
3, 4
GND_IF
0
GCA, quadrature demodulator
block ground.
5
Vcc_IF
2.85
GCA, quadrature demodulator
block V
CC
.
6
LOCAL SW
--
Local frequency division ratio
setting.
High: 1/4 frequency division
Low: 1/2 frequency division
7
LOCAL IN
--
Local input.
9, 10,
12, 13
I, IX,
Q, QX
1.5
Baseband I, Q outputs.
8
GND_R
0
Local signal GND.
3
CXA3328TN/EN
Vcc_IF
40k
16k
12k
16k
12k
GND_IF
16
16
VCONT
--
Gain control voltage input.
11, 14
GND_BUF
0
Output buffer block ground.
15
Vcc_BUF
2.85
Output buffer block V
CC
.
Pin
No.
Symbol
Typical pin
voltage [V]
Equivalent Circuit
Pin Description
4
CXA3328TN/EN
Input Conditions
(V
CC
= 2.85V, Ta = 27C)
IF input frequency 1
IF input frequency 2
LO input frequency
LO input level
F
RXIF1
F
RXIF2
F
LO
V
LO
LOCAL SW = "L"
LOCAL SW = "H"
--
--
--
18
380
190
760
15
--
--
--
12
MHz
MHz
MHz
dBm
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
IF I/O Resistance (Design Values)
(V
CC
= 2.85V, Ta = 27C)
IF input
resistance
IF input
capacitance
R
IIF
C
IIF
Differential between Pins 1 and 2
380MHz
Differential between Pins 1 and 2
380MHz
--
--
2.6
2
--
--
k
pF
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Electrical Characteristics
Current Consumption
(V
CC
= 2.85V, Ta = 27C)
Current
Consumption
Icc
Vcont = 1.3V
1
8
11
15
mA
A
Item
Symbol
Conditions
Measure-
ment circuit
Measure-
ment point
Min.
Typ.
Max.
Unit
I/O Resistance
(V
CC
= 2.85V, Ta = 27C)
Input resistance
VCONT pin
LO input
resistance
Output resistance
I, IX, Q, QX pins
R
IVC
R
ILO
Z
OUT
DC measurement:
V
IN
= 2.85V
DC measurement:
I
IN
= 2mA
DC measurement:
I
OUT
= 100A
1
1
1
B
C
D, E
F, G
10
37.5
80
--
50
250
--
62.5
550
k
Item
Symbol
Conditions
Measure-
ment circuit
Measure-
ment point
Min.
Typ.
Max.
Unit
5
CXA3328TN/EN
GCA Block
(V
CC
= 2.85V, Ta = 27C)
Input conversion
noise figure
Input conversion
3rd intercept
point
Gain flatness
Minimum gain
Maximum gain
Gain temperature
error
NF
IIP3_1
IIP3_2
G
F
G
MIN
G
MAX
G
ERR
Gain = +65dB
Gain = +65dB
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
Gain = 10dB
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
F
RXIF
= 382 2.5MHz
LOCAL SW = "L"
F
LO
= 2
(F
RXIF
+ 2) MHz
Vcont = 0.3 [V],
30mVp-p differential output
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
Vcont = 2.3 [V],
100mVp-p differential output
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
Ta = 25 to +85C
3
2
2
2
2
2
2
A, B
C, D
A, B
C, D
A, B
C, D
A, B
C, D
A, B
C, D
A, B
C, D
A, B
C, D
--
58
10
0.25
--
67.5
4
--
--
--
--
25.5
72.5
--
10
--
--
0.25
20.5
--
4
dB
dBm
dBm
dB
dB
dB
dB
Item
Symbol
Conditions
Measure-
ment circuit
Measure-
ment point
Min.
Typ.
Max.
Unit
6
CXA3328TN/EN
Quadrature Demodulator Block
(V
CC
= 2.85V, Ta = 27C)
I/Q maximum
output amplitude
I/Q output band
width
I/Q phase error
I/Q output
amplitude balance
I-IX/Q-QX
DC offset
V
MAX
V
BW
P
ERR
V
BL
V
OFST
R
L
= 10k
, C
L
= 10pF
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
3dB band width
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
F
RXIF
= 382MHz
F
LO
= 760MHz
LOCAL SW = "L"
DC measurement
2
2
2
2
2
A, B
C, D
A, B
C, D
A, B
C, D
A, B
C, D
A, B
C, D
500
5
4
1.5
200
--
13
--
--
--
--
--
4
1.5
200
mVp-p
MHz
deg
dB
mV
Local Frequency Division Ratio
LOCAL SW (Pin 6)
L
H
Frequency division ratio
1/2
1/4
Item
Symbol
Conditions
Measure-
ment circuit
Measure-
ment point
Min.
Typ.
Max.
Unit
7
CXA3328TN/EN
Electrical Characteristics Measurement Circuit 1
1/2
SWITCH
AGC
CONT
1/4
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
VCONT
V
CC
_BUF
GND_BUF
QX
Q
GND_BUF
IX
I
IN
INX
GND_IF
100p
F
RXIF
82n
1
2
600
TRANS
50 : 500
1
GND_IF
V
CC
_IF
LOCAL SW
LOCAL IN
GND_R
B
G
F
E
D
C
A
1
LQN21A (MURATA MFG. CO., LTD.)
2
616DS-1135 (TOKO, Inc.)
8
CXA3328TN/EN
Electrical Characteristics Measurement Circuit 2
1/2
SWITCH
AGC
CONT
1/4
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
VCONT
V
CC
_BUF
GND_BUF
QX
Q
GND
IX
I
IN
INX
GND_IF
100p
F
RXIF
82n
1
2
600
TRANS
50 : 500
1
GND_IF
V
CC
_IF
LOCAL SW
LOCAL IN
GND_R
D
C
B
A
F
LO
1
MURATA LQN21A
2
TOKO 616DS-1135
10k
10p
10k
10p
10000p
10000p
10000p
10000p
10k
10p
10k
10p
9
CXA3328TN/EN
1/2
SWITCH
AGC
CONT
1/4
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
VCONT
V
CC
_BUF
GND_BUF
QX
Q
GND
IX
I
IN
INX
GND_IF
100p
82n
1
600
1
GND_IF
V
CC
_IF
LOCAL SW
LOCAL IN
GND_R
D
C
B
A
F
LO
1
MURATA LQN21A
10k
10p
10k
10p
10000p
10000p
10000p
10000p
10k
10p
10k
10p
Electrical Characteristics Measurement Circuit 3
10
CXA3328TN/EN
1/2
SWITCH
AGC
CONT
1/4
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
VCONT
V
CC
_BUF
GND_BUF
QX
Q
GND_BUF
IX
I
IN
INX
GND_IF
GND_IF
Vcc
Local signal
From receive
RF circuit
V
CC
_IF
LOCAL SW
LOCAL IN
GND_R
RX
BPF
Vcc
To LPF
Application Circuit
Adjust this value so that the impedance matching with this IC is optimum.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
11
CXA3328TN/EN
CXA3328TN/EN
LPF
CXA3309ER
LPF
CODEC
Digital processing mobile
station modem
RF receive/transmit
processing
CXG1110EN
1/2
1/4
Phase
Shifter,
Switch
IF
Local
OUT (I)
OUT (Q)
Description of Operation
1. Outline of Operation
This IC performs the signal processing between the analog transmit baseband processing block and the
analog transmit RF processing block of the cellular phone. The figure below shows the general circuit block
diagram for the portable cellular phone using this IC. The input of this IC is connected to the analog RF
processing block; the output is connected to the baseband signal processing block.
2. IC Internal Signal Flow
An IF signal and a local signal are input to this IC as shown in the figure below. The IF signal is gain-
controlled to the necessary level by the gain control amplifier and is input to the quadrature demodulator
block. The local signal is 1/2 or 1/4 frequency-divided. Also, that signal becomes the quadrature I/Q local
signal via the FF phase shifter and quadrature-demodulated with the IF signal to become the baseband
signal.
12
CXA3328TN/EN
Notes on Operation
1. IF Input
The IF signal is differentially input to the IN pin and INX pin of this IC. IF is input to the input pin by AC
coupling. The value of the AC coupling is selected so that the transfer power from the receive RF circuit is
maximum.
1
2
RX
BPF
CXA3328TN/EN
From receive
RF circuit
2. Notes on Power Supplies
The CXA3328TN/EN is designed to operate by a 2.85V stabilized power supply to allow use with the
battery driven portable phones. Using multiple voltage regulators throughout the phone is recommended to
minimize the power supply noise in the CXA3328TN/EN power supply input. The recommended power
supply range for the CXA3328TN/EN is 2.7 to 3.3V. Decouple the power supplies around the CXA3328TN/
EN using 1F capacitor for each V
CC
pin. Locate this capacitor as close to the pins as possible, and
minimize the series inductance for the pin connections. Using an additional 1nF decoupling capacitor in
parallel to the 1F capacitor is recommended to further reduce the high frequency noise in the power
supply input to the CXA3328TN/EN.
This value must be the value taken for the optimum impedance matching between the BPF filter and this IC.
13
CXA3328TN/EN
Voltage gain vs. Control voltage Vcont
1.5
80
70
60
50
40
30
20
10
0
10
20
30
1
0.5
0
2
2.5
3
Vcont [V]
V
oltage gain [dB]
Noise figure vs. Voltage gain
30
40
80
70
60
50
40
30
20
10
0
10
10
20
30
20
10
0
40
50
60
70
80
90
Voltage gain [dB]
Noise figure [dB]
IIP3 vs. Voltage gain
30
40
10
0
10
20
30
40
50
60
70
80
10
20
30
20
10
0
40
50
60
70
80
90
Voltage gain [dB]
IIP3 [dBm]
Example of Representative Characteristics
14
CXA3328TN/EN
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
PACKAGE STRUCTURE
0.03g
TSSOP-16P-L01
16PIN TSSOP (PLASTIC)
0.2 0.02
0.22 0.03
+ 0.036
0.1
0.01
0.12
0.02
+ 0.026
DETAIL B
X
X
0.1
1
0.5
0.08
S A
M
0.1
A B
X4
S
B
0.2
A B
X2
S
0.1
16
A
2.05
4.1
9
0 to 8
2.9
3.9
0.1 0.05
0.45
0.1
0.25
(3.0)
0.08 S
S
1.2MAX
B
8
Package Outline
Unit: mm
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18m
SPEC.
SCT & Kokubu Ass'y
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
PACKAGE STRUCTURE
0.03g
TSSOP-16P-L01
16PIN TSSOP (PLASTIC)
0.2 0.02
0.22 0.03
+ 0.036
0.1
0.01
0.12
0.02
+ 0.026
DETAIL B
X
X
0.1
1
0.5
0.08
S A
M
0.1
A B
X4
S
B
0.2
A B
X2
S
0.1
16
A
2.05
4.1
9
0 to 8
2.9
3.9
0.1 0.05
0.45
0.1
0.25
(3.0)
0.08 S
S
1.2MAX
B
8
CXA3328TN
15
CXA3328TN/EN
Package Outline
Unit: mm
0.05
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
PACKAGE STRUCTURE
TERMINAL SECTION
0.2
0.01
0.23
0.02
0.03
0.03
Soldrer Plating
0.14
ranges of 0.1mm and 0.25mm from the end of a terminal.
NOTE: 1) The dimensions of the terminal section apply to the
16PIN VSON (PLASTIC)
VSON-16P-01
0.02 g
0.2 S B
A
3.5
2.7
2.5
0.4
B
0.2 S
B
A
0.05 M S A-B
2x
4x
S
S
0.9 MAX
0.6
0.5
0.2
0.13 0.025
+ 0.09
0.03
1.4
0.35 0.1
0.35
0.1
0.05
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
PACKAGE STRUCTURE
TERMINAL SECTION
0.2
0.01
0.23
0.02
0.03
0.03
Soldrer Plating
0.14
ranges of 0.1mm and 0.25mm from the end of a terminal.
NOTE: 1) The dimensions of the terminal section apply to the
16PIN VSON (PLASTIC)
VSON-16P-01
0.02 g
0.2 S B
A
3.5
2.7
2.5
0.4
B
0.2 S
B
A
0.05 M S A-B
2x
4x
S
S
0.9 MAX
0.6
0.5
0.2
0.13 0.025
+ 0.09
0.03
1.4
0.35 0.1
0.35
0.1
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18m
SPEC.
SCT & Kokubu Ass'y
Sony Corporation
CXA3328EN