--1--
E92128B78-TE
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 C)
Supply voltage
V
DD
V
SS
0.5 to +7.0
V
Input voltage
V
I
V
SS
0.5 to V
DD
+0.5
V
Output voltage
V
O
V
SS
0.5 to V
DD
+0.5
V
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg
55 to +150
C
Recommended Operating Conditions
Supply voltage
V
DD
+3.5 to +5.5 (+5.0 Typ.) V
Operating temperature
Topr
20 to +75
C
Description
The CXD1196AR is a CD-ROM decoder LSI with a
built-in ADPCM decoder.
Features
CD-ROM, CD-I and CD-ROM XA format
compatible
Real time error correction
Double speed playback compatible
(when V
DD
=5.010 %)
Can be connected to a standard SRAM up to 32
Kbytes (256 Kbits).
All audio output sampling frequency : 132.3 kHz
(Built-in oversampling filter)
Built-in de-emphasis digital filter
Capable of V
DD
3.5 V operation
Applications
CD-ROM drive
Structure
Silicon gate CMOS IC
CD-ROM DECODER
80 pin LQFP (Plastic)
CXD1196AR
For the availability of this product, please contact the sales office.
--2--
CXD1196AR
Block Diagram
5-11.13-20
MAO-MA14
3
34
36
37
38
59
55
54
57
35
50
48
47
46
45
53
51
44
67
68
66
65
64
78
4
24-31
DMA
SEQUENCER
ADDRESS GEN
COP I/F
DESCRAMBLER
SYNC CONTROL
GALOIS FIELD
SYNDROME GEN
ECC
CORRECTOR
PRIORITY
RESOLVER
CLOCK GEN
DIGITAL
FILTER
DAC
I/F
ADPCM
DECODER
CPU DMA
CPU I/F
DMA FIFO
XMOE XMWR MDBO-MDB7
C2PO
BCLK
DATA
LRCK
XRST
XTL1 XTL2 CLK
WCKO
LRCO
DATO
BCKO
MUTE
69
DO-D7
XRD
XWR
XCS
AO
INT
INTP
DRO
XDAC
2.12.23.32.42.52.63.72
GND
33.73
V
DD
EMP
--3--
CXD1196AR
Pin Description
No.
Symbol
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TD7
GND
XMOE
XMWR
MA0
MA1
MA2
MA3
MA4
MA5
MA6
GND
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
TD6
TD5
GND
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
GND
V
DD
C2PO
EMP
BCLK
DATA
LRCK
TD4
TD3
I/O
--
O
O
O
O
O
O
O
O
O
--
O
O
O
O
O
O
O
O
I/O
I/O
--
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
--
--
I
I
I
I
I
I/O
I/O
Test pin
Ground pin
Buffer memory output enable negative logic signal
Buffer memory write enable negative logic signal
Buffer memory address (LSB)
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Ground pin
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address (MSB)
Test pin
Test pin
Ground pin
Buffer memory data bus (LSB)
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus (MSB)
Ground pin
Power supply pin
C2 pointer positive logic signal from CD player
Emphasis positive logic signal from CD player
Bit clock signal from CD player
Data signal from CD player
LR clock signal from CD player
Test pin
Test pin
--4--
CXD1196AR
No.
Symbol
I/O
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
TD2
GND
TD1
INTP
WCKO
LRCO
DATO
BCKO
N. C
MUTE
DRQ
GND
XDAC
XTL2
XTL1
TD0
CLK
TDIO
XRST
TA3
TA2
TA1
GND
XRD
XWR
XCS
INT
A0
D7
D6
D5
GND
V
DD
D4
D3
D2
D1
D0
TA0
N. C
I/O
--
I/O
I
O
O
O
O
--
O
O
--
I
O
I
I/O
O
I
I
I
I
I
--
I
I
I
O
I
I
I
I
--
--
I
I
I
I
I
I
--
Test pin
Ground pin
Test pin
INT pin polarity control signal
Word clock signal to DA converter
LR clock signal to DA converter
Data signal to DA converter
Bit clock signal to DA converter
Mute positive logic signal
DMA request positive logic signal
Ground pin
Acknowledge negative logic signal for DRQ
Crystal oscillator circuit output pin
Crystal oscillator circuit input pin
Test pin
Clock with 1/2 frequency of XTL1
Test pin
Chip reset negative logic signal
Test pin
Test pin
Test pin
Ground pin
CPU register read strobe negative logic signal
CPU register write strobe negative logic signal
Chip select negative logic signal from CPU
Interrupt request signal to CPU
CPU address signal
CPU data bus (MSB)
CPU data bus
CPU data bus
Ground pin
Power supply pin
CPU data bus
CPU data bus
CPU data bus
CPU data bus
CPU data bus (LSB)
Test pin
--5--
CXD1196AR
Electrical Characteristics
DC characteristics
(V
DD
=5 V10 %, V
SS
=0 V, Topr=20 to 75 C)
Item
TTL input level pin (
1)
input voltage H level
TTL input level pin (
1)
input voltage L level
CMOS input level pin (
2)
input voltage H level
CMOS input level pin (
2)
input voltage L level
TTL schmitt input level pin (
3)
input voltage H level
TTL schmitt input level pin (
3)
input voltage L level
TTL schmitt input level pin (
3)
input voltage hysteresis
CMOS schmitt input level pin (
4)
input voltage H level
CMOS schmitt input level pin (
4)
input voltage L level
CMOS schmitt input level pin (
4)
input voltage hysteresis
Pull-up resistor provided input pin
(
5) input current
Pull-down resistor provided input pin
(
6) input current
Pull-up resistor provided bidirectional
pin (
7) input current
Output voltage H level (
8)
Output voltage L level (
8)
Input leak current (
9)
Oscillation cell (
10) input voltage
H level
Oscillation cell input voltage L level
Oscillation cell logic threshold value
Oscillation cell feedback
resistance value
Oscillation cell output voltage H level
Oscillation cell output voltage L level
Symbol
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IL3
V
IH3
V
IL3
V
IH4
V
IL4
V
IH4
V
IL4
I
IL1
I
IL2
I
IL3
V
OH1
V
OL1
I
IL2
V
IH4
V
IL4
LV
TH
R
FB
V
OH2
V
OL2
Conditions
V
IN
=0 V
V
IN
=0 V
V
IN
=0 V
V
OH
=2 mA
I
OL
=4 mA
V
IN
=V
SS
or V
DD
I
OH
=3 mA
I
OL
=3 mA
Min.
Typ.
Max.
Unit
2.2
V
0.8
V
0.7 V
DD
V
0.3 V
DD
V
2.2
V
0.8
V
0.4
V
0.8 V
DD
V
0.2 V
DD
V
0.6
V
40
100
240
A
40
100
240
A
90
200
440
A
V
DD
0.8
V
0.4
V
40
40
A
0.7 V
DD
V
0.3 V
DD
V
0.5 V
DD
V
500 K
1 M
2 M
0.5 V
DD
V
0.5 V
DD
V
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