CXD2053AM/AS

E96531-ST

Auto Wide, EDTV-

ID Detection, ID-1 Detection

Description

The CXD2053AM/AS is an IC which has the three

functions of identifying the wide video (auto wide),

detecting the EDTV-

ID, and detecting ID-1 (EIAJ,

CPX1024) from the video signal.

Features

· Video aspect ratio identification used with wide

TVs is realized with a single chip.

· I

C bus interface.

This IC can also be used without the bus.

· For auto wide function, 525/60 (NTSC) and 625/50

(PAL, SECAM) can be Supported.

Applications

Wide TV

Structure

Silicon gate CMOS IC

Block Diagram

Absolute Maximum Ratings

· Supply voltage

0.5 to +7.0

· Input voltage

0.5 to V

+ 0.5

· Output voltage

0.5 to V

+ 0.5

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage

4.5 to 5.5

· Operating temperature

Topr

20 to +70

°C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2053AS

28 pin SDIP (Plastic)

C Bus Interface

VSIN

VDIN

ADIN

MCON

OED

OLBX

O164

OAW2

SDA

OAW1

SCL

Data Slice Sync
Separator

AD Converter

Auto wide
Identification

EDTV-

ID Decoder

Timing Signal
Generator

ID-1 Decoder

CXD2053AM

28 pin SOP (Plastic)

For the availability of this product, please contact the sales office.

CXD2053AM/AS

Pin Description

Pin
No.

ADIN

CPV

VRB

VRT

CCP

ISET

VSIN

VDIN

TST1

TST2

SCL
[EDDEC2]

SDA
[ED2FSC]

XRST

MCON

OLBX

O164

OAW1

OAW2

OED

I/O

ANALOG

TTL

CMOS

1, 3

TTL

CMOS

Analog power supply.

AD converter input.

Analog ground.

Clamp voltage.

AD converter bottom voltage.

AD converter top voltage.

AD converter clamp integrating capacitor connection.

Bias current setting.

Analog power supply

Sync separation input.

Data slicer input.

Analog ground.

Test input; connect to V

C bus clock [EDTV-

decoding identification switching]

C bus data [EDTV-

3.58 M check existence]

Digital ground.

Reset at 0.

C bus-free mode switching; 0 = I

C-free.

Digital system power supply.

Oscillator connection (14.318MHz).

Oscillator connection or clock input.

Digital ground.

VB-ID detection output; 1 = letter-box, 0 = normal.

VB-ID detection output; 1 = full mode.

Auto wide identification output; 1 = wide video subtitles not present.

Auto wide identification output; 1 = wide video subtitles present.

EDTV-

ID bit 3 detection output.

Symbol

I/O

I/O level

Description

Schmitt input

With pull-down resistor

Open drain

Note) In I

C-free mode when Pin 19 (MCON) = 0, Pins 15 and 16 switch to the functions in parentheses [ ].

CXD2053AM/AS

Electrical Characteristics

DC Characteristics (Logic Section)

= 5.0V, V

= 0V, Ta = 25°C)

Item

Output voltage

Input voltage

Input hysteresis
width

Input leak current

Output leak current

Input current

Feedback resistor

Current consumption

Vhys

Rfbk

= 2mA

= 4mA

= 3mA

= either V

or V

= eother V

or V

= V

XI (Pin 22) = either
V

or V

Clock 14.318MHz

0.8

2.2

0.7

0.8

0.05

250k

0.4

100

0.4

0.8

0.3

0.2

+10

+40

240

2.5M

µA

Pins 24, 25, 26,
27 and 28

Pin 21 only

Pin 16 only

Pins 13, 14, 18
and 19

Pin 22 only

Pins 15 and 16

Pin 18

Except for Pins
13, 14 and 22

Pin 16 only

Pins 13 and 14

Between Pins 21
and 22

Sum of Pins 1, 9
and 20

Symbol

Condition

Min.

Typ.

Max.

Unit

Remarks

Item

Clock frequency

fxi

14.318

MHz

Pin 22 input, or
oscillator between
Pins 21 and 22

Symbol

Condition

Min.

Typ.

Max.

Unit

Remarks

AC Characteristics

= 5.0V, V

= 0V, Ta = 25°C)

Item

Input pin
capacitance

Output pin
capacitance

Input/output pin
capacitance

OUT

I/O

= V

= 0V,

f = 1MHz

= V

= 0V,

f = 1MHz

= V

= 0V,

f = 1MHz

Symbol

Condition

Min.

Typ.

Max.

Unit

Remarks

I/O Pin Capacitance

CXD2053AM/AS

Pins and Electrical Characteristics

Analog Section

= 5.0V, V

= 0V, Ta = 25°C)

Pin
No.

ADIN

CPV

VRB

VRT

CCP

Symbol

Equivalent circuit

Description

AD converter analog power supply.
Connect a low-noise power supply from the
digital system.

AD converter analog ground.
Connect to the same potential as other V

and AV

AD converter input.
This pin is pedestal clamped to the
potential of CPV (Pin 4), so input the video
signal with capacitor coupled.

ADIN (Pin 2) pedestal clamp voltage
setting.

AD converter input range setting.
The resistor between Pins 5 and 6 is 310

(Typ.).

Clamp circuit integrating capacitor
connection. Connect 0.022µF between this
pin and AV

(Pin 3).

Not connected to V

(Pin 20) or AV

(Pin 9) inside the IC.

Not connected to V

(Pins 17 and 23) or

(Pin 12) inside the IC.

CXD2053AM/AS

ISET

VSIN

Sync separation system analog power supply.
Connect a low-noise power supply from the
digital system.

Sync separation system analog ground.
Connect to the same potential as other V

and AV

Bias setting.
Connect to AV

(Pin 9) with 33k

Chip clamp, sync separation input.
Input with capacitor coupled.

Pedestal clamp, ID-1 data slicer input.
Input with capacitor coupled.

Not connected to V

(Pin 20) or AV

(Pin 1) inside the IC.

Not connected to AV

(Pin 3) or V

(Pins 17 and 23) inside the IC.

VDIN

Clamp voltage 1.5V

Clamp voltage
1.5V

Pin
No.

Symbol

Equivalent circuit

Description

CXD2053AM/AS

1. Description of auto wide function

The auto wide function performs wide screen identification from the black bands at the top and bottom of the

screen. As shown below, the CXD2053AM/AS identifies the three types of 4:3 normal video, 16:9 wide video,

and wide video with subtitles.

4:3 normal video

16:9 wide video

Wide video with subtitles

Fig. 1. Wide identification types

The results of this auto wide identification are expressed by 2 bits, and are output through the I

C bus during

bus mode. Also, these results are output directly to the OAW1 (Pin 26) and OAW2 (Pin 27) pins regardless of

bus or bus-free mode.

Auto wide identification is provided with a transition time of about 1 to 15 seconds to prevent misoperation.

During I

C bus mode, wide identification can be changed quickly without this transition time by manipulating

the INST bit.

2. Description of ID-1 (transmitter method of additional video information, aspect ratio identification)

As shown in the table below, the additional video information consists of 14-bit data, to which a 6-bit CRCC is

appended for a total of 20 bits. On an NTSC video signal, this information is carried on lines 20 and 283 of the

vertical blanking interval.

bit-No

WORD0

WORD1
WORD2

Description

"1"

"0"

1
2
3

Transmitter aspect ratio
Pictorial representation format
Undefined

Full mode (16:9)

Letter-box

4:3

Normal

Discrimination information about the video signal and any other signal (audio
signal, etc.) incident to the video and transmitted simultaneously.

Word 0 dependent discrimination signal
Word 0 dependent discrimination signal, information, etc.

4
5
6

4-bit width
4-bit width

(From the Provisional Standard of EIAJ, CPX-1204)

Table 1. Description of ID-1 signal

Of the 14-bit data noted above, only the first 2 bits are handled by the CXD2053AM/AS. These 2 bits are

obtained by the I

C bus during bus mode. Also, these bits are output directly to the OLBX (Pin 24) and O164

(Pin 25) regardless of bus or bus-free mode.

CXD2053AM/AS

3. Description of EDTV-

As shown in the table below, EDTV-

ID consists of 27-bit data. On an NTSC video signal, this information is

carried on lines 22 and 285 of the vertical blanking interval.

Bit
No.

1
2
3
4
5
6
7
8
9

10
11
12
13
14

Reference signal
Reference signal
Letter-box
Parity of bits 3 and 5
Undefined
Field No.
Multiphase
VT
VH
HH
HH precombing
Broadcasting station operation bit
Broadcasting station operation bit
Broadcasting station operation bit

Full line

0
0
1

No
No
No
No

Letter-box

Yes
Yes
Yes
Yes

15
16
17
18
19
20
21
22
23
24
25
26
27

Undefined
Undefined
Undefined
Error correction signal
Error correction signal
Error correction signal
Error correction signal
Error correction signal
Error correction signal
0
Confirmation sine wave
Confirmation sine wave
Confirmation sine wave

--
--
--

Description

Bit
No.

Description

Table 2. Description of EDTV-

ID (discrimination control signal) signal

Of the 27 bits noted above, the CXD2053AM/AS outputs only bits 3 and 5. These 2 bits are obtained by the I

bus during bus mode. Also, bit 3 only is output directly to the OED (Pin 28) regardless of bus or bus-free mode.

Since the CXD2053AM/AS does not perform decode processing for bits 6 to 23, this results in simple

identification which does not use the error correction signals.

4. Clock

The CXD2053AM/AS requires a 4fsc clock (14.318MHz). Connect XI (Pin 22) and XO (Pin 21) when using a

crystal oscillator.

When inputting the clock from an external source, input to XI (Pin 22).

Clock is 14.318MHz regardless of switching auto wide 525/60 (NTSC) or 625/50 (PAL, SECAM).

5. Settings and data input/output

The CXD2053AM/AS settings and data input/output can be performed by direct setting by pins or with the I

bus interface.

CXD2053AM/AS

5-1. I

C bus

Settings and data can be taken out via the I

C bus when MCON (Pin 19) is set to "1".

This LSI supports the I

C bus slave RECEIVER and slave TRANSMITTER modes. The slave address is 1C (H).

Also, in addition to standard mode (Max. 100K bit/s), this LSI also supports high-speed mode (Max. 400K bit/s).

Even when the IC power supply falls to 0V, it does not occupy the bus. However, the Absolute Maximum

Ratings should be strictly observed.

The I

C bus transfer sequence is shown in the figure below.

The amount of data transferred by this IC is 2 bytes for the write (RECEIVER) side and 1 byte for the readout

(TRANSMITTER) side.

Data write (RECEIVER mode)

SLAm

7654321

76543210

DATAm

SLAm

7654321

76543210

DATAs

XAm

Data readout (TRANSMITTER mode)

Symbol

SLA

DATA

from master to slave

from slave to master

Start Condition

Stop Condition

Slave Address

Data

0: Write

Master

Slave

1: Read

Slave

Master

Clock pulse for Acknowledgement (SDA: L)

Acknowledgement none (SDA: H)

Description

CXD2053AM/AS

Table 3. List of I

C bus controls

R/W

Bit

bit 7 MSB

bit 6

bit 5
bit 4

bit 3
bit 2

bit 1

bit 0

LSB

bit 7 MSB

bit 6

bit 5
bit 4
bit 3
bit 2

bit 1

bit 0

LSB

bit 7 MSB

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LSB

ED2FSC

ED2RES

EDDEC1

EDDEC2

VBLNJ1

VBRES

AWRES

INST

No Use
and TEST

UPAREA

PAL

ED2ID

EDVLD

VBID

VBVLD

AWS

0 when checking the 3.58MHz amplitude during EDTV-

decoding; 1 when not checking the amplitude.

EDTV-

ID decoding function reset. 1 = reset.

EDTV-

ID decoding function detection switching.

Standard values: bit 5 = 0, bit 4 = 1.

EDTV-

ID decoding function detection switching.

Standard values: bit 3 = 0, bit 2 = 1.

Decoding not only of line 20 but also of the 1 line before and after line
20 by the ID-1 decoding function. 0 = yes, 1 = line 20 only.

ID-1 decoding function reset. 1 = reset.

Auto wide function reset. 1 = reset to 4:3.

Auto wide switching is performed without the wait time by changing
INST from 0 to 1.

Not used and LSI test bits. Be sure to set all bits to 0.

Normally. Set the same value as that of PAL bit below.
When PAL = 0, UPAREA = 0, etc.

Auto wide function switching.
525/60 when PAL = 0 and 625/50 when PAL = 1.

EDTV-

ID decoding results. 3rd bit of the EDTV-

ID.

EDTV-

ID decoding results. 5th bit of the EDTV-

ID.

EDTV-

ID decoding results judgment. Becomes 1 when a valid

EDTV-

ID exists. The above noted ED2ID is output and held

regardless of this judgment.

ID-1 decoding results. 1st bit: full mode bit.

ID-1 decoding results. 2nd bit: letter-box bit.

VB-ID decoding results judgment. Becomes 1 when a valid VB-ID
exists. The above noted VB-ID is output and held regardless of this
judgment.

Auto wide identification results.
For 4:3 video, bit 1 = 0 and bit 0 = 0.
For 16:9 wide video, bit 1 = 0 and bit 0 = 1.
For subtitle video, bit 1 = 1 and bit 0 = 0.

Name

Description

1st byte

2nd byte

1st byte

CXD2053AM/AS

5-2. Bus-free mode

The CXD2053AM/AS can be operated without using the I

C bus when Pin 19 (MCON) is set to 0 and the IC is

switched to bus-free mode.

In this case, the contents normally set by the I

C are fixed to the values below.

Also, only the two functions listed in the table below can be switched by Pins 15 (SCL) and 16 (SDA).

Bit

bit 7 MSB

bit 6

bit 5
bit 4

bit 3
bit 2

bit 1

bit 0

LSB

bit 7 MSB

bit 6

bit 5
bit 4
bit 3
bit 2

bit 1

bit 0

LSB

ED2FSC

ED2RES

EDDEC1

EDDEC2

VBLNJ1

VBRES

AWRES

INST

No Use
and TEST

UPAREA

PAL

Directly controlled by Pin 16 (SDA).
The unmodified SDA pin level becomes ED2FSC.

ED2RES = 0

bit5 = 0, bit4 = 1.

Directly controlled by Pin 15 (SCL).
When SCL = 0, bit 3 = 0 and bit 2 = 1. When SCL = 1, bit 3 = 1 and bit 2 = 0.

VBLNJ1 = 0

VBRES = 0

AWRES = 0

INST = 0

All 0

UPAREA = 0

PAL = 0 Fixed to 525/60 mode.

Name

Description

1st byte

2nd byte

C setting information

Table 4. Setting values during bus-free mode (Pin 19 (MCON) = 0)

CXD2053AM/AS

6. Processing of EDTV-

ID and ID-1 data from the bus

EDTV-

or ID-1

EDVLD or
VBVLD

Decoder

Data validity judgment

CXD2053AM/AS

Pin direct output

to microcomputer

As shown in the figure above, the data validity judgment and decoding results are obtained independently

during EDTV-

ID or ID-1 decoding. When outputting these results directly to pins, the results are output after

first taking their logical product (AND). These results are output independently to the I

C bus.

Therefore, processing inside the microcomputer which has acquired the information from the I

C is performed

either by simply outputting this data directly to the pins or by taking the logical product (AND) as above.

In addition, performing the processing when the data validity judgment result (EDVLD or VBVLD) is 1 and the

decoding result is 0 allows video to be judged as 4:3 video. Even video which has had the top and bottom of

the screen blacked out due to picture composition intentions can be viewed as the original 4:3 video by giving

this judgment priority over the auto wide function.

7. Setting EDTV-

ID decoding function

The performance of the EDTV-

ID decoding function can be switched directly by pin settings during either I

bus or bus-free mode.

Setting

C exists

C -free

Resistance to ghosting

Resistance to weak
electric fields

ED2FSC = 0
EDDEC2 bit3 = 0, bit2 = 1

SCL (15pin) = Low
SDA (16pin) = Low

Medium

ED2FSC = 0
EDDEC2 bit3 = 1, bit2 = 0

SCL (15pin) = High
SDA (16pin) = Low

Strong

Medium

ED2FSC = 1
EDDEC2 bit3 = 1, bit2 = 0

SCL (15pin) = High
SDA (15pin) = High

Strong

Table 5. EDTV-

ID decoding function switching

ED2FSC is originally a function which stops the 3.58MHz amplitude check for the Y signal input from the S

terminal, etc. However, it can also be used in combination with the EDDEC2 setting to increase the resistance

to ghosting and weak electric fields as shown in the table above. EDDEC2 is the luminance check level

switching during the 3.58MHz or 2.04MHz confirmation signal interval.

Similarly, although EDDEC1 is the 2.04MHz amplitude check level switching, it should be set to bit 5 = 0 and

bit 4 = 1.

Since EDTV-

ID identification for this IC is simple identification, increasing the resistance to weak electric

fields, etc. results in a tradeoff which increases the possibility of misoperation. Accordingly, the leftmost

settings in the table above should be used as the standard settings, and other settings used only when

necessary.

CXD2053AM/AS

8. Judgment time during auto wide and shortening this time

An appropriate judgment transition wait time is provided during auto wide in order to prevent misjudgments.

During I

C bus mode, this transition time can be shortened as necessary using the INST bit.

At the rising edge of INST, the screen changes without waiting to the screen being judged at that time.

The INST pulse width should be set to 3 fields or more as shown below.

3 fields (50ms) or more

INST

The wait time-free status ends with the auto wide judgment transition or when INST becomes 0. This situation

is illustrated in the figure below.

INST

Wait time-free status

(inside the IC)

Auto wide identification

Transition time wait

INST

Wait time-free status

(inside the IC)

Auto wide identification

No screen change

The screen change here.

INST does not
function.

After transition

Transition time wait

CXD2053AM/AS

Application Circuit

33k

100

0.01µ

60 to 80mA

= 5.0V ±

2.2k

100

10µ

3.3k

10k

100

10µ

1µ

100

1000p

0.1µ

100

100 IRE

0 IRE

40 IRE

0.022µ

470p

Direct output

(open when not used)

22p

14.3MH

ISET

VRT

CPV

VRB

CCP

VSIN

VDIN

ADIN

MCON

XRST

OED

OLBX

O164

OAW2

SDA

TST1

OAW1

SCL

TST2

2.0Vp-p

100

CXD2053AM/AS

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXD2053AM/AS

Package Outline

Unit: mm

CXD2053AM

SONY CODE

EIAJ CODE

JEDEC CODE

SOP-28P-L04

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

42 ALLOY

SOLDER PLATING

EPOXY / PHENOL RESIN

28PIN SOP (PLASTIC) 375mil

18.8 0.1

+ 0.4

0.45 ± 0.1

1.27

9.3

2.3 0.15

+ 0.4

0.1 0.05

+ 0.2

0.5 ±

0.2

0.2 0.05

+ 0.1

7.6 0.1

+ 0.3

10.3 ±

0.4

0.15

± 0.12

SOP028-P-0375-D

0.7g

CXD2053AS

28PIN SDIP (PLASTIC) 400mil

26.9 0.1

+ 0.4

8.5

+ 0.3 0.1

0.25

+ 0.1

0.05

1.778

10.16

0° to 15°

3.7

+ 0.4 0.1

0.5 ± 0.1

0.9 ± 0.15

3.0 MIN

0.5 MIN

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER PLATING

COPPER / 42 ALLOY

SDIP-28P-01

SDIP028-P-0400-A

1.7g

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