Timing Controller for CCD Camera

Description

The CXD2463R generates the sync signals for

timing control and back end signal processing in a

CCD camera system using a 510H or 760H black-

and-white CCD image sensor.

Features

· Built-in sync signal generation function

· Built-in electronic iris (electronic shutter) function

· Supports low-speed limiter for electronic iris

· Supports external synchronization

(Line-Lock, VReset + HPLL)

· Supports automatic external sync discrimination

· Window pulse output for backlight compensation

· Built-in V driver

Applications

· Surveillance camera

· Door phone camera

Structure

Silicon gate CMOS IC

Applicable CCD Image Sensors

· Type 1/2, 760H black-and-white CCD (EIA/CCIR)

· Type 1/3, 510/760H black-and-white CCD (EIA/CCIR)

· Type 1/4, 510/760H black-and-white CCD (EIA/CCIR)

Absolute Maximum Ratings

· Supply voltage

, AV

0.5 to V

+ 7.0

· Supply voltage

VL 0.5 to VL + 26.0

· Supply voltage

VL 0.5 to VL + 26.0

· Supply voltage

VL 0.5 to VL + 26.0

· Input voltage

0.5 to V

+ 0.5

· Output voltage

0.5 to V

+ 0.5

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage 1 V

, AV

4.75 to 5.25

· Supply voltage 3 VH

14.55 to 15.45

· Supply voltage 4 VL

9.0 to 8.0

· Supply voltage 5 VM

· Operating temperature

Topr

20 to +75

°C

Base oscillation

· 1212f

(EIA: 19.0699MHz)

(CCIR: 18.9375MHz)

· 1820f

(EIA: 28.6364MHz)

· 1816f

(CCIR: 28.375MHz)

E98930B9X

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2463R

48 pin LQFP (Plastic)

CXD2463R

NO SIGNAL

DETECTION

CIRCUIT

VD DETECTION

CIRCUIT

SYNC

DISCRIMINA

TION

CIRCUIT

-PLL

SELECT

LCIN

COMP

EVD

EHD/SYNC

EXT

HVDET

EIA

TEST

LCOUT

CKI

CCD

SHP

SHD

SUB

SYNC

CBLK

CLP1

CLP2

BLC

BLCW2

BLCW1

IRIN/ED1

SPDNV/ED2

Vreg

SPUPV/ED0

1/2

1/606

1/910

1/908

TG/SSG

RESET

GEN

IRIS/SHUTTER

CK GEN

COUNTER

ESHUT2

ESHUT1

RST

TEST

CIRCUIT

SELECT

DECODE

UP/DOWN ADDER

IHD

IVD

EIA

1/525

1/625

SYNC

SEP

V DRIVER

DECODER

-PLL

SELECT

Block Diagram

CXD2463R

Pin Configuration (Top View)

IRIN/ED1

BLC

BLCW1

BLCW2

ESHUT2

ESHUT1

TEST

CLP1

CLP2

I
A

/
E

r
e

CKI

LCOUT

LCIN

COMP

EHD/SYNC

EVD

Pin Description

No.

SUB

Vreg

SPUPV/ED0

SPDNV/ED2

IRIN/ED1

Power supply (GND for V driver)

Pulse output for CCD vertical register drive

Power supply (positive power supply for V driver)

Pulse output for CCD vertical register drive

CCD discharge pulse output

Power supply (negative power supply for V driver)

Power supply (for comparator)

Bias current supply for comparator

Shutter speed up reference voltage/shutter speed setting

Shutter speed down reference voltage/shutter speed setting

Iris signal input/shutter speed setting

GND (for comparator)

Symbol

I/O

Description

CXD2463R

No.

BLC

BLCW1

BLCW2

ESHUT2

ESHUT1

TEST

CLP1

CLP2

SYNC

CBLK

EIA

CCD

RST

SHD

SHP

HVDET

EXT

EVD

EHD/SYNC

COMP

LCIN

LCOUT

CKI

Window pulse output for backlight compensation

GND

Window select 1 for backlight compensation (with pull-down resistor)

Window select 2 for backlight compensation (with pull-down resistor)

Power supply

Sub pulse control (with pull-down resistor)

Fixed low (with pull-down resistor)

Clamp pulse output

Composite sync output

Composite blanking output

Low: EIA, High: CCIR (with pull-down resistor)

Low: 510H, High: 760H (with pull-down resistor)

Reset (low reset). Always input reset pulse after power-on.

Data sample-and-hold pulse

Precharge level sample-and-hold pulse

GND

Horizontal PLL/Vertical PLL discrimination signal
High: Vertical PLL, Low: Horizontal PLL

External sync/internal sync discrimination signal
High: External sync, Low: Internal sync

Vertical drive output

Horizontal drive output

Vertical drive signal input (with pull-up resistor)

Horizontal drive signal input/Composite sync input (with pull-up resistor)

Comparator output

Inverter input for oscillation

Inverter output for oscillation

2MCK input

Power supply

Power supply (for H1, H2, and RG)

H1 clock output for CCD horizontal register drive

H2 clock output for CCD horizontal register drive

GND (for H1, H2, and RG)

Reset gate pulse output

Symbol

I/O

Description

CXD2463R

Electrical Characteristics

1) DC Characteristics

= 5V ± 0.25V, Topr = 20 to +75°C)

Item

= 4.0mA

= 8.0mA

= 6.9mA

= 3.0mA

= 17.4mA

= 12.0mA

= 6.0mA

= 4.0mA

= 5.0mA

= 10.0mA

= 7.2mA

= 5.0mA

= 4.0mA

= 5.4mA

= V

or V

= V

or V

= 0V

= V

= 5V

1 = 5V

2 = 5V

= 8.5V

= 15V

4.75

0.7V

0.8V

2.0

0.8

0.25

250k

20k

5.0

50k

1.9

0.8

5.25

0.3V

0.2V

0.4

+ 0.25

2.5M

125k

Symbol

Conditions

Min.

Typ.

Max.

Unit

Supply voltage

Input voltage 1
(For input pins not listed below)

Input voltage 2
(Pin 29)

Input voltage 3
(Pins 11 and 12 in electronic iris
mode)

Input voltage 4
(Pin 13 in electronic iris mode)

Output voltage 1
(Pins 15, 23, 24, 25, 26, 33, 34, 35 and 36)

Output voltage 2
(Pins 30, 31 and 48)

Output voltage 3
(Pins 45 and 46)

Output voltage 4
(Pin 39)

Output voltage 5
(Pins 2, 3, 4 and 6)

Output voltage 6
(Pins 4 and 6 (SG))

Output voltage 7
(Pin 7)

Feedback resistor 1
(Pin 42)

Feedback resistor 2
(Resistor between Pins 40 and 41)

Pull-up resistor

Pull-down resistor

Current consumption

The typical power consumption is 148mW with the ICX054BL load (in the normal operating state).

CXD2463R

2) Input/Output Capacitance

= V

= 0V, f

= 1MHz)

Item

Input pin capacitance

Output pin capacitance

I/O pin capacitance

OUT

I/O

Symbol

Min.

Typ.

Max.

Unit

3) Comparator Characteristics (V

= 5V ± 0.25V, Topr = 20 to +75°C)

Item

Indefinite region

±70

Symbol

Min.

Typ.

Max.

Unit

4) Power-on Reset Condition

(Within the recommended operating condition)

Item

Power-on reset period

WRST

Symbol

Min.

Typ.

Max.

Unit

Note 1) Input offset voltage and indefinite region

The input offset voltage and indefinite region (region in which the comparator output is not set to high

or low) shown in the figure below exist in the built-in comparator in this IC, so be careful when

designing the external circuit.

Note 2) Pins 11 and 12 in electronic iris mode

Make sure of Pin 11 (SPUPV) < Pin 12 (SPDNV).

5.0V

GND

70mV

Pins 11 and 12
(SPUPV, SPDNV)

Indefinite region

4.75V

WRST

0.2V

RST

CXD2463R

1. Electronic Iris/Electronic Shutter Function

The electronic iris or electronic shutter can be selected by setting the following pins to different combinations of

high and low.

ESHUT1

Pin 21

Electronic iris without limiter

Electronic iris with limiter EIA: 1/100 (s), CCIR: 1/120 (s)

Electronic shutter mode

Sub pulse stopped

ESHUT2

Pin 20

Operating Mode

Symbol

IRIN/ED1

SPDNV/ED2

SPUPV/ED0

Iris signal input

Shutter speed down reference voltage

Shutter speed up reference voltage

Pin No.

Function

1) Electronic Iris Mode

Symbol

SPUPV/ED0

IRIN/ED1

SPDNV/ED2

Shutter speed

EIA:

1/100

CCIR:

1/120

1/250

1/500

1/1000

1/2000

1/5000

1/10000

1/100000

Pin No.

Mode

2) Electronic Shutter Mode

CXD2463R

2. Backlighting Correction Function

The CXD2463R has a function to output the window pulse for backlight compensation.

The backlight compensation pulse is output from BLC (Pin 15) in the following range according to the high/low

combination of BLCW1 (Pin 17) and BLCW2 (Pin 18).

Window Type for Different Pin Combinations

Window type

Full-screen photometry

Bottom emphasis photometry

Center emphasis photometry

Bottom + center emphasis photometry

BLCW1 (Pin 17) BLCW2 (Pin 18)

Example of Basic Circuit Configuration

Iris comparator

Iris
window switch

AGC
window switch

IRIN/ED1

BLC

3.9k

10k

39k

+5V

100k

IRIS

OP+

DETOUT

10k

100k

10k

CXD2463R

CXA1310AQ

Full-screen photometry

Center emphasis photometry

Bottom emphasis photometry

Bottom + center emphasis photometry

CXD2463R

3. External Sync Function

The CXD2463R supports the three modes of Line-Lock, VReset + HPLL (VD and HD inputs), and VReset +

HPLL (Sync input) as the external sync functions. Each mode is automatically switched according to the

combination of signals input to EHD/SYNC (Pin 38) and EVD (Pin 37).

1) Automatic External Sync Discrimination

I/O

EHD/SYNC

EVD

HVDET

EXT

No signal

INT

No signal

VReset

+ HPLL

SYNC

HD after SYNC
separation

VReset

+ HPLL

No signal

INT

Symbol

No.

EHD/SYNC and EVD pins signal input state
and HVDET and EXT pins discrimination results

Mode

· If unspecified signals are input for the external signals given above, there may be recognition errors.

2) LL (Line-Lock) Mode

When the V sync clock is externally input to EVD (Pin 37), the result of comparing the falling edge of the clock

and the falling edge of the internal VD is output from COMP (Pin 39). The output polarity is compatible with the

active filter.

EXT-VD
(Pin 37)

INT-VD
(Pin 35)

COMP
(Pin 39)

High impedance state

CXD2463R

3) VReset + HPLL (VD and HD Inputs) Mode

When the HD cycle clock is externally input to EHD/SYNC (Pin 38) and the V cycle clock is externally input to

the EVD (Pin 37), the CXD2463R sync signal is output as shown below based on the phase difference

between these signals.

Similar to Line-Lock mode, the result of comparing the phase of the falling edges of the HD cycle clock input to

Pin 38 and the CXD2463R internal HD is output from COMP (Pin 39). The PLL is applied using this signal.

Similar to Line-Lock mode, the polarity of the COMP (Pin 39) output is compatible with the active filter. The

phase of the HD falling edge can be shifted up to ±1/4H with respect to the falling edge of the master VD (EXT-

VD).

· EIA/ODD

(1) EXT-VD and EXT-HD have the same phase.

1/4H 1/4H

EXT-VD
(Pin 37 input)

EXT-HD
(Pin 38 input)

VD
(Pin 35 output)

HD
(Pin 36 output)

SYNC
(Pin 25 output)

(2) EXT-VD and EXT-HD have the same phase to +1/4H.

EXT-VD

EXT-HD

SYNC

(3) EXT-VD and EXT-HD have the 1/4H to the same phase.

EXT-VD

EXT-HD

SYNC

CXD2463R

4) VReset + HPLL (SYNC Input) Mode

When the specified sync signal is externally input to EHD/SYNC (Pin 38), the EXT-HD separated from this

sync signal is output from HD (Pin 36). This signal is input through the shifter to EVD (Pin 37). At this time, the

CXD2463R sync signal is output as shown below based on the amount by which EXT-HD is shifted. (The

phase can be shifted up to ±1/2H with respect to the falling edge of EXT-HD.)

COMP (Pin 39) outputs the result of comparing the phase of the falling edge of the shifted EXT-HD (signal

input to Pin 37) and the falling edge of the CXD2463R internal HD. The polarity is compatible with the active

filter.

· EIA/ODD

EXT-HD

(Pin 36 output)

(1) Same phase

(2) Delayed phase

EXT-VD

(Generated inside
the CXD2463R)

EXT-SYNC
(Pin 38 input)

SFT-HD (1) to (3) are the signals after shifting EXT-HD.

1/2H 1/2H

(Pin 35 output)

SFT-HD (1)
(Pin 37 input)

SFT-HD (2)

SYNC

(3) Advanced phase

SFT-HD (3)

SYNC

(Pin 25 output)

CXD2463R

I
E

.
O

I
E

.
E

I
E

.
E

I
E

.
O

Timing Generator + Sync Generator Block Timing Chart

Vertical Direction EIA (during 510H/760H CCD drive)

CXD2463R

I
E

.
E

I
E

.
O

.
5

I
E

.
O

I
E

.
E

.
5

Timing Generator + Sync Generator Block Timing Chart

Vertical Direction CCIR (during 510H CCD drive)

CXD2463R

I
E

.
E

I
E

.
O

.
5

I
E

.
O

I
E

.
E

.
5

Timing Generator + Sync Generator Block Timing Chart

Vertical Direction CCIR (during 760H CCD drive)

CXD2463R

/
B

(
I
n

t
e

r
n

l

c

l
o

)

.
8

Timing Generator + Sync Generator Block Timing Chart

Horizontal Direction EIA (during 510H CCD drive)

CXD2463R

/
B

(
I
n

t
e

r
n

l

c

l
o

)

.
6

Timing Generator + Sync Generator Block Timing Chart

Horizontal Direction CCIR (during 510H CCD drive)

CXD2463R

/
B

(
I
n

t
e

r
n

l

c

l
o

)

.
8

Timing Generator + Sync Generator Block Timing Chart

Horizontal Direction EIA (during 760H CCD drive)

CXD2463R

/
B

(
I
n

t
e

r
n

l

c

l
o

)

.
4

Timing Generator + Sync Generator Block Timing Chart

Horizontal Direction CCIR (during 760H CCD drive)

CXD2463R

:

2

.
5

:

2

.
5

(
2

)

:

1

.
5

:

1

.
5

(
1

)

:

1

.
9

:

2

.
0

(
1

)

:

E

I
A

.
8

:

C

I
R

.
6

:

3

.
3

:

3

.
6

(
3

)

(
1

)

:

1

.
2

:

1

.
2

(
3

)

:

0

.
3

:

0

.
3

Timing Generator + Sync Generator Block Timing Chart

Charge Readout Timing

Field Accumulation (during 510H CCD drive)

CXD2463R

:

2

.
5

:

2

.
5

(
3

)

:

2

.
5

:

2

.
5

(
3

)

:

2

.
5

:

2

.
5

(
3

)

:

E

I
A

.
8

:

C

I
R

.
4

:

4

.
5

:

4

.
9

(
5

)

(
2

)

:

1

.
6

:

1

.
6

(
3

)

:

0

.
2

:

0

.
2

Timing Generator + Sync Generator Block Timing Chart

Charge Readout Timing

Field Accumulation (during 760H CCD drive)

CXD2463R

.
7

(
3

)

.
4

(
1

)

/
2

I
A

(
H

)

(
O

)

(
E

)

(
E

)

(
O

)

.
1

(
5

)

.
7

(
4

)

.
3

(
2

)

.
7

(
4

)

.
3

(
2

)

.
4

(
1

)

.
8

.
7

(
4

)

.
9

(
1

)

Timing Generator + Sync Generator Block Timing Chart

Effective Horizontal Period (during 510H CCD drive)

CXD2463R

.
0

(
3

)

.
4

(
1

)

/
2

I
R

(
H

)

(
O

)

(
E

)

(
O

)

(
E

)

.
2

(
5

)

.
7

(
4

)

.
3

(
2

)

.
7

(
4

)

.
3

(
2

)

.
4

(
1

)

.
6

.
7

(
4

)

.
0

(
1

)

Timing Generator + Sync Generator Block Timing Chart

Effective Horizontal Period (during 510H CCD drive)

CXD2463R

.
7

(
4

)

.
5

(
2

)

/
2

I
A

(
H

)

(
O

)

(
E

)

(
E

)

(
O

)

.
2

(
9

)

.
7

(
6

)

.
3

(
3

)

.
7

(
6

)

.
3

(
3

)

.
5

(
2

)

.
8

.
7

(
6

)

.
7

(
1

)

Timing Generator + Sync Generator Block Timing Chart

Effective Horizontal Period (during 760H CCD drive)

CXD2463R

.
0

(
4

)

.
5

(
2

)

/
2

I
R

(
H

)

(
O

)

(
E

)

(
O

)

(
E

)

.
3

(
9

)

.
7

(
6

)

.
4

(
3

)

.
7

(
6

)

.
4

(
3

)

.
5

(
2

)

.
4

.
7

(
6

)

.
9

(
1

)

Timing Generator + Sync Generator Block Timing Chart

Effective Horizontal Period (during 760H CCD drive)

CXD2463R

.
9

I
D

.
0

t
o

.
0

.
5

t
o

.
4

t

c

i
r
c

i
t

i
f
t
e

.
0

I
N

.
1

/
7

l
a

-
a

-
w

i
t
e

Application Circuit

· SYNC input external synchronization

· Electronic iris mode

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same

CXD2463R

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

48PIN LQFP (PLASTIC)

9.0 ± 0.2

7.0 ± 0.1

(0.22)

0.18 0.03

+ 0.08

0.2g

LQFP-48P-L01

LQFP048-P-0707

(
8

.
0

)

.
5

.
2

0.127 0.02

+ 0.05

1.5 0.1

+ 0.2

0.1

SOLDER/PALLADIUM

NOTE: Dimension "

" does not include mold protrusion.

0.1 ± 0.1

.
5

.
2

0° to 10°

DETAIL A

0.13 M

0.5

DETAIL B:SOLDER

(0.18)

(
0

.
1

)

DETAIL B:PALLADIUM

.
1

.
0

0.18 0.03

+ 0.08

.
1

.
0

0.18 ± 0.03

Package Outline

Unit: mm

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2463

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2463