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Электронный компонент: CXP88152

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Description
The CXP88152/88160 is a CMOS 8-bit micro-
computer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, PWM for tuner, VISS/ VASS circuit, 32kHz
timer/counter, remote control receiving circuit,
fluorescent display panel (FDP) controller/driver,
VSYNC separator and the measurement circuit
which measure signals of capstan FG and drum
FG/PG and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
Also, CXP88152/88160 provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
Features
A wide instruction set (213 instructions) which cover various types of data
-- 16-bit arithmetic/multiplication and division/boolean bit operation instructions
Minimum instruction cycle
250ns at 16MHz operation
122s at 32kHz operation
Incorporated ROM capacity
52K bytes (CXP88152)
60K bytes (CXP88160)
Incorporated RAM capacity
1296 bytes (including fluorescent display area)
Peripheral function
-- A/D converter
8 bits, 8 channels, successive approximation system
(Conversion time of 20s/16MHz)
-- Serial interface
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
-- Timer
8-bit timer/counter, 2 channels
19-bit time base timer
32kHz timer/counter
-- High precision timing pattern generation
PPG 8 pins 32-stage programmable circuit
RTG 5 pins, 2 channels
-- PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 4 channels
-- Servo input control
Capstan FG, Drum FG/PG, CTL input
-- VSYNC separator
-- FRC capture unit
Incorporated 26-bit and 8-stage FIFO
-- PWM output
14-bit, 1 channel
-- VISS/VASS circuit
Pulse duty auto detection circuit
-- 32kHz timer/event counter
32kHz oscillation circuit, ultra-low speed instruction mode
-- Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
-- Fluorescent display panel controller/driver Maximum 148-segment display possible
Hardware key scan function (Maximum 16
3 key matrix available)
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
-- Tri-state output
PPG 1 pin, RTG 1 pin, output 8 pins
-- Pseudo HSYNC output function
-- High speed head switching circuit
Interruption
22 factors, 15 vectors, multi-interruption possible
Standby mode
SLEEP/STOP
Package
100-pin plastic QFP
Piggyback/evaluation chip
CXP88100A 100-pin ceramic GFP
Structure
Silicon gate CMOS IC
1
CXP88152/88160
E95324-ST
CMOS 8-bit Single Chip Microcomputer
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
100 pin QFP (Plastic)
2
CXP88152/88160
SO1
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE1
PE2 to PE7
PF0 to PF3
PF4 to PF7
PG0 to PG7
PI1 to PI7
Vss
V
DD
MP
RST
XTAL
EXTAL
CLOCK
GENERATOR/
SYSTEM CONTROL
RAM
1296 BYTES
SPC700
CPU CORE
ROM
52K/60K BYTES
INTERRUPT CONTROLLER
2
2
FIFO
FRC
CAPTURE UNIT
PROGRAMABLE
PATTERN
GENERATOR
RAM
2
5
8
AVss
AV
REF
AV
DD
2
A/D CONVERTER
SERIAL
INTERFACE UNIT
(CH0)
FIFO
8 BIT TIMER/COUNTER 0
V SYNC SEPARATOR
14 BIT PWM GENERATOR
12 BIT PWM GENERATOR CH0
SERVO INPUT
CONTROL
CAPSTAN
DRUM
CTL
2
3
2
12 BIT PWM GENERATOR CH1
4
PWM1
PWM0
PWM
RMC
PBCTL
DPG
DFG
CFG
EXI1
EXI0
SYNC1
SYNC0/EC2
TO/DDO/ADJ
EC0
SCK1
SI1
SCK0
SO0
SI0
CS0
AN0 to AN7
REALTIME
PULSE
GENERATOR
INT2
INT0
8
4
PORT A
PORT B
8
PORT C
8
PORT D
6
2
PORT E
4
4
PORT F
8
PORT G
3
PORT H
7
PORT I
PH0 to PH2
TX
TEX
INT1/NMI
PRESCALER/
TIME BASE TIMER
VISS/VASS
REMOCON INPUT
FIFO
SERIAL INTERFACE UNIT
(CH1)
CH0
CH
1
PPO0 to PPO7
RTO3 to RTO7
8 BIT TIMER/COUNTER1
EC
SELECT
FDP
CONTROLLER
/DRIVER
4
RAM
8
8
8
S0 to S7
T8/S15
to
T15/S8
T0 to T7
V
FDP
PSEUDO HSYNC GENERATOR
HGO
32kHz
TIMER/COUNTER
2
EC1
EC2
ADJ
DAA1
DAB1
DAA0
DAB0
8
Block Diagram
3
CXP88152/88160
Pin Configuration (Top View)
PB0
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2
PC1
PC0
PA7/PPO7
(HAMP) PA6/PPO6
(ROTA) PA5/PPO5
(RF-PLS) PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
HGO/PA0/PPO0
PF7
SI1/PF6
SO1/PF5
SCK1/PF4
PF3/AN7
PF2/AN6
PF1/AN5
PF0/AN4
AN3
AN2
AV
REF
AV
SS
AV
DD
PI6/SO0
PI7/SI0
V
FDP
PD0/S0
PD1/S1
PD2/S2
PD3/S3
PD4/S4
PD5/S5
PD6/S6
PD7/S7
S8/T15
S9/T14
S10/T13
S11/T12
S12/T11
S13/T10
S14/T9
S15/T8
T7
T6
T5
T4
T3
T2
T1
T0
PE0/INT0 (ENV-DET)
PE1/EC0/INT2
PWM0/PE2
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PH0/KR0
PH1/KR1
PH2/KR2
NC
V
DD
V
SS
TX
TEX
PI1/RMC
PI2/PWM
PI3/TO/DDO/ADJ
PI4/INT1/NMI/CS0
PI5/SCK0
AN1
AN0
PG7/EXI1
PG6/EXI0
PG5/SYNC1
PG4/SYNC0/EC2
PG3/PBCTL/EC1
PG2/DPG
MP
RST
V
SS
XTAL
EXTAL
PG1/DFG
PG0/CFG
DAB1/PE7
DAB0/PE6
PE5/DAA1
PE4/DAA0
PE3/PWM1
40
39
38
37
36
35
34
31 32 33
41 42 43 44 45 46 47 48 49 50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
81
82
83
84
88 87 86 85
89
90
100 99 98 97 96 95 94
91
92
93
Note) 1. NC (Pin 90) is always connected to V
DD
.
2. Vss (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) must be connected to GND.
4
CXP88152/88160
Analog input pins to A/D converter. (8 pins)
(Port F)
Lower 4 bits are for
inputs; upper 4 bits are
for I/O. I/O can be set
in a unit of single bits.
(8 pins)
Output/Real time
output/Output
I/O/
Real time output
Output/
Real time output
Output
I/O
I/O/
Real time output
Output
Output/Output
Output/Output
Input/Input
Input/Input/Input
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input
Input/Input
I/O/I/O
I/O/Output
I/O/Input
I/O
(Port A)
PA0 and PA5 to PA7 are
for putputs; PA1 to PA4
are for I/O. I/O can be set
in a unit of single bits.
Data is gated with RTO
content by OR-gate and
they are output.
(8 pins)
8-bit output port. Tri-state can be controlled.
(8 pins)
(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with RTO
content by OR-gate and
they are output. (8 pins)
FDP timing signal output pin. (8 pins)
Output pins for FDP timing signal and segment signal. (8 pins)
(Port D)
8-bit output port.
(8 pins)
(Port E)
8-bit port.
Lower 2 bits are for
inputs; upper 6 bits are for
outputs.
(8 pins)
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
Trigger pulse
input pin for head
switching output.
External event
input pin for
timer/counter.
Input pin to request
external interruption.
Active when falling edge.
Input pin to request
external interruption.
Active when falling edge.
FDP segment signal output pin. (8 pins)
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)
Head switching
output pins.
(2 pins)
Pseudo HSYNC
output pin.
Real-time pulse generator (RTG) output.
Functions as high precision real-time pulse
output port.
(5 pins)
Symbol
I/O
Description
PA0/PPO0/
HGO
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PB0 to PB7
PC0 to PC2
PC3/PPO3
to
PC7/PPO15
T0 to T7
T8/S15
to
T15/S8
PD0/S0
to
PD7/S7
PE0/INT0
PE1/EC0/
INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/SCK1
PF5/SO1
PF6/SI1
PF7
Pin Description
5
CXP88152/88160
PG0/CFG
PG1/DFG
PG2/DPG
PG3/
PBCTL/EC1
PG4/
SYNC0/EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1
PH0/KR0
to
PH2/KR2
PI1/RMC
PI2/PWM
PI3/TO/
DDO/ADJ
PI4/INT1/
NMI/CS0
PI5/SCK0
PI6/SO0
PI7/SI0
EXTAL
XTAL
TEX
TX
RST
MP
V
FDP
AV
DD
AV
REF
AVss
V
DD
Vss
NC
Input/Input
Input/Input
Input/Input
Input/Input/Input
Input/Input/Input
Input/Input
Input/Input
Input/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input/
Input/Input
I/O/I/O
I/O/Output
I/O/Input
Input
Output
Input
Output
Input
Input
Input
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
Playback CTL input pin.
Composite sync signal input pin.
External input pin for FRC capture unit.
Key return input signal for key scanning at FDP
segment signal. (3 pins)
External event
input pin for
timer/counter.
External event
input pin for
timer/counter.
(Port G)
8-bit input port.
(8 pins)
(Port H)
3-bit I/O port.
(3 pins)
Remote control reception circuit input pin.
14-bit PWM output pin.
Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.
Input pin to request external interruption,
non-maskable interruption and for serial chip select
(CH0). Active when falling edge.
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
(Port I)
7-bit I/O port.
I/O can be set
in a unit of
single bits.
(7 pins)
Connecting pin of crystal oscillator for system clock.
When supplying the external clock, input the external clock to EXTAL
pin and input opposite phase clock to XTAL pin.
Connecting pin of crystal oscillator for 32kHz timer clock.
When used as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)
System reset pin of active "L" level.
Test mode pin. Always connect to GND.
FPD voltage supply pin when specifying internal resistor by mask
option.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.
Not connected. Under normal operation, connect to V
DD
.
Symbol
I/O
Description