Description

The CXP88852/88860 is a CMOS 8-bit micro-

computer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, VISS/ VASS circuit, 32kHz timer/counter,
remote control receiving circuit, VSYNC separator
and the measurement circuit which measure signals
of capstan FG amplifier and drum FG/PG amplifier
and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.

Also, CXP88852/88860 provides sleep/stop function

which enables to lower power consumption.

Features
· A wide instruction set (213 instructions) which cover various types of data

-- 16-bit arithmetic/multiplication and division/boolean bit operation instructions

· Minimum instruction cycle

250ns at 16MHz operation
122µs at 32kHz operation

· Incorporated ROM capacity

52K bytes (CXP88852)
60K bytes (CXP88860)

· Incorporated RAM capacity

1600 bytes (including PPG RAM)

· Peripheral function

-- A/D converter

8 bits, 14 channels, successive approximation system
(Conversion time of 20µs/16MHz)

-- Serial interface

Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel

-- Timer

8-bit timer/counter, 2 channels
19-bit time base timer
32kHz timer/counter

-- High precision timing pattern generation

PPG 19 pins 32-stage programmable circuit
RTG 5 pins, 1 channel

5-bit, 8-satge FIFO (RECCTL control), 1channel

-- PWM/DA gate output

12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 2 channels

-- Analog signal input circuit

Capstan FG amplifier circuit
Drum FG amplifier circuit
Drum PG amplifier circuit
PBCTL amplifier circuit

-- CTL write/rewrite circuit

Recording current control circuit

-- Servo input control

Capstan FG, Drum FG/PG, CTL input

-- VSYNC separator
-- FRC capture unit

Incorporated 26-bit and 8-stage FIFO

-- PWM output

14-bit, 1 channel

-- VISS/VASS circuit

Pulse duty auto detection circuit

-- 32kHz timer/event counter

32kHz oscillation circuit, ultra-low speed instruction mode

-- Remote control reception circuit

8-bit pulse measurement counter, 6-stage FIFO

-- Tri-state output

PPG 1 pin, output 8 pins

-- Pseudo HSYNC output function
-- High speed head switching circuit

· Interruption

20 factors, 15 vectors, multi-interruption possible

· Standby mode

SLEEP/STOP

· Package

100-pin plastic QFP

· Piggyback/evaluation chip

CXP88800 100-pin ceramic QFP

CXP88852/88860

E96515-ST

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Structure

Silicon gate CMOS IC

100 pin QFP (Plastic)

CXP88852/88860

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

1600 BYTES

SPC700

CPU CORE

ROM

52K/60K BYTES

INTERRUPT CONTROLLER

FIFO

FRC

CAPTURE UNIT

PROGRAMABLE

PATTERN

GENERATOR

RAM

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

FIFO

8 BIT TIMER/COUNTER 0

V SYNC SEPARATOR

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

GAIN

CONTROL

AMP

12 BIT PWM GENERATOR CH1

REALTIME PULSE

GENERATOR

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT H

PORT I

Vss
V

MP
RST

XTAL

EXTAL

TX
TEX

AVss

REF

INT2

INT0

INT1/NMI

PRESCALER/

TIME BASE TIMER

VISS/VASS

SERIAL INTERFACE UNIT

(CH1)

CH0

CH1

PPO0 to PPO18

RTO3 to RTO7

8 BIT TIMER/COUNTER1

SELECT

PSEUDO HSYNC GENERATOR

32kHz

TIMER/COUNTER

PULSE WIDTH

COUNTER

FIFO

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0, 1, 6, 7

PE2 to PE5

PF0 to PF3

PF4 to PF7

PG0, 1

PI0 to PI7

PH0 to PH7

CTL R/W CONTROL

AMPV

SO1

PWM1

PWM0

PWM

RMC

CTLAMP

DPG

DFG

CFG

EXI1

EXI0

SYNC

SCK1

SI1

SCK0

SO0

SI0

CS0

AN0 to AN13

HGO

DAA1

DAA0

RECCTL

CTLCIN

ADJ

DDO

NMI

REMOCON INPUT

FIFO

Block Diagram

CXP88852/88860

Pin Assignment (Top View)

PH7

31 32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

PE5/EXI1

PE6/PWM0/DAA0

PE7/PWM1/DAA1

CFG

DFG

DPG

VREFOUT

AMPV

CTLSAMPI

CTLFAMPO

CTLAG

CTLAMP (+)

CTLAMP ()

CTLCIN ()

CTLCIN (+)

RECCTL (+)

RECCTL ()

AMPV

RECCAP

AN0/ANOUT

AN1

AN2

AN3

PF0/AN4

PF1/AN5

REF

PF2/AN6

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

XTAL

EXTAL

PG1/AN13

PG0/AN12

PF7/AN11

PF6/AN10

PF5/AN9

PF4/AN8

PF3/AN7

PB5/PPO13

PB4/PPO12

PB3/PPO11

PB2/PPO10

PB1/PPO9

PB0/PPO8

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2/PPO18

PC1/PPO17

PC0/PPO16

PI7

PI6

PI5

PI4

PI3

PI2

PI1/EC/INT2

PI0/INT0

PD7/SI0

PD6/SO0

PD5/SCK0

PD4/CS0

PD3/TO/DDO/ADJ/SRVO

PD2/PWM

PD1/RMC

PD0/INT1/NMI

PB6/PPO14

PB7/PPO15

PA0/PPO0/HGO

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

TEX

PE0/SCK1

PE1/SO1

PE2/SI1

PE3/SYNC

PE4/EXI0

Note) 1. NC (Pin 90) is always connected to V

2. V

(Pins 61 and 89) are both connected to V

3. Vss (Pins 41 and 88) are both connected to GND.

4. MP (Pin 39) must be connected to GND.

CXP88852/88860

Pin Description

(Port A)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
(8 pins)

(Port B)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
Tri-state control is possible.
(8 pins)

(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with PPO or
RT contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. I/O can be
set in a unit of single bits.
(8 pins)

(Port E)
8-bit port. Bits 2, 3, 4 and 5
are for inputs; bits 0, 1, 6
and 7 are for outputs.
(8 pins)

Programmable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.

(19 pins)

PA0 can be tri-state controlled with PPG.

Pseudo HSYNC output pin.

Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)

Input pin to request external interruption
and non-maskable interruption.

Remote control receiving circuit input pin.

14-bit PWM output pin.

Timer/counter, CTL duty detector, 32kHz
oscillation adjustment and servo amplifier
output pin.

Serial chip select (CH0) input pin.

Serial clock (CH0) I/O pin.

Serial data (CH0) output pin.

Serial data (CH0) input pin.

Serial clock (CH1) I/O pin

Serial data (CH1) output pin

Serial data (CH1) input pin

Composite sync signal input pin.

External input pin for FRC capture unit.
(2 pins)

Symbol

I/O

Description

PA0/PPO0
/HGO

PA1/PPO1

PA7/PPO7

PB0/PPO8

PB7/PPO15

PC0/PPO16

PC2/PPO18

PC3/RTO3

PC7/RTO7

PD0/INT1/
NMI

PD1/RMC

PD2/PWM

PD3/TO
DDO/ADJ
SRVO

PD4/CS0

PD5/SCK0

PD6/SO0

PD7/SI0

PE0/SCK1

PE1/SO1

PE2/SI1

PE3/SYNC

PE4/EXI0

PE5/EXI1

PE6/PWM0/
DAA0

PE7/PWM1/
DAA1

PWM output pin.
(2 pins)

DA gate pulse
output pin.
(2 pins)

Output/Real-time
output/Output

Output/
Real-time output

I/O/
Real-time output

I/O/Input/Input

I/O/Input

I/O/Output

I/O/Output/Output/
Output/Output

I/O/Input

I/O/I/O

I/O/Output

I/O/Input

Output/I/O

Output/Output

Input/Input

Output/Output

CXP88852/88860

AN0/ANOUT

AN1 to AN3

PF0/AN4

PF3/AN7

PF4/AN8

PF7/AN11

PG0/AN12
PG1/AN13

PH0 to PH7

PI0/INT0

PI1/EC/
INT2

PI2 to PI7

CFG

DFG

DPG

RECCTL (+)
RECCTL ()

CTLCIN (+)
CTLCIN ()

CTLAMP (+)
CTLAMP ()

CTLFAMPO

CTLSAMPI

RECCAP

VREFOUT

CTLAG

AMPV

Input/Output

Input

Input/Input

Output/Input

Input/Input

Output

I/O/Input

I/O/Input/Input

I/O

Input

I/O

Output

Input

Output

Input

I/O

Output

Description

I/O

Description

(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)

(Port G)
2-bit input port.
(2 pins)

Analog circuit internal
waveform output pin.

(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

(Port I)
8-bit I/O port. I/O can be
set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)

External event input
pin for timer/counter.

Input pin to request external interruption.
Active when falling edge.

Input pin to request
external interruption.
Active when falling
edge.

Capstan FG input pin.

Drum FG input pin.

Drum PG input pin.

RECCTL signal output pin.
(2 pins)

Connected to RECCTL (+) and RECCTL () with the internal switch for
playback. (2 pins)

Input PBCTL signal with capacitor coupled.
(2 pins)

PBCTL signal 1st amplifier output.

PBCTL signal 2nd amplifier input.

Capacitor connecting pin for the slope setting of the CTL writing
trapezoidal wave.

Capacitor connecting pin for the VREF level smoothing of DPG, DFG
and CFG.

Capacitor connecting pin for the CTL and AGND smoothing.

Analog signal input circuit GND pin.

Analog signal input circuit power supply pin.

PBCTL signal input pin.
(2 pins)

Analog input pin for
A/D converter.
(14 pins)

CXP88852/88860

EXTAL

XTAL

TEX

RST

REF

Input

Output

Input

Output

Input

Symbol

I/O

Description

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input it to EXTAL pin and input the opposite phase
clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)

System reset pin; Low level active.

NC pin. Connect this pin to V

for normal operation.

Test mode input pin. Always connect to GND.

Positive power supply pin for A/D converter.

Reference voltage input pin for A/D converter.

GND pin for A/D converter.

Positive power supply pin.

GND pin. Connect both Vss pins to GND.

CXP88852/88860

When reset

Circuit format

Input/Output Circuit Formats for Pins

PPO data

Data bus

Output becomes active from high impedance
by data writing to port.

Port A data

RD (Port A)

Port A

Hi-Z

PA1/PPO1

PA2/PPO2

PA7/PPO7

Port B

6 pins

8 pins

Hi-Z

PB0/PPO8

PB7/PPO15

Port A

Data bus

RD (Port A)

PA0

Data bus

RD (Port A)

PA1

PPO1

PPG control status register bit 0
Tri-state control selection

PPO1

MPX

PPO0

HOUT

HOUTE

HSEL

Output becomes active from high impedance by
data writing to port.

Output becomes active from high impedance by data
writing to port.

Data bus

Port B data

RD (Port B)

Port B tri-state
control

PPO data

PA0/PPO0/
HGO

1 pin

CXP88852/88860

When reset

Circuit format

PPO, RTO data

Data bus

RD (Port C)

Port C direction

Port C data

Input protection circuit

RD (Port C direction)

Port D

8 pins

Hi-Z

PC0/PPO16

PC2/PPO18

PC3/RTO3

PC7/RTO7

PD0/INT1/
NMI
PD1/RMC
PD4/CS0
PD7/SI0

Port D

4 pins

2 pins

Hi-Z

PD2/PWM
PD3/TO/
DDO/ADJ/
SRVO

Port C

MPX

Port D data

Data bus

RD (Port D)

Port D direction

Port D function
select

PD2: 14-bit PWM
PD3: Timer/counter, CTL duty

detection circuit,
32kHz timer,
amplifier circuit

Port D data

Data bus

RD (Port D)

Port D direction

PD1: Remote control circuit
PD0: Interruption circuit
PD4, 7: Serial CH0

Schmitt input

CXP88852/88860

When reset

Circuit format

Data bus

RD (Port E)

SIO CH1

Hi-Z control

MPX

Port E data

Port E function
select

Data bus

RD (Port E)

SIO CH1

Hi-Z control

MPX

Port E data

Port/SCK output
select

SIO CH1

MPX

Port D data

Data bus

RD (Port D)

Port D direction

Port D function
select

MPX

SIO CH0

Note)
PD5 is schmitt input
PD6 is inverter input

Port E

2 pins

Hi-Z

PD5/SCK0
PD6/SO0

PE0/SCK1

Port E

1 pin

4 pins

Hi-Z

PE1/SO1

PE2/SI1
PE3/SYNC
PE4/EXI0
PE5/EXI1

Port D

RD (Port E)

Data bus

Schmitt input

PE2: SIO CH1
PE3
PE4 Servo input
PE5

Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected

with the mask oprion.

CXP88852/88860

Data bus

RD (Port E)

DA gate output or
PWM output

Hi-Z control

MPX

Port E data

Port/DA/PWM
select

4 pins

2 pins

Hi-Z

When reset

PE6/PWM0/
DAA0
PE7/PWM1/
DAA1

PF4/AN8

PF7/AN11

AN0/ANOUT

1 pin

3 pin

AN1

AN3

4 pins

High level

PFO/AN4

PF3/AN7

Port E

Circuit format

Port F data

Data bus

RD (Port F)

Port/AD select

A/D converter

Input multiplexer

From amplifier circuit

Input multiplexer

A/D converter

Analog output control

Input multiplexer

A/D converter

Port E

Port F

RD (Port F)

Data bus

Input multiplexer

A/D converter

Port F

CXP88852/88860

When reset

Circuit format

RD (Port G)

Data bus

Input multiplexer

A/D converter

Port I data

Data bus

RD (Port I)

Port I direction

RD (Port I direction)

Standby release

Data bus

Edge detection

Hi-Z

PG0/AN12

PG1/AN13

2 pins

8 pins

6 pins

Hi-Z

PH0

PH7

Data bus

RD (Port H)

Port H data

Large current 12mA

Medium drive
voltage12 V

Port H

PI0/INT0

PI1/EC/INT2

Port I data

Data bus

RD (Port I)

Port I direction

RD (Port I direction)

Standby release

Interruption circuit

Data bus

Edge detection

2 pins

PI2

PI7

Port I

Port G

Port I

CXP88852/88860

AMPV

RTG control permission

RTO3

From RECCTL () pin

CTLCIN (+) pin

Recording current
control circuit

AMPV

Write current select

RTG control permission

RTO6

RTO7

RTO3

AMPV

1 pin

Hi-Z

Low level

When reset

RECCTL (+)

CTLCIN ()

RECCAP

RECCTL ()

1 pin

Hi-Z

CTLCIN (+)

Circuit format

AMPV

RTG control permission

RTO3

From RECCTL (+) pin

RTG control permission

RTO5

Recording current control circuit

CTLCIN () pin

Recording current
control circuit

AMPV

Write current select

RTG control permission

RTO7

RTO6

RTO3

AMPV

CXP88852/88860

and V

must not exceed +0.3V.

AMPV

and V

must not exceed +0.3V.

and V

OUT

must not exceed V

+0.3V.

The large current output port is port H (PH).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may

adversely affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Medium drive output voltage

High level output current

High level total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

AMPV

OUT

OUTP

OLC

Topr

Tstg

0.3 to +7.0

AVss to +7.0

0.3 to +0.3

AMPV

to +7.0

0.3 to +0.3

0.3 to +7.0

0.3 to +15.0

130

20 to +75

55 to +150

600

°C

Port H

Total of output pins

Other than large current output
ports (value per pin)

Large current output port

(value per pin)

Total of output pins

QFP package type

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V reference)

CXP88852/88860

Analog power supply

High level input voltage

Low level input voltage

Operating temperature

Supply voltage

5.5

+ 0.3

0.3V

0.2V

0.8

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.7

2.5

4.5

0.7V

0.8V

2.2

0.4

0.3

AMPV

IHS

IHTS

IHEX

ILS

ILTS

ILEX

Topr

Guaranteed operation range for 1/2 and 1/4
frequency dividing clock

Guaranteed operation range for 1/16 frequency
dividing clock or during SLEEP mode

Guaranteed operation range by TEX clock

Guaranteed data hold operation range
during STOP

CMOS schmitt input

TTL schmitt input

EXTAL pin

TEX pin

CMOS schmitt input

TTL schmitt input

EXTAL pin

TEX pin

and V

should be set to the same voltage.

AMPV

and V

should be set to the same voltage.

Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PG and PI2 to PI7), MP pin

Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE0/SCK1, PE2/SI1,

PE3/SYNC, PE4/EXI0, PE5/EXI1, PI0/INT0, PI1/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is

selected with mask option.)

PE3/SYNC (when TTL schmitt input is selected with mask option.)

Specifies only during external clock input.

Specifies only during external event input.

Recommended Operating Conditions

(Vss = 0V)

CXP88852/88860

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 12.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 5.5V

High level
output voltage

4.0

3.5

0.5

0.1

1.5

µA

EXTAL

TEX

RST

Item

Symbol

Pins

Conditions

Min.

Clock 1MHz
0V other than the measured pins

DD,

DD1

LOH

DDS1

DD2

DDS2

DDS3

IHE

ILE

IHT

ILT

ILR

Low level
output voltage

Input current

Typ.

0.4

0.6

1.5

400

±10

Max.

Unit

DC Characteristics (V

= 4.5 to 5.5V)

Electrical Characteristics

(Ta = 20 to +75°C, Vss = 0V reference)

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when no resistor is selected.

When entire output pins are open.

When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FE

) to "00" and

operating in high speed mode (1/2 frequency dividing clock).

= 5.5V

SLEEP mode

= 5.5V

= 5V±0.5V

Supply
current

Input capacity

= 5.5V,

= 0.4V

= 5.5V,

= 0, 5.5V

= 5.5V

= 12V

16MHz crystal oscillation (C

= C

= 15pF)

STOP mode
(EXTAL and TEX pins oscillation stop)

I/O leakage
current

Open drain
output leakage
current (N-CH
Tr off state)

PA to PG,
PI, MP,
AN0 to AN3,
RST

2.0

100

µA

= 3.3V

SLEEP mode

= 3V ± 0.3V

32kHz crystal oscillation (C

= C

= 47pF)

PA to PD,
PE0 to PE1,
PE6 to PE7,
PF4 to PF7,
PH (V

only)

PC, PD, PE0,
PE2 to PE5
PF, PG, PI,
RECCTL (+),
RECCTL (),
CTLAMP (+),
CTLAMP (),
CTLSAMPI,
CFG, DFG,
DPG,
EXTAL, TEX

CXP88852/88860

TEX
EC

0.2V

0.8V

Fig. 3. Event count clock timing

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper 2 bits

(CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

XTAL

0.4V

1/fc

External clock

EXTAL

XTAL

74HC04

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

32kHz clock applied condition
Crystal oscillation

TEX

AC Characteristics

(1) Clock timing

System clock frequency

System clock input pulse width

System clock input rise and
fall times

Event count clock input
pulse width

Event count clock input
rise and fall times

System clock frequency

Event count clock input
pulse width

Event count clock input
rise and fall times

XTAL
EXTAL

TEX
TX

TEX

MHz

kHz

µs

Item

Symbol

Condition

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig. 3

= 2.7 to 5.5V

Fig. 2 (32kHz clock
applied condition)

Fig. 3

Typ.

32.768

Min.

sys

200

Max.

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

Fig. 2. Clock applied condition

CXP88852/88860

Input mode

Output mode

Input mode

Output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

CS0

SCK0

delay time

CS0

SCK0

floating delay time

CS0

SO0

delay time

CS0

SO0

floating delay time

CS0
high level width

SCK0
cycle time

SCK0
high and low level widths

SI0 input set-up time
(against SCK0

)

SI0 input hold time
(against SCK0

)

SCK0

SO0 delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 200

16000/fc

sys + 100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

Max.

Unit

Condition

CXP88852/88860

Serial transfer (CH1)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol

Min.

Max.

Condition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input set-up time
(against SCK1

)

SI1 input hold time
(against SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

1000

16000/fc

400

8000/fc 50

100

200

100

200

100

Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer timing (CH1)

SCK1

SI1

SO1

KCY

0.2V

0.8V

SIK

KSI

KSO

Input data

Output data

0.2V

0.8V

0.2V

0.8V

CXP88852/88860

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

Ta = 25°C
V

= AV

REF

= 5.0V

= AVss = 0V

Operation mode

SLEEP mode
STOP mode
32kHz operation mode

Linearity error

Absolute error

Resolution

REF

current

REF

µs

REF

1.0

µA

0.6

160/f

ADC

12/f

ADC

0.5

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Bits

(3) A/D converter characteristics

(Ta = 20 to +75°C, V

= AV

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AVss = 0V reference)

±1

±2

LSB

Analog input

Linearity error

Digital conversion value

Fig. 6. Definitions of A/D converter terms

REF

AN0 to AN7

ADC

indicates the below values due to the contents

of bit 0 (ADCCK) of the ADC operation clock selection

), bits 7 (PCK1) and 6 (PCK0) of

the clock control register (CLC: 00FE

00 (

= f

/2)

01 (

= f

/4)

11 (

= f

/16)

ADC

= fc/2

ADC

= fc/4

ADC

= fc/16

ADC

= fc

ADC

= fc/2

ADC

= fc/8

0 (

/2 selection)

1 (

selection)

PCK1, PCK0

ADCCK

CXP88852/88860

Voltage gain

Offset voltage

Input resistance

Charge switch ON
resistance

RECCTL and
CTLCIN connection
switch ON resistance

CTLCIN 0V fix
switch ON resistance

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

(2) CTL 1st amplifier characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V, CTLAG reference)

Gain = 16dB
RECCTL () = 0V

Gain = 27dB
RECCTL () = 0V

Gain = 42dB
RECCTL () = 0V

Gain = 58dB
RECCTL () = 0V

CTLAMP (+) and CTLAMP ()

= open

Charge switch OFF
CTLAMP (+) = +0.2V

Charge switch OFF
CTLAMP () = +0.2V

Charge switch ON
CTLAMP (+) = +0.5V

Charge switch ON
CTLAMP () = +0.5V

During CTL read operation,
CTLCIN (+) RECCTL (+) = 0.2V

During CTL read operation,
CTLCIN () RECCTL () = 0.2V

During CTL write operation,
CTLCIN (+) = AMPV

+ 0.2V

During CTL write operation,
CTLCIN () = AMPV

+ 0.2V

VCTL1

OSCTL1

INCTL1

CCTL1

READ

WRITE

RECCTL (+)
CTLFAMPO

CTLAMP (+)

CTLAMP ()

CTLAMP (+)

CTLAMP ()

RECCTL (+)
CTLCIN (+)

RECCTL ()
CTLCIN ()

CTLCIN (+)

CTLCIN ()

12.5

23.5

39.0

54.5

26.0

1.20

315

14.5

25.5

41.5

57.0

44.5

2.0

560

400

250

16.5

27.5

44.0

59.5

+40

1010

770

310

When CTLCIN (+), CTLAMP (+) pins and CTLCIN (), CTLAMP () pins are AC coupled, and then the
signal is input from RECCTL (+) pin.

The result after measuring output waveform of CTLFAMPO pin or voltage value.

Note) The gain increases by approximately 1.5dB when the AC coupling capacitor (47µF) is connected to

CTLAMP (+) and CTLAMP () pins, and the signal is input from CTLAMP (+) and CTLAMP () pins.

Reference level
output voltage

Reference level
output current

VREFOUT

CTLAG

VREFOUT

CTLAG

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Analog Circuit Characteristics

(1) Amplifier circuit reference voltage characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V reference)

2.6

2.55

VREFOUT = VREFOUT + 0.5V

VREFOUT = VREFOUT 0.5V

CTLAG = CTLAG + 0.5V

CTLAG = CTLAG 0.5V

2.2

2.15

3.50

0.30

2.80

0.30

2.4

2.35

6.5

0.85

5.5

0.85

CXP88852/88860

Voltage gain

LPF cut-off
frequency

Offset voltage

Comparator level

Input resistance

Charge switch ON
resistance

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

kHz

-p

(3) CTL 2nd amplifier characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V, CTLAG reference)

Gain = 5dB

Gain = 11dB

Gain = 16dB

Gain = 20dB

3dB

CTLSAMPI = open

Comparator level = +100mV

-p

Comparator level = +250mV

-p

Comparator level = +400mV

-p

Comparator level = 100mV

-p

Comparator level = 250mV

-p

Comparator level = 400mV

-p

Charge switch OFF
CTLSAMPI = +0.2V

Charge switch ON
CTLSAMPI = +0.5V

VCTL2

CCTL

OSCTL2

CCTL

INCTL2

CCTL2

CTLSAMPI

4.8

10.4

15.3

19.3

15.0

70.0

215

370

70.0

220

370

10.0

5.8

11.5

16.5

20.5

25.0

100

245

400

100

250

400

18.0

770

6.8

12.6

17.7

21.7

40.0

+50

130

275

430

130

280

430

1140

When the signal is input with the AC coupling capacitor (47µF) connected to CTLSAMPI pin.

The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

Voltage gain

Input amplitude

(peak value)

Input sensitivity

Input dead band

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

-p

(4) CTLAMP characteristics (1st amplifier + 2nd amplifier)

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V reference)

CTL 1st amplifier gain = 16dB
CTL 2nd amplifier gain = 20dB
RECCTL () = 0V

RECCTL () = 0V

CTL 1st amplifier gain = 58dB
CTL 2nd amplifier gain = 20dB
Comparator level = +400mV

-p

400mV

-p

RECCTL () = 0V

VCTL

PKCTL

SCTL

NSCTL

RECCTL (+)

31.8

0.015

35.0

0.08

0.04

38.2

±300

0.10

As for other combinations of the amplifier gains, CTL 1st amplifier and CTL 2nd amplifier are added

respectively.

Note) The result when the signal is input from RECCTL (+) pin with CTL 1st amplifier + CTL 2nd amplifier after

performing AC coupling of CTLCIN (+), CTLAMP (+) pins and CTLCIN (), CTLAMP () pins, and

CTLFAMPO, CTLSAMPI pins.

CXP88852/88860

Voltage gain

LPF cut-off
frequency

Offset voltage

Comparator
judgment level
width

Input sensitivity

Input dead band

Input resistance

Charge switch ON
resistance

Digital output
waveform duty

Input amplitude
(peak value)

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

kHz

mVp-p

-p

(5) CFGAMP characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V, VREFOUT reference)

Gain = 0dB

Gain = 20dB

Gain = 34dB

Gain = 38dB

3dB

CFG = open

Comparator schimitt width

= 320mVp-p

Comparator schimitt width

= 160mVp-p

Gain = 38dB
Comparator level = 320mVp-p

Gain = 38dB
Comparator level = 160mVp-p

Gain = 38dB
Comparator level = 320mVp-p

Gain = 38dB
Comparator level = 160mVp-p

Charge switch OFF
CFG = +0.2V

Charge switch ON
CFG = +0.5V

CFG = sine wave with 50%
duty

VCFG

CCFG

OSCFG

CCFG

SCFG

NSCFG

INCFG

CCFG

TYCFG

PKCFG

CFG

0.3

19.2

33.2

37.0

30.0

260

110

3.40

1.50

5.5

48.0

0.6

20.8

34.8

38.7

55.0

320

155

4.20

2.10

4.10

2.00

8.3

455

50.0

2.2

22.4

36.4

40.4

80.0

+50

360

200

5.00

2.40

710

52.0

±2.4

When the signal is input with the AC coupling capacitor (47µF) connected to CFG pin.

The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

The result after measuring the digital signal waveform output from the amplifier circuit.

CXP88852/88860

Voltage gain

LPF cut-off
frequency

Offset voltage

Comparator
judgment level
width

Input sensitivity

Input dead band

Input resistance

Charge switch ON
resistance

Digital output
waveform duty

Input amplitude
(peak value)

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

kHz

mVp-p

-p

(6) DFGAMP characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V, VREFOUT reference)

Gain = 0dB

Gain = 20dB

Gain = 34dB

Gain = 38dB

3dB

DFG = open

Comparator schmitt width

= 320mVp-p

Comparator schmitt width

= 160mVp-p

Gain = 38dB
Comparator level = 320mVp-p

Gain = 38dB
Comparator level = 160mVp-p

Gain = 38dB
Comparator level = 320mVp-p

Gain = 38dB
Comparator level = 160mVp-p

Charge switch OFF
DFG = +0.2V

Charge switch ON
DFG = +0.5V

CFG = sine wave of 50%
duty

VDFG

CDFG

OSDFG

CDFG

SDFG

NSDFG

INDFG

CDFG

TYDFG

PKDFG

DFG

0.3

19.2

33.2

37.0

30.0

260

110

3.40

1.50

5.5

48.0

0.6

20.8

34.8

38.7

55.0

320

155

4.20

2.10

4.10

2.00

8.3

455

50.0

2.2

22.4

36.4

40.4

80.0

+50

360

200

5.00

2.40

710

52.0

±2.4

When the signal is input with the AC coupling capacitor (47µF) connected to DFG pin.

The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

The result after measuring the digital signal waveform output from the amplifier circuit.

CXP88852/88860

Voltage gain

LPF cut-off
frequency

Offset voltage

Comparator level

Input sensitivity

Input dead band

Input resistance

Charge switch ON
resistance

Input amplitude
(peak value)

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

kHz

-p

(7) DPGAMP characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V, VREFOUT reference)

3dB

DFG = open

Comparator level = 600mV

-p

Comparator level = 400mV

-p

Comparator level = 200mV

-p

Comparator level = 100mV

-p

Comparator level = 600mV

-p

Comparator level = 400mV

-p

Comparator level = 200mV

-p

Comparator level = 100mV

-p

Comparator level
= 600mV

-p, 200mV

-p

Comparator level
= 400mV

-p, 100mV

-p

Comparator level
= 600mV

-p, 200mV

-p

Comparator level
= 400mV

-p, 100mV

-p

Comparator level
= 600mV

-p, 200mV

-p

Comparator level
= 400mV

-p, 100mV

-p

Comparator level
= 600mV

-p, 200mV

-p

Comparator level
= 400mV

-p, 100mV

-p

Charge switch OFF
DPG = +0.2V

Charge switch ON
DPG = +0.5V

VDPG

CDPG

OSDPG

CDPG

SDPG

NSDPG

INDPG

CDPG

PKDPG

DPG

11.1

30.0

570

370

175

572

368

174

113

120

24.0

12.0

55.0

605

400

200

100

605

400

200

100

150

100

155

109

142

150

103

44.5

450

13.2

85.0

+35

640

432

220

125

643

438

223

124

180

120

185

130

860

±2.4

When the signal is input with the AC coupling capacitor (47µF) connected to DPG pin.

The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.

CXP88852/88860

Output resistance

Output current

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

(8) CTL write circuit characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V reference)

RECCAP = AMPV

0.5V

RECCAP = AMPV

+ 0.5V

Write current = 2.0mA

Write current = 2.5mA

Write current = 3.0mA

Write current = 3.5mA

Write current = 4.0mA

Write current = 4.5mA

Write current = 5.0mA

Write current = 5.5mA

Write current = 6.0mA

OREC

RECCAP

RECCTL (+)
RECCTL ()

450

410

1.3

1.7

2.1

2.6

2.9

3.3

3.7

4.0

4.4

625

555

2.0

2.5

3.1

3.6

4.0

4.6

5.1

5.6

6.1

1005

840

2.9

3.7

4.5

5.2

5.9

6.6

7.2

8.0

8.9

The current value which flows when RECCTL (+) pin and RECCTL () pin are shorted.

Amplifier operating
current

AMP

AMPV

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

µA

(9) Amplifier operating current characteristics

(Ta = 20 to +75°C, V

= AMPV

= 5.0V, Vss = AMPV

= 0V reference)

12.0

When the amplifier is operating

When the amplifier is not
operating

7.6

The CTL recording current is added during CTL write.

Note) The amplifier operation and NOT-operation is controlled according to the contents of amplifier power

supply control register (ASWC: 05E2

) bits 5, 4, 1 and 0.

CXP88852/88860

Supplement

Fig. 9. Recommended oscillation circuit

EXTAL

XTAL

(i)

TEX

(ii)

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

Model

HC-49/U03

HC-49/U (-S)

fc (MHz)

8.00

10.00

12.00

8.00

10.00

16.00

16 (12)

16.00

16 (12)

(pF) C

(pF) Rd

(

) Circuit

example

(i)

470k

(ii)

Mask option table

12.00

32.768kHz

The input circuit format can be selected for PE3/SYNC pin.

Item

Content

Reset pin pull-up resistor

Input circuit format

Non-existent

CMOS schmitt

Existent

TTL schmitt

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP88852

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP88852