CMOS 16-bit Single Chip Microcomputer

Description

The CXP972032/973032/973064 is a CMOS 16-bit

microcomputer integrating on a single chip an A/D
converter, serial interface, I

C bus interface, timer,

PWM output circuit, programmable pattern
generator, remote control receive circuit, parallel
interface, as well as basic configurations like a 16-bit
CPU, ROM, RAM, and I/O port.

This LSI also provides the sleep/stop functions that

enable lower power consumption.

Features
· An efficient instruction set as a controller

-- Direct addressing, numerous abbreviated forms,

multiplication and division instructions

· Instruction sets for C language and RTOS

-- Highly quadratic instruction system,

general-purpose register of 16-bit

8-pin

16-bank

configuration

· Minimum instruction cycle

50ns at 40MHz operation (2.7 to 3.6V)

· Incorporated ROM capacity

128K bytes (CXP972032/973032)
256K bytes (CXP973064)

· Incorporated RAM capacity

7.5K bytes (CXP972032)
11.5K bytes (CXP973032/973064)

· Peripheral functions

-- A/D converter

8-bit 12-analog input, successive approximation system,
3-stage FIFO (Conversion time: 1.55µs at 40MHz)

-- Serial interface

Asynchronous serial interface (UART)
128-byte buffer RAM, 3 channels

-- I

C bus interface

64-byte buffer RAM
(supports master/slave and automatic transfer mode)

-- Timers

8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output)
16-bit timer, 4 channels, watchdog timer

-- PWM output circuit

14-bit PWM, 4 channels
(2 channels of binary output switch function by PPG)

-- Programmable pattern generator

16-bit output, 64-byte buffer RAM, 1 channel

-- Remote control receive circuit

8-bit pulse measurement counter, 10-stage FIFO

-- Parallel interface

External register interface (8-bit parallel bus), 4-chip select

· Interruption

33 factors, 33 vectors, multi-interruption and priority selection possible

· Standby mode

Sleep/stop

· Package

100-pin plastic QFP (CXP972032/973032/973064)
100-pin plastic LQFP (CXP972032/973032/973064)
104-pin plastic LFLGA (CXP973064)

· Piggy/evaluation chip

CXP971000

· FLASH EEPROM incorporated version CXP973F064

Structure

Silicon gate CMOS IC

E99930A14-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP972032/973032/973064

100 pin QFP (Plastic)

100 pin LQFP (Plastic)

104 pin LFLGA (Plastic)

Perchase of Sony's I

C components conveys a licence under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conforms to the I

C Standard Specifications as defined by Philips.

CXP972032/973032/973064

Block Diagram

0 to P

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE7

PF0 to PF5

PF6, PF7

PH0, PH1,

PH6, PH7

PI0 to PI7

PJ0 to PJ7

SCS0

SO0

SI0

SCK0

SI1

SCS1

SCK1

SO1

SCS2

SO2

SI2

SCK2

PWM0

EC0

RMC

PORT

16-BIT

CAPTURE

TIMER/COUNTER (CH2)

BUFFER

RAM

C BUS

INTERF

UNIT

BUFFER

RAM

SERIAL

INTERF

UNIT

(CH2)

BUFFER

RAM

SERIAL

INTERF

UNIT

(CH1)

BUFFER

RAM

SERIAL

INTERF

UNIT

(CH0)

PORT

PG4 to PG7

PH2 to PH5

PORT

PG0 to PG3

PORT

PK0 to PK4

PK5 to PK6

PORT

SPC970

CPU CORE

CLOCK GENERA

SYSTEM CONTROLLER

ROM

128K/256K

BYTES

RAM

7.5K/1

1.5K

BYTES

PWM1

PWM2

PWM3

PRESCALER/

TIME-BASE TIMER

EC2

CINT

SCL

SDA

TxD

RxD

INT0

to INT7

KS0

to KS19

NMI

RST

EXTAL

XTAL

A/D

CONVER

TER

REMOCON

FIFO

2CH 14-BIT

PWM (PPG)

2CH 14-BIT

PWM

4CH 16-BIT

TIMER

UAR

INTERRUPT CONTROLLER

AN0

to AN11

PPO00

to PPO15

D0 to D7

A0 to A15

ADTEN

ADTRG

XCS3

XCS2

XCS1

XCS0

XRD

XWR

REF

8-BIT

TIMER/COUNTER

(CH0)

8-BIT

TIMER

(CH1)

PROGRAMABLE

TTEERN

GENERA

EXT

.
REGISTERS

INTERF

ACE

BUFFER RAM

FIFO

KEI PRESCALER

CXP972032/973032/973064

Pin Assignment 1 (Top View) 100-pin QFP package

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PE7/INT7/CINT

PF0/EC0

PF1/EC2

PF2/SCS1/NMI

PF3/SI1

PF4/SO1

PF5/SCK1

PF6/T1

PF7/T2

RST

EXT

PG0/PWM0

PG1/PWM1

PG2/PWM2

PG3/PWM3

PG4/SCS0

PG5/SI0

PH0/SDA

PK6

PK5

PK4/ADTRG

PK3/ADTEN

PK2

PK1

PK0

REF

PJ7/AN11/KS11

PJ6/AN10/KS10

PJ5/AN9/KS9

PJ4/AN8/KS8

PJ3/AN7/KS7

PJ2/AN6/KS6

PJ1/AN5/KS5

PJ0/AN4/KS4

PI7/AN3/KS3

PI6/AN2/KS2

PI5/AN1/KS1

PI4/AN0/KS0

Vss

PI3/SCK2

PI2/SO2

PI1/SI2

PI0/SCS2

PG7/SCK0

PG6/SO0

PB2/PPO02/A10

PB3/PPO03/A11

PB4/PPO04/A12

PB5/PPO05/A13

PB6/PPO06/A14

PB7/PPO07/A15

PC0/PPO08

PC1/PPO09

PC2/PPO10

PC3/PPO11

PC4/PPO12/XCS3

PC5/PPO13/XCS2

PC6/PPO14/XCS1

PC7/PPO15/XCS0

PD0/D0/KS12

PD1/D1/KS13

PD2/D2/KS14

PD3/D3/KS15

PD4/D4/KS16

PD5/D5/KS17

PD6/D6/KS18

PD7/D7/KS19

PE0/INT0

PE1/INT1

PE2/INT2

PE3/INT3

PE4/INT4

PE5/INT5

PE6/INT6

PB1/PPO01/A9

PB0/PPO00/A8

A7/A7

A6/A6

A5/A5

A4/A4

A3/A3

A2/A2

A1/A1

A0/A0

PH7/XRD

PH6/XWR

PH5

PH4/RMC

PH3/TxD

PH2/RxD

PH1/SCL

100

Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM

incorporated version.

2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND.
3. V

and AV

(Pins 44, 72 and 89) must be connected to V

CXP972032/973032/973064

Pin Assignment 2 (Top View) 100-pin LQFP package

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PE7/INT7/CINT

PF0/EC0

PF1/EC2

PF2/SCS1/NMI

PF3/SI1

PF4/SO1

PF5/SCK1

PF6/T1

PF7/T2

RST

EXT

PG0/PWM0

PG1/PWM1

PG2/PWM2

PG3/PWM3

PG4/SCS0

PG5/SI0

PH0/SDA

PK6

PK5

PK4/ADTRG

PK3/ADTEN

PK2

PK1

PK0

REF

PJ7/AN11/KS11

PJ6/AN10/KS10

PJ5/AN9/KS9

PJ4/AN8/KS8

PJ3/AN7/KS7

PJ2/AN6/KS6

PJ1/AN5/KS5

PJ0/AN4/KS4

PI7/AN3/KS3

PI6/AN2/KS2

PI5/AN1/KS1

PI4/AN0/KS0

Vss

PI3/SCK2

PI2/SO2

PI1/SI2

PI0/SCS2

PB4/PPO04/A12

PB5/PPO05/A13

PB6/PPO06/A14

PB7/PPO07/A15

PC0/PPO08

PC1/PPO09

PC2/PPO10

PC3/PPO11

PC4/PPO12/XCS3

PC5/PPO13/XCS2

PC6/PPO14/XCS1

PC7/PPO15/XCS0

PD0/D0/KS12

PD1/D1/KS13

PD2/D2/KS14

PD3/D3/KS15

PD4/D4/KS16

PD5/D5/KS17

PD6/D6/KS18

PD7/D7/KS19

PE0/INT0

26 27 28 29

PE1/INT1

PE2/INT2

PE3/INT3

PE4/INT4

PE5/INT5

PE6/INT6

PB1/PPO01/A9

PB2/PPO02/A10

PB3/PPO03/A1

PB0/PPO00/A8

7/A7

6/A6

5/A5

4/A4

3/A3

2/A2

1/A1

0/A0

PH7/XRD

PH6/XWR

PH5

PH4/RMC

PH3/TxD

PH2/RxD

PH1/SCL

100

PG7/SCK0

PG6/SO0

Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM

incorporated version.

2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND.

3. V

and AV

(Pins 42, 70 and 87) must be connected to V

CXP972032/973032/973064

Pin Assignment 3 (Top View) 104-pin LFLGA package

100

PB0

PA6

PA3

PA1

PH6

PH4

PH2

PK6

PB2

PA7

PA4

PA2

PH7

PH3

PK5

PK4

PB5

PB3

PB1

PA5

PA0

PH5

PH1

PH0

PK3

PK1

PC0

PB4

PB6

PK2 AV

REF

PC2

PC1

PB7

PK0 AV

PJ7

PC5

PC4

PC3

PJ6

PJ5

PJ4

PC7

PC6

PJ3

PJ1

PJ2

PD1

PD2

PD0

PI6

PJ0

PI7

PD3

PD4

PD5

PI3

PI4

PI5

PD6

PD7

PE1

PI2

PI0

PE0

PE2

PE6

PF0

PF3

PF6 EXTAL PG3

PG5

PG7

PI1

PE3

PE4

PF2

PF5

RST XTAL

PG0

PG2

PG6

PE5

PE7

PF1

PF4

PF7

PG1

PG4

Note) 1. NC (Pin C7) must be left open. However, use this pin for FLASH EEPROM

incorporated version.

2. Vss and AVss (Pins B7, E12, G2, K13 and N8) must be connected to GND.

3. V

and AV

(Pins A7, D12 and N9) must be connected to V

CXP972032/973032/973064

Pin Functions

Symbol

I/O

Functions

PA0/A0
to PA7/A7

PB0/PPO00/
A8
to PB7/PPO07/
A15

PC0/PPO08
to PC3/PPO11

PC4/PPO12/
XCS3
to PC7/PPO15/
XCS0

PD0/D0/
KS12
to PD7/D7/
KS19

PE0/INT0
to PE6/INT6

PE7/INT7/
CINT

PF0/EC0
PF1/EC2

PF2/SCS1/
NMI

PF3/SI1

PF4/SO1

PF5/SCK1

PF6/T1

PF7/T2

PG0/PWM0
to PG1/PWM1

PG2/PWM2
PG3/PWM3

PG4/SCS0

PG5/SI0

PG6/SO0

PG7/SCK0

Output / Output

Output /
Output / Output

I/O / Output

I/O / Output /
Output

I/O / I/O / Input

I/O / Input

I/O / Input /
Input

Input / Input

Input / Input /
Input

Input / Input

Input / Output

Input / I/O

Output / Output

I/O / Input

I/O / Output

I/O / I/O

(Port A)
8-bit output port.
(8 pins)

(Port B)
8-bit output port. PPO
value and OR output.
(8 pins)

(Port C)
8-bit I/O port. I/O can
be specified in 1-bit
units. PPO value and
OR output.
(8 pins)

(Port D)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)

(Port E)
8-bit I/O port. I/O can
be specified in 1-bit
units. (8 pins)

External register interface address bus port
output data value and OR output.
(8 pins)

Programmable pattern generator outputs.
(16 pins)

External register
interface data bus.
(8 pins)

External interrupt inputs.
(8 pins)

External event inputs for 8-bit timer/counter.
(2 pins)

Serial chip select
(CH1) input.

Serial data (CH1) input.

Serial data (CH1) output.

Serial clock (CH1) I/O.

8-bit timer/counter output.

16-bit capture timer/counter timing output.

14-bit PWM output with output value switch
control by programmable pattern generator.
(2 pins)

14-bit PWM output.
(2 pins)

Serial chip select (CH0) input.

Serial data (CH0) input.

Serial data (CH0) output.

Serial clock (CH0) I/O.

External register interface address bus.
Address width can be extended in 1-bit
units.
(8 pins)

External register interface chip select
signal. Chip select signal output function
can be selected in 1-bit units.
(4 pins)

External capture input for 16-bit capture
timer/counter.

Standby release input
function can be
specified in 1-bit units.
(8 pins)

Non-maskable external
interrupt input.

(Port F)
8-bit port. Lower 6 bits
are for input; upper 2
bits are for output.
(8 pins)

(Port G)
8-bit port. Lower 4 bits
are for output; upper 4
bits are for I/O. Upper
4 bits can be specified
in 1-bit units.
(8 pins)

CXP972032/973032/973064

PH0/SDA

PH1/SCL

PH2/RxD

PH3/TxD

PH4/RMC

PH5

PH6/XWR

PH7/XRD

PI0/SCS2

PI1/SI2

PI2/SO2

PI3/SCK2

PI4/AN0/
KS0
to PI7/AN3/
KS3

PJ0/AN4/
KS4
to PJ7/AN11/
KS11

PK0 to PK2

PK3/ADTEN

PK4/ADTRG

PK5
PK6

EXTAL

XTAL

RST

REF

AVss

Vss

Output / I/O

I/O / Input

I/O / Output

I/O / Input

I/O

Output / Output

I/O / Input

I/O / Output

I/O / I/O

I/O / Input /
Input

I/O

I/O / Input

Output

Input

(Port I)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)

(Port J)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)

(Port K)
7-bit port. Lower 5 bits
are for I/O; upper 2 bits
are for output. Lower
5 bits can be specified
in 1-bit units.
(7 pins)

Connects a crystal for main clock oscillation. (When the clock is supplied
externally, input it to EXTAL and input an opposite phase clock to XTAL.)

System reset. Active at "L" level.

Positive power supply for A/D converter. (Must be the same voltage with
V

)

Reference voltage input for A/D converter. (Must be the same voltage with
V

)

GND for A/D converter.

Positive power supply.
(Connect both V

pins to positive power supply.)

GND. (Connect all four Vss pins to GND.)

NC. (NC is used for FLASH EEPROM incorporated version.)

C bus interface data I/O.

C bus interface clock I/O.

UART reception data input.

UART transmission data output.

Remote control receive circuit input.

External register interface write signal.

External register interface read signal.

Serial chip select (CH2) input.

Serial data (CH2) input.

Serial data (CH2) output.

Serial clock (CH2) I/O.

Analog input for
A/D converter.
(12 pins)

A/D converter operation enable input by external
trigger.

External trigger input for A/D converter.

Standby release input
function can be
specified in 1-bit units.
(12 pins)

Symbol

I/O

Functions

(Port H)
8-bit port. Lower 2 bits
are for large current
N-ch open drain
outputs; medium 4 bits
are for I/O; upper 2 bits
are for output. Medium
4 bits can be specified
in 1-bit units.
(8 pins)

CXP972032/973032/973064

I/O Circuit Format for Pins

Circuit format

After a reset

PA0/A0
to PA7/A7

Hi-Z

PB0/PPO00/A8
to PB7/PPO07/
A15

Hi-Z

PC0/PPO08
to PC3/PPO11

Hi-Z

A0 to A7

PA register

PA register write

(Undefined after a reset)

Reset

Internal
data bus

A8 to A15

PPO00 to PPO07

PB register

PB register write

Address width
setting

(Undefined after a reset)

("0" after a reset)

Reset

Internal
data bus

MPX

PPO08 to PPO11

PC register

Input
protection
circuit

("0" after a reset)

Internal
data bus

PCD register

("0" after a reset)

CXP972032/973032/973064

PC4/PPO12/
XCS3
to PC7/PPO15/
XCS0

Hi-Z

PD0/D0/KS12
to PD7/D7/
KS19

Hi-Z

PE0/INT0
to PE7/INT7/
CINT

Hi-Z

XCS3 to XCS0

PPO12 to PPO15

XCS output setting

MPX

PC register

PCD register

Internal
data bus

("0" after a reset)

PD register

PDD register

External register
I/F

WR (external register area)

Internal data bus

External register operation enable

Standby release

("0" after a reset)

RD (external register area)

External register operation enable

CLR

Large current drive

5mA (V

= 2.7 to 3.6V)

PE register

PED register

Internal data bus

INT0 to INT7/CINT

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

Circuit format

After a reset

CXP972032/973032/973064

PF0/EC0
PF1/EC2

Hi-Z

PF2/SCS1/
NMI

Hi-Z

PF3/SI1

Hi-Z

PF4/SO1

Hi-Z

PF5/SCK1

Hi-Z

Internal data bus

EC0, EC2

CMOS Schmitt input

PFSL register

("0" after a reset)

NMI input enable

("0" after a reset)

Internal data bus

CMOS Schmitt input

SCS1

NMI

PFSL register

("0" after a reset)

Internal data bus

CMOS Schmitt input

SI1

PFSL register

("0" after a reset)

SO1 output enable

SO1

Internal data bus

CMOS Schmitt input

PFSL register

("0" after a reset)

SCK1 output enable

SCK1

Internal data bus

SCK1

Circuit format

After a reset

CXP972032/973032/973064

PF6/T1

"H" level

PF7/T2

"H" level

("H" level at ON
resistance of
pull-up transistor
by a reset.)

PG0/PWM0
to PG3/PWM3

Hi-Z

PFSL register

("1" after a reset)

("0" after a reset)

Internal data bus

MPX

PF register

PF register write

Reset

PFSL register

("1" after a reset)

("0" after a reset)

Internal data bus

MPX

PF register

Pull-up transistor

approximately 150k

= 2.7 to 3.6V)

PG register write

Reset

PWM0 to PWM3

PGSL register

(Undefined after a reset)

("0" after a reset)

Internal data bus

MPX

PG register

Circuit format

After a reset

CXP972032/973032/973064

PG4/SCS0

Hi-Z

PG5/SI0

Hi-Z

PG6/SO0

Hi-Z

PGD register

PGSL register

Internal data bus

SCS0

("0" after a reset)

PG register

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

PGD register

PGSL register

Internal data bus

SI0

("0" after a reset)

PG register

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

PG register

PGSL register

Internal
data bus

(Undefined after a reset)

("0" after a reset)

PGD register

("0" after a reset)

SO0 output enable

SO0

MPX

Circuit format

After a reset

CXP972032/973032/973064

PG7/SCK0

Hi-Z

PH0/SDA
PH1/SCL

Hi-Z

PH2/RxD

Hi-Z

PG register

PGSL register

Internal
data bus

(Undefined after a reset)

("0" after a reset)

PGD register

("0" after a reset)

SCK0 output enable

CMOS Schmitt input

SCK0

MPX

CMOS Schmitt input

PHSL register

Internal data bus

("0" after a reset)

PH register

("1" after a reset)

SDA, SCL

MPX

Large current drive

5mA (V

= 2.7 to 3.6V)

CMOS Schmitt input

PHL register

PHD register

Internal data bus

RxD

(Undefined after a reset)

("0" after a reset)

Circuit format

After a reset

CXP972032/973032/973064

PH3/TxD

Hi-Z

PH4/RMC

Hi-Z

PH5

Hi-Z

PH6/XWR
PH7/XRD

Hi-Z

PH register

Internal
data bus

(Undefined after a reset)

PHD register

("0" after a reset)

TxD output enable

TxD

MPX

CMOS Schmitt input

PH register

PHD register

Internal data bus

RMC

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

PH register

PHD register

Internal data bus

(Undefined after a reset)

("0" after a reset)

XWR, XRD

PH register

PH register write

PHSL register

(Undefined after a reset)

("0" after a reset)

Reset

Internal
data bus

MPX

Circuit format

After a reset

CXP972032/973032/973064

PI0/SCS2

Hi-Z

PI1/SI2

Hi-Z

PI2/SO2

Hi-Z

PID register

PISL register

Internal data bus

SCS2

("0" after a reset)

PI register

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

PID register

PISL register

Internal data bus

SI2

("0" after a reset)

PI register

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

PI register

PISL register

Internal
data bus

(Undefined after a reset)

("0" after a reset)

PID register

("0" after a reset)

SO2 output enable

SO2

MPX

Circuit format

After a reset

CXP972032/973032/973064

PI3/SCK2

Hi-Z

PI4/AN0/KS0
to PI7/AN3/
KS3

Hi-Z

PJ0/AN4/KS4
to PJ7/AN11/
KS11

Hi-Z

PI register

PISL register

Internal data bus

(Undefined after a reset)

("0" after a reset)

PID register

("0" after a reset)

SCK2 output enable

CMOS Schmitt input

SCK2

MPX

PID register

PISL register

Internal data bus

Standby release

A/D converter

("0" after a reset)

PI register

(Undefined after a reset)

("0" after a reset)

Input multiplexer

PJD register

PJSL register

Internal data bus

Standby release

A/D converter

("0" after a reset)

PJ register

(Undefined after a reset)

("0" after a reset)

Input multiplexer

Circuit format

After a reset

CXP972032/973032/973064

PK0 to PK2

Hi-Z

PK3/ADTEN
PK4/ADTRG

Hi-Z

PK5

"H" level

PK6

"H" level

("H" level at ON
resistance of
pull-up transistor
by a reset.)

PK register

PKD register

Internal data bus

(Undefined after a reset)

("0" after a reset)

PK register

PKD register

Internal data bus

ADTEN, ADTRG

(Undefined after a reset)

("0" after a reset)

CMOS Schmitt input

("1" after a reset)

Internal data bus

PK register

PK register write

Reset

("1" after a reset)

Internal data bus

PK register

Pull-up transistor

approximately 150k

= 2.7 to 3.6V)

Circuit format

After a reset

CXP972032/973032/973064

Absolute Maximum Ratings

(Vss = 0V reference)

Item

Supply voltage

Input voltage

Output voltage

High level output current

High level total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

REF

OUT

OLC

Topr

Tstg

0.3 to +4.6

to +4.6

0.3 to +0.3

0.3 to +4.6

5.0

15.0

20.0

130

30 to +85

55 to +150

600

380

500

°C

Output (value per pin)

Total for all output pins

All pins excluding large
current output pins
(value per pin)

Large current output pins

(value per pin)

Total for all output pins

QFP-100P-L01

LQFP-100P-L01

LFLGA-104P-01

Symbol

Rating

Unit

Remarks

and AV

REF

must be the same voltage with V

and V

OUT

excluding PH0 and PH1 must not exceed V

+ 0.3V.

The large current drive transistor is N-ch transistor of PD and PH0, PH1.

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely

affect the reliability of the LSI.

CXP972032/973032/973064

Item

Supply voltage

REF

IHS

IHEX

ILS

ILEX

Topr

High level input
voltage

Low level input
voltage

Symbol

Min.

2.7

2.0

2.7

0.7V

0.8V

0.4

0.3

3.6

+ 0.2

0.2V

0.4

+85

°C

Guaranteed data hold range during stop mode

CMOS Schmitt input

EXTAL

CMOS Schmitt input

EXTAL

Max.

Unit

Remarks

and AV

REF

must be the same voltage with V

PC, PD, PF4, PG6, PH3, PI2, PI4 to PI7, PJ, PK0 to PK2 for normal input port.

RST, PE, PF0 to PF3, PF5, PG4, PG5, PG7, PH0 to PH2, PH4, PH5, PI0, PI1,PI3, PK3 and PK4.

Specified only during self-oscillation.

Recommended Operating Conditions

(Vss = 0V reference)

Operating
temperature

CXP972032/973032/973064

Electrical Characteristics

DC Characteristics 1

(Topr = 30 to +85°C, Vss = 0V reference)

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

= 3.0V, I

= 0.15mA

= 2.7V, I

= 0.15mA

= 3.0V, I

= 0.5mA

= 2.7V, I

= 0.5mA

= 3.0V, I

= 1.5mA

= 2.7V, I

= 1.5mA

= 1.2mA

= 1.6mA

= 2.0mA

= 3.0mA

= 5.0mA

= 3.6V, V

= 3.6V

= 3.6V, V

= 0.3V

= 3.6V, V

= 0.3V

= 3.6V, V

= 0, 3.6V

= 3.6V, V

= 3.6V

IHE

ILE

ILR

LOH

High level
output
voltage

Low level
output
voltage

Input
current

I/O leakage
current

Open drain
output
leakage
current
(N-ch Tr.
off state)

PD to PE, PF6,
PF7, PG0 to PG5,
PH2, PH4, PH5,
PI to PJ,
PK0 to PK6

PA to PC, PF4,
PF5, PG6, PG7,
PH3, PH6, PH7,
PI2, PI3

PE, PF6, PF7,
PG0 to PG5,
PH2, PH4, PH5,
PI0, PI1, PI4 to PI7,
PJ, PK0 to PK6

PA to PC, PF4,
PF5, PG6, PG7,
PH3, PH6, PH7,
PI2, PI3

PD, PH0, PH1

EXTAL

RST

PA to PJ, PK0 to PK6,
RST

PH0, PH1

2.70

2.40

2.30

2.00

2.30

2.00

0.3

0.9

0.30

0.50

0.30

0.50

1.00

250

±31

µA

RST specifies the input current when pull-up resistor has been selected; the leakage current when no

resistor has been selected.

CXP972032/973032/973064

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

= 3.3 ± 0.3V,

= fsrc = 40MHz, External clock operation

A/D off state, PLL off state

= 3.3 ± 0.3V,

= fsrc = 40MHz, External clock operation

A/D off state, PLL off state,
sleep mode

= 3.6V, stop mode

DD1

DDS2

DDS3

Supply
current

, V

8.0

µA

DC Characteristics 2 (CXP972032)

(Topr = 30 to +85°C, Vss = 0V reference)

85°C or less

75°C or less

50°C or less

When all output pins are open.

When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the

LSI is operated in high-speed mode (2 frequency dividing clock).

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

= 3.3 ± 0.3V,

= fsrc = 40MHz, External clock operation

A/D off state, PLL off state

= 3.3 ± 0.3V,

= fsrc = 40MHz, External clock operation

A/D off state, PLL off state,
sleep mode

= 3.6V, stop mode

DD1

DDS2

DDS3

Supply
current

, V

8.8

µA

DC Characteristics 2 (CXP973032/973064)

(Topr = 30 to +85°C, Vss = 0V reference)

85°C or less

75°C or less

50°C or less

When all output pins are open.

When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the

LSI is operated in high-speed mode (2 frequency dividing clock).

CXP972032/973032/973064

AC Characteristics

(1) Clock timing

(Topr = 30 to +85°C, V

= 2.7 to 3.6 V, Vss = 0V reference)

Item

Main clock base
oscillation frequency

Main clock base
oscillation input pulse
width

Main clock base
oscillation input
rise time, fall time

Main clock duty

EXTAL,
XTAL

XTAL

Fig.1, Fig.2
Mask option
Selection less than 40MHz

Fig.1, Fig.2
Mask option
Selection less than 20MHz

= 40.0MHz