Description
The ICX075AL is an interline CCD solid-state
image sensor suitable for CCIR black-and-white
video cameras. Progressive scan allows all pixels
signals to be output independently within
approximately 1/50 second. This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
image without mechanical shutter. Individual pixels
in a square matrix make this device suitable for
image input and processing applications.
High sensitivity and low dark current are achieved
through the adoption of HAD (Hole-Accumulation
Diode) sensors.
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High vertical resolution (580TV-lines) still picture
without mechanical shutter.
Square pixel unit cell
High resolution, high sensitivity, low dark current
Continuous variable-speed shutter
Low smear
Excellent antiblooming characteristics
Reset gate: 5V drive (bias: no adjustment)
Device Structure
Image size:
Diagonal 8mm (Type 1/2)
Number of effective pixels:
782 (H)
582 (V)
approx. 460K pixels
Total number of pixels:
823 (H)
592 (V)
approx. 490K pixels
Interline CCD image sensor
Chip size:
8.10mm (H)
6.33mm (V)
Unit cell size:
8.3m (H)
8.3m (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 38 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 19
Vertical 5
Substrate material:
Silicon
1
ICX075AL
E95309F99
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for CCIR B/W Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
22 pin DIP (Cer-DIP)
Pin 1
V
3
38
2
8
Pin 12
H
Optical black position
(Top View)
2
ICX075AL
Pin No.
Pin No. Symbol
Description
Pin Description
1
DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1F or more.
2
Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIG
1
, HIG
2
, and
POG
.
1
2
3
4
5
6
7
8
9
10
11
V
DD
RG
V
L
SUB
H
1
H
2
HHG
1
HHG
2
HIG
2
POG
VOG
Supply voltage
Reset gate clock
Protective transistor bias
Substrate (overflow drain)
Horizontal register transfer clock
Horizontal register transfer clock
Inter-horizontal register transfer clock
Inter-horizontal register transfer clock
Test pin
2
Test pin
2
Vertical register final stage
transfer clock
Test pin
2
Test pin
2
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register final stage
accumulation clock
GND
Output amplifier 1 gate
1
decoupling capacitor
Signal output 1
Output amplifier 2 gate
1
decoupling capacitor
Signal output 2
Symbol
Description
HIG
1
HIS
V
3
V
2
V
1
VHOLD
GND
C
GG1
V
OUT1
C
GG2
V
OUT2
12
13
14
15
16
17
18
19
20
21
22
Horizontal Register 1
Horizontal Register 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note)
Note) : Photo sensor
V
O
U
T
2
G
N
D
C
G
G
2
C
G
G
1
V
H
O
L
D
V
1
V
2
H
I
G
1
V
D
D
V
O
G
S
U
B
V
L
R
G
P
O
G
H
1
H
2
V
e
r
t
i
c
a
l
R
e
g
i
s
t
e
r
15
16
17
18
19
20
21
22
H
H
G
1
H
H
G
2
H
I
G
2
V
O
U
T
1
V
3
H
I
S
Block Diagram and Pin Configuration
(Top View)
3
ICX075AL
Item
0.3 to +55
0.3 to +18
55 to +10
15 to +20
to +10
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +27.5
0.3 to +22.5
0.3 to +17.5
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit Remarks
Absolute Maximum Ratings
1
+27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Substrate voltage SUB GND
V
DD
, V
OUT1
, V
OUT2
, HIS, C
GG1
, C
GG2
GND
Supply voltage
V
DD
, V
OUT1
, V
OUT2
, HIS, C
GG1
, C
GG2
SUB
V
1
, V
2
, V
3
, VHOLD
,
VOG
GND
Clock input voltage
V
1
, V
2
, V
3
, VHOLD
,
VOG
SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
VOG
H
1
, H
2
GND
H
1
, H
2
SUB
V
L
SUB
V
2
, V
3
, V
DD
, V
OUT1
, V
OUT2
, HIS, HIG
1
, HIG
2
, POG
V
L
RG GND
V
1
, C
GG1
, C
GG2
, H
1
, H
2
, HHG
1
, HHG
2
, VOG
, VHOLD
V
L
Storage temperature
Operating temperature
4
ICX075AL
Integer portion of code
Value
9
10
11 12 13 14 15 16 17
18
9
A
C
d
E
f
G
h
J
K
1
Indications of substrate voltage (V
SUB
) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (V
SUB
) to the indicated voltage.
V
SUB
code two characters indication
Integer portion
Decimal portion
The integer portion of the code and the actual value correspond to each other as follows.
Item
V
DD
V
SUB
V
L
14.55
9.0
Indicated
voltage 0.1
15.45
18.5
Indicated
voltage + 0.1
15.0
Indicated
voltage
2
V
V
V
1
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions
DC Characteristics
<Example> "A5"
V
SUB
= 10.5V
2
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
3
(1) Current to each pin when 18V is applied to V
DD
, V
OUT1
, V
OUT2
, HIS, RG, C
GG1
, C
GG2
, GND and SUB
pins, while pins that are not tested are grounded.
(2) Current to each pin when 20V is applied sequentially to V
1
, V
2
and V
3
pins, while pins that are not
tested are grounded. However, 20V is applied to SUB pin.
(3) Current to each pin when 15V is applied sequentially to RG, H
1
and H
2
pins, while pins that are not
tested are grounded. However, 15V is applied to SUB pin.
(4) Current to V
L
pin when 25V is applied to V
2
, V
3
, POG
, HIG
1
, HIG
2
, V
DD
, V
OUT1
and V
OUT2
pins or
when, 15V is applied to V
1
, VHOLD
, VOG
, C
GG1
, C
GG2
, H
1
, H
2
, HHG
1
and HHG
2
pins, while V
L
pin is grounded. However, GND and SUB pins are left open.
(5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded.
4
Current to SUB pin when 55V is applied to SUB pin, while all pins that are not tested are grounded.
Supply voltage
Substrate voltage
adjustment range
Substrate voltage
adjustment precision
Protective transistor bias
Item
Supply current
Input current
Input current
I
DD
I
IN1
I
IN2
10
1
10
mA
A
A
3
4
Symbol
Min.
Typ.
Max.
Unit
Remarks
5
ICX075AL
Item
V
VT
V
VH02
V
VH1
, V
VH2
, V
VH3
V
VL1
, V
VL2
, V
VL3
V
V
| V
VL1
V
VL3
|
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGH
V
SUB
V
VHOLDH
, V
VOGH
V
VHOLDL
, V
VOGL
V
HHG1H
, V
HHG2H
V
HHG1L
, V
HHG2L
V
HHG1M
, V
HHG2M
14.55
0.05
0.2
8.0
6.8
4.75
0.05
4.5
V
DD
+ 0.4
21.5
0.05
8.0
4.75
8.0
0.05
15.0
0
0
7.5
7.5
5.0
0
5.0
V
DD
+ 0.6
22.5
0
7.5
5.0
7.5
0
15.45
0.05
0.05
7.0
8.05
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
V
DD
+ 0.8
23.5
0.05
7.0
5.25
7.0
0.05
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
6
6
7
7
7
V
VH
= V
VH02
V
VL
= (V
VL01
+ V
VL03
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 3)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01F
capacitance
Low-level coupling
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical final stage
accumulation clock
voltage
/transfer clock voltage
Inter-horizontal register
transfer clock voltage
Symbol
Min. Typ. Max. Unit
Waveform
diagram
Remarks
Clock Voltage Conditions
6
ICX075AL
Clock Equivalent Circuit Constant
Item
C
V1
C
V2
C
V3
C
V12
C
V23
C
V31
C
VHOLD
C
VOG
C
HHG1
C
HHG2
C
H1
C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
R
GND
R
H1
R
H2
820
820
820
3300
2200
2200
19
12
19
19
68
68
47
10
400
22
15
24
24
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer clock and GND
Capacitance between vertical transfer clocks
Capacitance between vertical final stage accumulation
clock and GND
Capacitance between vertical final stage transfer clock
and GND
Capacitance between inter-horizontal register transfer
clock and GND
Capacitance between horizontal transfer clock and
GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Symbol
Min.
Typ.
Max.
Unit Remarks
R
H1
R
H2
H
2
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
3
C
V2
R
GND
R
3
R
1
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
C
V1
C
v
31
C
v
23
H
1
C
V3
7
ICX075AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
M
0V
M
2
V
1
V
VH1
V
VH1
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VLH
V
VLH
V
VL1
V
VL1
V
VL01
V
VL
V
VLL
V
VLL
V
3
V
VH3
V
VH3
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VLH
V
VLH
V
VL3
V
VL03
V
VL
V
VLL
V
VLL
V
V1
= V
VH1
V
VL01
V
V2
= V
VH02
V
VL2
V
V3
= V
VH3
V
VL03
V
VH
= V
VH02
V
VL
= (V
VL01
+ V
VL03
)/2
V
2
V
VLH
V
VL2
V
VLL
V
VLH
V
VL2
V
VL
V
VLL
V
VH
V
VHH
V
VH02
V
VHH
V
VH2
V
VHL
V
VH2
V
VHL
8
ICX075AL
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
10%
twl
V
H
V
HL
(4) Reset gate clock waveform
Point A
twl
V
RG
V
RGH
V
RGL
+ 0.5V
V
RGL
V
RGLH
RG waveform
V
RGLL
H
1
waveform
2.5V
twh
tr
tf
V
RGLH
is the maximum value and V
RGLL
is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, V
RGL
is the average value of V
RGLH
and
V
RGLL
.
V
RGL
= (V
RGLH
+ V
RGLL
)/2
Assuming V
RGH
is the minimum value during the interval twh, then:
V
RG
= V
RGH
V
RGL
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr
twh
tf
M
M
2
V
SUB
9
ICX075AL
(6) Vertical final stage accumulation clock waveform Vertical final stage transfer clock waveform
(7) Inter-horizontal register transfer clock waveform
tf
tr
90%
10%
V
VHOLDL
, V
VOGL
V
VHOLDH
, V
VOGH
VHOLD
, VOG
tf2
tr
10%
V
HHG1L
, V
HHG2L
V
HHG1M
, V
HHG2M
90%
tf1
V
HHG1H
, V
HHG2H
90%
10%
90%
10%
HHG
1
, HHG
2
10
ICX075AL
Readout clock
Vertical transfer
clock
During imaging
During parallel-
serial conversion
Reset gate clock
Substrate clock
Vertical final stage
accumulation/
transfer clock
Inter-horizontal
register transfer clock
V
T
V
1
,
V
2
, V
3
H
1
H
2
H
1
H
2
RG
SUB
VHOLD
VOG
HHG
1
HHG
2
2.3
18
21
11
1.4
2.5
23
26
14
1.6
21
18
26
23
49
0.4
10
10
0.01
0.01
2
20
20
20
20
17.5
15
0.4
15
0.1
10
10
0.01
0.01
2
20
20
20
20
400
17.5
15
0.4
s
ns
ns
s
ns
s
ns
ns
ns
ns
During readout
1
2
During drain
charge
H
o
r
i
z
o
n
t
a
l
t
r
a
n
s
f
e
r
c
l
o
c
k
Item
Symbol
twh
twl
tr
tf, tf1, tf2
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Remarks
Horizontal
transfer clock
H
1
, H
2
20
24
ns
3
Item
Symbol
two
Min. Typ. Max.
Unit
Remarks
1
When vertical transfer clock driver CXD1268M is used.
2
tf
tr 2ns, and the cross-point voltage (V
CR
) for the H
1
rising side of the H
1
and H
2
waveforms must be
at least 2.5V.
3
The overlap period for twh and twl of horizontal transfer clocks H
1
and H
2
is two.
Clock Switching Characteristics
11
ICX075AL
Image Sensor Characteristics
(Ta = 25C)
Item
Sensitivity
Saturation signal
Smear
Video signal shading
Dark signal
Dark signal shading
Lag
Uniformity between output
channels
S
Vsat
Sm
SH
Vdt
Vdt
Lag
V
230
375
300
0.003
0.007
25
2
1
0.5
3
mV
mV
%
%
mV
mV
%
%
1
2
3
4
5
6
7
8
Ta = 60C
Zone 0
Ta = 60C
Ta = 60C
Symbol
Min.
Typ.
Max.
Unit
Measurement method
Remarks
Zone Definition of Video Signal Shading
2
2
582 (V)
6
6
782 (H)
Effective pixel region
Zone 0
Ignored region
Note) All the characteristic data of this image sensor was yielded when the sensor was operated in the 1/50s
interlaced mode.
Measurement System
CCD
C.D.S
S/H
AMP
CCD signal output 1
Signal output 1
Note) Adjust the amplifier gain so that the gain between [
A] and [
C], and between [
B] and [
D] equals 1.
[
A]
[
C]
C.D.S
S/H
AMP
CCD signal output 2
Signal output 2
[
B]
[
D]
12
ICX075AL
Readout modes
The output methods for the two readout modes indicated below are now described.
Odd field
Even field
1/50s interlaced
1/25s non-interlaced
1. 1/50s interlaced
In this mode, the signals are output in a 1/50s period using the two output pins (V
OUT1
, V
OUT2
).
The signals from two adjacent horizontal lines are simultaneously output from the respective output pins.
The lines output from the output pins are changed over with each field. The V
OUT1
signal after it has passed
through the CDS and other external circuits or the signal produced by adding the V
OUT1
and V
OUT2
signals
accommodate interlaced scanning.
2. 1/25s non-interlaced
In this mode, the signals are output in a 1/25s period using only one output pin (V
OUT1
).
Unlike the 1/50s interlaced mode described above, the external circuit can be simplified. The imaging
characteristics also differ from those of the other modes.
V
OUT1
V
OUT2
V
OUT1
V
OUT2
V
OUT1
V
OUT2
13
ICX075AL
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output and the value measured at point [
A] in the
measurement system is used.
3) In the following measurements, this image sensor is operated in 1/50s interlaced mode.
Definition of standard imaging conditions
1) Standard imaging condition
I
:
Use a pattern box (luminance 706cd/m
2
, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR
cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as
the standard sensitivity testing luminous intensity.
2) Standard imaging condition
II
:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is
adjusted to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition
I
. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the
following formula.
S = Vs
[mV]
2. Saturation signal
Set to standard imaging condition
II
. After adjusting the luminous intensity to 10 times the intensity with
average value of signal output, 120mV, measure the minimum value of the signal output.
3. Smear
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of signal output, 120mV. When the readout clock is stopped and
the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum
value VSm [mV] of the signal output and substitute the value into the following formula.
4. Video signal shading
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the signal output is 120mV. Then measure the maximum (Vmax [mV]) and
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.
SH = (Vmax Vmin)/120
100 [%]
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
Sm =
100 [%] (1/10V method conversion value)
120
VSm
500
1
10
1
50
250
14
ICX075AL
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
Vdt = Vdmax Vdmin [mV]
7. Lag
Adjust the signal output value generated by strobe light to 120mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/120)
100 [%]
8. Uniformity between output channels
Set to standard imaging condition
I
. Measure the signals at signal output 1 (V1) and at signal output 2 (V2),
and substitute the values into the following formula.
V =
100 [%]
Vlag (lag)
Signal output 120mV
Light
FLD
SG
Strobe light
timing
Output
V1
| V2 V1 |
15
ICX075AL
2
7
0
k
0
.
1
X
H
2
X
H
1
R
G
1
5
V
7
.
5
V
5
V
X
V
2
X
S
G
X
V
1
X
V
3
X
S
U
B
X
V
H
O
L
D
X
H
H
G
1
-
1
X
H
H
G
1
-
2
X
H
H
G
2
-
1
X
H
H
G
2
-
2
X
V
O
G
1
2
3
4
5
6
7
8
9
1
0
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
C
X
D
1
2
6
8
M
C
X
D
1
2
5
0
1
2
3
4
5
6
7
8
9
1
0
2
0
1
9
1
8
1
6
1
5
1
4
1
3
1
2
1
1
1
7
2
2
/
1
6
V
2
2
/
1
6
V
N
.
C
.
N
.
C
.
N
.
C
.
2
2
/
2
0
V
1
0
/
2
0
V
1
/
3
5
V
2
2
/
1
6
V
2
2
/
1
0
V
2
2
/
1
0
V
3
.
3
/
1
6
V
C
C
D
O
U
T
1
C
C
D
O
U
T
2
[
A
]
1
2
3
4
5
6
7
8
9
1
0
1
1
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
I
C
X
0
7
5
(
B
O
T
T
O
M
V
I
E
W
)
HIG
1
HIS
V
3
V
2
GN
D
C
GG
1
V
OU
T1
C
GG
2
V
OU
T2
VO
G
PO
G
HIG
2
HH
G
2
HH
G
1
H
2
H
1
SU
B
V
L
RG
V
DD
1
/
1
0
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1
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V
2
S
K
5
2
3
1
0
0
3
.
9
k
1
0
0
3
.
9
k
2
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5
2
3
3
.
3
/
2
0
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0
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0
1
1
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1
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0
1
/
2
0
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1
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k
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.
1
5
6
k
1
/
3
5
V
1
/
3
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V
2
7
k
2
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2
7
8
5
3
1
0
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4
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C
0
4
0
.
0
1
V
1
VH
OL
D
0
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1
[
B
]
Drive Circuit
16
ICX075AL
Spectral Sensitivity Characteristics
(includes lens characteristics, excludes light source characteristics)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
500
600
700
800
900
1000
400
Wave Length [nm]
R
e
l
a
t
i
v
e
R
e
s
p
o
n
s
e
Sensor Readout Clock Timing Chart 1/50s interlaced mode
HD
V1
V3
V2
Odd Field
V1
V3
V2
Even Field
43.25
2.58 2.58
3.25
Unit: s
17
ICX075AL
2
4
6
8
1
3
5
7
58
2
58
1
1
3
5
7
2
4
6
8
58
1
58
2
34
0
33
5
33
0
32
9
32
8
32
7
32
6
32
5
32
4
32
3
32
2
32
1
32
0
31
9
31
8
31
7
31
6
31
5
31
4
31
3
31
2
31
1
31
0
30
9
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
62
5
F
L
D
V
D
B
L
K
H
D
V
1
V
2
V
3
C
C
D
O
U
T
1
C
C
D
O
U
T
2
S
G
3
5
7
4
6
8
2
4
6
8
1
3
5
7
1
2
Drive Timing Chart (Vertical Sync) 1/50s interlaced mode
18
ICX075AL
H
D
B
L
K
V
1
V
2
V
3
V
O
G
V
H
O
L
D
H
H
G
1
H
H
G
2
H
1
H
2
R
G
S
H
P
S
H
D
S
U
B
C
L
K
Drive Timing Chart (Horizontal Sync) 1/50s interlaced mode
19
ICX075AL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
Compressive strength
39N
0.9Nm
Upper ceramic
Lower ceramic
29N
Low melting
point glass
29N
Shearing strength
Tensile strength
Torsional strength
20
ICX075AL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not
to perform the following actions as this may cause cracks.
Applying repeated bending stress to the outer leads.
Heating the outer leads for an extended period with a soldering iron.
Rapidly cooling or heating the package.
Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
21
ICX075AL
Package Outline
Unit: mm
P
A
C
K
A
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E
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T
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T
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0
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7
3
11
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0
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.
4
15
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0
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15
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4
9
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2
1
2
1
1
1
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to
9
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2
2
2
-
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0
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1
1
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5
1
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