Publication# 25769

Rev: C Amendment/ 2

Issue Date: September 27, 2004

Refer to AMD's Website (www.amd.com) for the latest information.

Am29DL320G

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations

-- Data can be continuously read from one bank while

executing erase/program functions in another bank

-- Zero latency between read and write operations

Flexible Bank

architecture

-- Read may occur in any of the three banks not being

written or erased.

-- Four banks may be grouped by customer to achieve

desired bank divisions.

256-byte SecSiTM (Secured Silicon) Sector

-- Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data

-- Customer lockable: One time programmable. Once

locked, data cannot be changed.

Zero Power Operation

-- Sophisticated power management circuits reduce

power consumed during inactive periods to nearly
zero

Package options

-- 63-ball FBGA

-- 48-ball FBGA

-- 48-pin TSOP

-- 64-ball Fortified BGA

Top or bottom boot blocks
Manufactured on 0.17 µm process technology
Compatible with JEDEC standards

-- Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS
High performance

-- Access time as fast 70 ns

-- Program time: 4 µs/word typical utilizing Accelerate

function

Ultra low power consumption (typical values)

-- 2 mA active read current at 1 MHz

-- 10 mA active read current at 5 MHz

-- 200 nA in standby or automatic sleep mode

Minimum 1 million write cycles guaranteed per sector
20 year data retention at 125°C

-- Reliable operation for the life of the system

SOFTWARE FEATURES
Data Management Software (DMS)

-- AMD-supplied software manages data programming,

enabling EEPROM emulation

-- Eases historical sector erase flash limitations

Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume

-- Suspends erase operations to allow reading from

other sectors in the same bank

Data# Polling and Toggle Bits

-- Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

-- Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES
Any combination of sectors can be erased
Ready/Busy# output (RY/BY#)

-- Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)

-- Hardware method of resetting the internal state

machine to the read mode

WP#/ACC input pin

-- Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect
status

-- Acceleration (ACC) function accelerates program

timing

Sector protection

-- Hardware method of locking a sector, either

in-system or using programming equipment, to
prevent any program or erase operation within that
sector

-- Temporary Sector Unprotect allows changing data in

protected sectors in-system

For new designs involving TSOP packages, S29JL032H supersedes Am29DL320G and is the factory-recom-
mended migration path. Please refer to the S29JL032H Datasheet for specifications and ordering information.

For new designs involving Fine-pitch BGA (FBGA) packages, S29PL032J supersedes Am29DL320G and is
the factory-recommended migration path. Please refer to the S29PL032J Datasheet for specifications and
ordering information.

Am29DL320G

September 27, 2004

GENERAL DESCRIPTION

The Am29DL320G is a 32 megabit, 3.0 volt-only flash
memory device, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word
mode data appears on DQ15DQ0; byte mode data
appears on DQ7DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V

supply, and can also be programmed in standard
EPROM programmers.

The device is available with an access time of 70, 90,
or 120 ns. The devices are offered in 48-pin TSOP,
48-ball or 63-ball FBGA packages, and 64-ball Forti-
fied BGA. Standard control pins--chip enable (CE#),
write enable (WE#), and output enable (OE#)--control
normal read and write operations, and avoid bus con-
tention issues.

The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.

Simultaneous Read/Write Operations with
Zero Latency

The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into four banks, two 4 Mb banks with small and
large sectors, and two 12 Mb banks of large sectors.
Sector addresses are fixed, system software can be
used to form user-defined bank groups.

During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device allows
a host system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.

The Am29DL320G can be organized as either a top or
bottom boot sector configuration.

Am29DL320G Features

The

SecSi

(Secured Silicon) Sector

is an 256 byte

extra sector capable of being permanently locked by
AMD or customers. The SecSi Indicator Bit (DQ7) is
permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable parts can never be used to replace a
factory locked part. Note that some previous AMD

32 Mbit Am29DL32x devices had a larger SecSi
Sector. Factory locked parts provide several options.
The SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD's ExpressFlash service), or
both.

DMS (Data Management Software) allows systems
to remove EEPROM devices. by simplifying system
software: DMS performs all functions necessary to
modify data in file structures, instead of using sin-
gle-byte modifications. To write or update a particular
piece of data (a phone number or configuration data,
for example), the user only needs to state which piece
of data is to be updated, and where the updated data
is located in the system. This is an advantage com-
pared to systems where user-written software must
keep track of the old data location, status, logical to
physical translation of the data onto the Flash memory
device (or memory devices), and more. Using DMS,
user-written software does not need to interface with
the Flash memory directly. Instead, the user's software
accesses the Flash memory by calling one of only six
functions. AMD provides this software to simplify sys-
tem design and software integration efforts.

The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.

The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.

The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.

The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
Th e system ca n a lso pla ce th e d evice in to th e
standby mode. Power consumption is greatly re-
duced in both modes.

Bank

Megabits

Sector Sizes

Bank 1

4 Mb

Eight 8 Kbyte/4 Kword,

Seven 64 Kbyte/32 Kword

Bank 2

12 Mb

Twenty-four 64 Kbyte/32 Kword

Bank 3

12 Mb

Twenty-four 64 Kbyte/32 Kword

Bank 4

4 Mb

Eight 64 Kbyte/32 Kword

September 27, 2004

Am29DL320G

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6

Special Package Handling Instructions .......................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations ...........................................................10

Word/Byte Configuration .............................................................. 10
Requirements for Reading Array Data .........................................10
Writing Commands/Command Sequences .................................. 11
Accelerated Program Operation ...................................................11
Autoselect Functions .................................................................... 11
Simultaneous Read/Write Operations
with Zero Latency .........................................................................11
Standby Mode .............................................................................. 11
Automatic Sleep Mode .................................................................11
RESET#: Hardware Reset Pin .....................................................12
Output Disable Mode ...................................................................12

Table 2. Top Boot Sector Addresses ...................................................13
Table 3. Top Boot SecSi

Sector Addresses ..................................... 14

Table 4. Bottom Boot Sector Addresses ...............................................15
Table 5. Bottom Boot SecSi

Sector Addresses ................................ 16

Autoselect Mode .......................................................................... 17

Table 6. Autoselect Codes, (High Voltage Method) .............................17

Sector/Sector Block Protection and Unprotection ........................ 18

Table 7. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................18
Table 8. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................18

Write Protect (WP#) .....................................................................19
Temporary Sector Unprotect ........................................................ 19

Figure 1. Temporary Sector Unprotect Operation ................................. 19
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ............................................................ 20

SecSi

(Secured Silicon) Sector

Flash Memory Region .................................................................. 21
Factory Locked: SecSi Sector Programmed and Protected At the
Factory .........................................................................................21
Customer Lockable: SecSi Sector NOT Programmed or Protected At
the Factory ...................................................................................21

Figure 3. SecSi Sector Protect Verify.................................................... 22

Hardware Data Protection ............................................................ 22
Low VCC Write Inhibit .................................................................. 22
Write Pulse "Glitch" Protection .....................................................22
Logical Inhibit ...............................................................................22
Power-Up Write Inhibit .................................................................22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 9. CFI Query Identification String ................................................ 23
Table 10. System Interface String......................................................... 23
Table 11. Device Geometry Definition .................................................. 24
Table 12. Primary Vendor-Specific Extended Query ............................ 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25

Reading Array Data ...................................................................... 25
Reset Command .......................................................................... 25
Autoselect Command Sequence .................................................. 25
Enter SecSi

Sector/Exit SecSi Sector

Command Sequence ...................................................................26

Byte/Word Program Command Sequence ................................... 26
Unlock Bypass Command Sequence ........................................... 26

Figure 4. Program Operation ................................................................ 27

Chip Erase Command Sequence ................................................. 27
Sector Erase Command Sequence .............................................. 27
Erase Suspend/Erase Resume Commands ................................ 28

Figure 5. Erase Operation .................................................................... 28
Table 13. Command Definitions ........................................................... 29

Write Operation Status . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ...................................................................... 30

Figure 6. Data# Polling Algorithm ......................................................... 30

RY/BY#: Ready/Busy# ................................................................. 31
DQ6: Toggle Bit I .......................................................................... 31

Figure 7. Toggle Bit Algorithm .............................................................. 31

DQ2: Toggle Bit II ......................................................................... 32
Reading Toggle Bits DQ6/DQ2 .................................................... 32
DQ5: Exceeded Timing Limits ...................................................... 32
DQ3: Sector Erase Timer ............................................................. 32

Table 14. Write Operation Status ......................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 8. Maximum Negative Overshoot Waveform ............................. 34
Figure 9. Maximum Positive Overshoot Waveform .............................. 34

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents).................................................................... 36
Figure 11. Typical I

CC1

vs. Frequency................................................... 36

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Test Setup .......................................................................... 37
Figure 13. Input Waveforms and Measurement Levels ........................ 37

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. Read Operation Timings...................................................... 38
Figure 15. Reset Timings...................................................................... 39

Word/Byte Configuration (BYTE#) ............................................... 40

Figure 16. BYTE# Timings for Read Operations .................................. 40
Figure 17. BYTE# Timings for Write Operations .................................. 40

Erase and Program Operations ................................................... 41

Figure 18. Program Operation Timings ................................................ 42
Figure 19. Accelerated Program Timing Diagram ................................ 42
Figure 20. Chip/Sector Erase Operation Timings ................................. 43
Figure 21. Back-to-back Read/Write Cycle Timings ............................. 44
Figure 22. Data# Polling Timings (During Embedded Algorithms) ....... 44
Figure 23. Toggle Bit Timings (During Embedded Algorithms) ............ 45
Figure 24. DQ2 vs. DQ6 ....................................................................... 45

Temporary Sector Unprotect ........................................................ 46

Figure 25. Temporary Sector Unprotect Timing Diagram ..................... 46
Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram 47

Alternate CE# Controlled Erase and Program Operations ........... 48

Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 49

Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50
TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51

FBD063--63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm . 51
FBD048--Fine-Pitch Ball Grid Array, 6 x 12 mm ......................... 52
TS 048--Thin Small Outline Package .......................................... 53

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AM29DL320GT70EF