July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29F010B
Data Sheet
Publication Number 22336 Revision
C
Amendment +1 Issue
Date
November 18, 2002
This Data Sheet states AMD's current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22336
Rev: C Amendment/1
Issue Date: November 18, 2002
Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
-- 5.0 V 10% for read, erase, and program operations
-- Simplifies system-level power requirements
Manufactured on 0.32 m process technology
-- Compatible with Am29F010 and Am29F010A
device
High performance
-- 45 ns maximum access time
Low power consumption
-- 12 mA typical active read current
-- 30 mA typical program/erase current
-- <1 A typical standby current
Flexible sector architecture
-- Eight 16 Kbyte sectors
-- Any combination of sectors can be erased
-- Supports full chip erase
Sector protection
-- Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
-- Sector protection/unprotection can be
implemented using standard PROM
programming equipment
Embedded Algorithms
-- Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
-- Embedded Program algorithm automatically
programs and verifies data at specified address
Erase Suspend/Resume
-- Supports reading data from a sector not
being erased
Minimum 1 million erase cycles guaranteed per
sector
20-year data retention at 125
C
-- Reliable operation for the life of the system
Package options
-- 32-pin PLCC
-- 32-pin TSOP
-- 32-pin PDIP
Compatible with JEDEC standards
-- Pinout and software compatible with
single-power-supply flash
-- Superior inadvertent write protection
Data# Polling and Toggle Bits
-- Provides a software method of detecting
program or erase cycle completion
2
Am29F010B
November 18, 2002
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010B
is offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The de-
vice is designed to be programmed in-system with the
standard system 5.0 Volt V
CC
supply. A 12.0 volt V
PP
is not
required for program or erase operations. The device can
also be programmed or erased in standard EPROM
programmers.
This device is manufactured using AMD's 0.32 m pro-
cess technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erase
algorithm--an internal algorithm that automatically pre-
programs the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection measures include a
low V
CC
detector automatically inhibits write operations
during power transitions. The hardware sector protec-
tion feature disa bles both program and erase
operations in any combination of the sectors of memory,
a n d i s i m p l e m e n t e d u s i n g s t a n d a r d E P R O M
programmers.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t le ve l s o f q u a li t y, r e li a b i li t y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
November 18, 2002
Am29F010B
3
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29F010B Device Bus Operations .................................9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Output Disable Mode .............................................................. 10
Table 2. Am29F010B Sector Addresses Table ...............................10
Autoselect Mode ..................................................................... 10
Table 3. Am29F010B Autoselect Codes (High Voltage Method) ....11
Sector Protection/Unprotection ............................................... 11
Hardware Data Protection ...................................................... 11
Low V
CC
Write Inhibit ......................................................................11
Write Pulse "Glitch" Protection ........................................................11
Logical Inhibit ..................................................................................11
Power-Up Write Inhibit ....................................................................11
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data ................................................................ 12
Reset Command ..................................................................... 12
Autoselect Command Sequence ............................................ 12
Byte Program Command Sequence ....................................... 12
Figure 1. Program Operation ..........................................................13
Chip Erase Command Sequence ........................................... 13
Sector Erase Command Sequence ........................................ 13
Erase Suspend/Erase Resume Commands ........................... 14
Figure 2. Erase Operation ...............................................................14
Command Definitions ............................................................. 15
Table 4. Am29F010B Command Definitions ...................................15
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 16
DQ7: Data# Polling ................................................................. 16
Figure 3. Data# Polling Algorithm ...................................................16
DQ6: Toggle Bit I .................................................................... 16
Reading Toggle Bit DQ6 ......................................................... 17
Figure 4. Toggle Bit Algorithm .........................................................17
DQ5: Exceeded Timing Limits ................................................ 17
DQ3: Sector Erase Timer ....................................................... 18
Table 5. Write Operation Status ..................................................... 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 19
Figure 5. Maximum Negative Overshoot Waveform ...................... 19
Figure 6. Maximum Positive Overshoot Waveform ........................ 19
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Test Setup ....................................................................... 22
Table 6. Test Specifications ........................................................... 22
Key to Switching Waveforms . . . . . . . . . . . . . . . 22
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Read Operations Timings ............................................... 23
Erase and Program Operations ......................................................... 24
Figure 9. Program Operation Timings ............................................ 25
Figure 10. Chip/Sector Erase Operation Timings .......................... 25
Figure 11. Data# Polling Timings (During Embedded Algorithms) . 26
Figure 12. Toggle Bit Timings (During Embedded Algorithms) ...... 26
Erase and Program Operations ......................................................... 27
Alternate CE# Controlled Writes .................................................... 27
Figure 13. Alternate CE# Controlled Write Operation Timings ...... 28
Erase and Programming Performance . . . . . . . 28
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 29
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 29
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 30
PD 032--32-Pin Plastic DIP ................................................... 30
PL 032--32-Pin Plastic Leaded Chip Carrier ......................... 31
TS 032--32-Pin Standard Thin Small Outline Package ......... 32
TSR 032--32-Pin Standard Thin Small Outline Package ....... 33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision A (August 12, 1999) ................................................. 34
Revision A+1 (September 22, 1999) ...................................... 34
Revision A+2 (September 27, 1999) ...................................... 34
Revision B (November 12, 1999) ............................................ 34
Revision C (November 28, 2000) ........................................... 34
4
Am29F010B
November 18, 2002
PRODUCT SELECTOR GUIDE
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
Family Part Number
Am29F010B
Speed Option
V
CC
= 5.0 V
5%
-45
V
CC
= 5.0 V
10%
-55 -70
-90
-120
Max Access Time (ns)
45
55
70
90
120
CE# Access (ns)
45
55
70
90
120
OE# Access (ns)
25
30
30
35
50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
CE#
OE#
STB
STB
DQ0
DQ7
Data
Latch
Y-Gating
Cell Matrix
Ad
dres
s Lat
ch
A0A16
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