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AmPDL128G
Data Sheet
Publication Number 25685 Revision
B
Amendment +2 Issue
Date
July 29, 2002
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 25685
Rev: B Amendment/+2
Issue Date: July 29, 2002
Refer to AMD's Website (www.amd.com) for the latest information.
Am29PDL128G
128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous
Read/ Write Flash Memory with VersatileIO
TM
Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
128Mbit Page Mode device
-- Word (16-bit) or double word (32-bit) mode selectable via
WORD# input
-- Page size of 8 words/4 double words: Fast page read access
from random locations within the page
s
Single power supply operation
-- Full Voltage range: 2.7 to 3.6 volt read, erase, and program
operations for battery-powered applications
s
Simultaneous Read/Write Operation
-- Data can be continuously read from one bank while
executing erase/program functions in another bank
-- Zero latency switching from write to read operations
s
FlexBank Architecture
-- 4 separate banks, with up to two simultaneous operations
per device
-- Organized as two 16 Mbit banks (Bank 1 & 4) and two 48
Mbit banks (Bank 2 & 3)
s
VersatileI/O
TM
(V
IO
) Control
-- Output voltage generated and input voltages tolerated on the
device is determined by the voltage on the V
IO
pin
s
SecSi (Secured Silicon) Sector region
-- 128 words (64 double words) accessible through a
command sequence
s
Both top and bottom boot blocks in one device
s
Manufactured on 0.17 m process technology
s
20-year data retention at 125C
s
Minimum 1 million write cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
s
High Performance
-- Page access times as fast as 25 ns
-- Random access times as fast as 70 ns
s
Power consumption (typical values at 10 MHz)
-- 38 mA active read current
-- 17 mA program/erase current
-- 1.5 A typical standby mode current
SOFTWARE FEATURES
s
Software command-set compatible with JEDEC 42.4
standard
-- Backward compatible with Am29F and Am29LV families
s
CFI (Common Flash Interface) complaint
-- Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
s
Erase Suspend / Erase Resume
-- Suspends an erase operation to allow read or program
operations in other sectors of same bank
s
Unlock Bypass Program command
-- Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
s
Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting program or erase
cycle completion
s
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading array data
s
WP# (Write Protect) input
-- At V
IL
, protects the two top and two bottom sectors,
regardless of sector protect/unprotect status
-- At V
IH
, allows removal of sector protection
-- An internal pull up to Vcc is provided
s
Persistent Sector Protection
-- A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
-- Sectors can be locked and unlocked in-system at V
CC
level
s
Password Sector Protection
-- A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
s
ACC (Acceleration) input provides faster programming
times in a factory setting
s
Package options
-- 80-ball Fortified BGA
2
Am29PDL128G
July 29, 2002
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 8 Mwords or 4 M double words (One word is equal
to two bytes). The device is offered in an 80-ball Fortified
BGA package. The word-wide data (x16) appears on
DQ15-DQ0; the double word mode data (x32) appears on
DQ31-DQ0. This device can be programmed in-system or in
standard EPROM programmers. A 12.0 V V
PP
is not re-
quired for write or erase operations.
The device offers fast page access times of 25 and 30 ns,
with corresponding random access times of 70 and 80 ns,
respectively, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with 2 simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations (see
Table 1
).
Page Mode Features
The device is AC timing, input/output, and package compat-
ible with 8 Mbit x16 page mode mask ROM. The page size
is 8 words or 4 double words.
After initial page access is accomplished, the page mode op-
eration provides fast read access speed of random locations
within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V
to 3.6 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combi-
nation of sectors of memory. This can be achieved in-system
or via programming equipment.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD's Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Bank/Sector Sizes
Bank
Number of
Sectors
Sector Size
(Word/Dbl.
Word)
Bank Size
1
8
4/2
16 Mbit
31
32/16
2
96
32/16
48 Mbit
3
96
32/16
48 Mbit
4
8
4/2
16 Mbit
31
32/16
July 29, 2002
Am29PDL128G
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simultaneous Operation Block Diagram . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29PDL128G Device Bus Operations ...........................10
Word/Double Word Configuration........................................... 10
Requirements for Reading Array Data ................................... 10
Random Read (Non-Page Read) ........................................... 10
Page Mode Read .................................................................... 11
Table 2. Page Select, Double Word Mode ......................................11
Table 3. Page Select, Word Mode ..................................................11
Simultaneous Operation ......................................................... 11
Table 4. Bank Select .......................................................................11
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation ............................................. 12
Autoselect Functions .............................................................. 12
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 5. Sector Address Table ........................................................13
Table 6. SecSi
Sector Addresses ................................................20
Autoselect Mode..................................................................... 20
Table 7. Autoselect Codes (High Voltage Method) ........................20
Table 8. Sector Block Addresses for Protection/Unprotection ........21
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 23
Persistent Sector Protection ................................................... 24
Persistent Protection Bit (PPB) ............................................... 24
Persistent Protection Bit Lock (PPB Lock) ............................. 24
Dynamic Protection Bit (DYB) ................................................ 24
Table 9. Sector Protection Schemes ...............................................25
Persistent Sector Protection Mode Locking Bit ...................... 25
Password Protection Mode ..................................................... 25
Password and Password Mode Locking Bit ........................... 25
64-bit Password ...................................................................... 26
Write Protect (WP#) ................................................................ 26
Persistent Protection Bit Lock ................................................. 26
High Voltage Sector Protection .............................................. 26
Figure 1. In-System Sector Protection/
Sector Unprotection Algorithms ...................................................... 27
Temporary Sector Unprotect .................................................. 28
Figure 2. Temporary Sector Unprotect Operation........................... 28
SecSiTM (Secured Silicon) Sector
Flash Memory Region ............................................................ 28
SecSi Sector Protection Bit .................................................... 29
Utilizing Password and SecSi Sector Concurrently ................ 29
Hardware Data Protection ...................................................... 29
Low VCC Write Inhibit ............................................................ 29
Write Pulse "Glitch" Protection ............................................... 29
Logical Inhibit .......................................................................... 29
Power-Up Write Inhibit ............................................................ 29
Common Flash Memory Interface (CFI) . . . . . . . 30
Table 10. CFI Query Identification String ............................ 30
Table 11. System Interface String................................................... 31
Table 12. Device Geometry Definition................................. 32
Table 13. Primary Vendor-Specific Extended Query........... 33
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 34
Reading Array Data ................................................................ 34
Reset Command ..................................................................... 34
Autoselect Command Sequence ............................................ 34
Enter SecSi Sector/Exit SecSi Sector
Command Sequence .............................................................. 34
Double Word/Word Program Command Sequence ................ 35
Unlock Bypass Command Sequence ..................................... 35
Figure 3. Program Operation ......................................................... 36
Chip Erase Command Sequence ........................................... 36
Sector Erase Command Sequence ........................................ 36
Erase Suspend/Erase Resume Commands ........................... 37
Figure 4. Erase Operation.............................................................. 37
Password Program Command ................................................ 37
Password Verify Command .................................................... 38
Password Protection Mode Locking Bit Program Command .. 38
Persistent Sector Protection Mode Locking Bit Program
Command ............................................................................... 38
SecSi Sector Protection Bit Program Command .................... 38
PPB Lock Bit Set Command ................................................... 38
DYB Write Command ............................................................. 39
Password Unlock Command .................................................. 39
PPB Program Command ........................................................ 39
All PPB Erase Command ........................................................ 39
DYB Write Command ............................................................. 39
PPB Lock Bit Set Command ................................................... 40
PPB Lock Bit Status Command .............................................. 40
Sector Protection Status Command ....................................... 40
Command Definitions Tables.................................................. 41
Table 14. Memory Array Command Definitions (x32 Mode) .......... 41
Table 15. Sector Protection Command Definitions (x32 Mode) ..... 42
Table 16. Memory Array Command Definitions (x16 Mode) .......... 43
Table 17. Sector Protection Command Definitions (x16 Mode) ..... 44
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 45
DQ7: Data# Polling ................................................................. 45
Figure 5. Data# Polling Algorithm .................................................. 45
RY/BY#: Ready/Busy#............................................................ 46
DQ6: Toggle Bit I .................................................................... 46
Figure 6. Toggle Bit Algorithm........................................................ 46
DQ2: Toggle Bit II ................................................................... 47
Reading Toggle Bits DQ6/DQ2 ............................................... 47
DQ5: Exceeded Timing Limits ................................................ 47
DQ3: Sector Erase Timer ....................................................... 47
Table 18. Write Operation Status ................................................... 48
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 49
Figure 7. Maximum Negative Overshoot Waveform ...................... 49
Figure 8. Maximum Positive Overshoot Waveform........................ 49
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9. Test Setup...................................................................... 51
Figure 10. Input Waveforms and Measurement Levels ................. 51
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52
Read-Only Operations ........................................................... 52
Figure 11. Read Operation Timings ............................................... 52
Figure 12. Page Read Operation Timings...................................... 53
4
Am29PDL128G
July 29, 2002
P R E L I M I N A R Y
Hardware Reset (RESET#) .................................................... 54
Figure 13. Reset Timings ................................................................ 54
Word/Double Word Configuration (WORD#) .......................... 55
Figure 14. WORD# Timings for Read Operations........................... 55
Figure 15. WORD# Timings for Write Operations........................... 55
Erase and Program Operations .............................................. 56
Figure 16. Program Operation Timings........................................... 57
Figure 17. Accelerated Program Timing Diagram........................... 57
Figure 18. Chip/Sector Erase Operation Timings ........................... 58
Figure 19. Back-to-back Read/Write Cycle Timings ....................... 59
Figure 20. Data# Polling Timings (During Embedded Algorithms).. 59
Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 60
Figure 22. DQ2 vs. DQ6.................................................................. 60
Temporary Sector Unprotect .................................................. 61
Figure 23. Temporary Sector Unprotect Timing Diagram ............... 61
Figure 24. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 62
Alternate CE# Controlled Erase and Program Operations ..... 63
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 64
Erase And Programming Performance. . . . . . . . 65
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 65
TSOP Pin and BGA Package Capacitance . . . . . 65
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67
LAB080--80-Ball Fortified Ball Grid Array
10 x 15 mm package .............................................................. 67
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 68
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