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Am29PDL640G
Data Sheet
Publication Number 26573 Revision
B
Amendment +1 Issue
Date
February 26, 2003
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 26573
Rev: B Amendment/+1
Issue Date: February 26, 2003
Am29PDL640G
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash
Memory with Enhanced VersatileIO
TM
Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
64 Mbit Page Mode device
-- Page size of 8 words: Fast page read access from random
locations within the page
Single power supply operation
-- Full Voltage range: 2.7 to 3.1 volt read, erase, and program
operations for battery-powered applications
Simultaneous Read/Write Operation
-- Data can be continuously read from one bank while
executing erase/program functions in another bank
-- Zero latency switching from write to read operations
FlexBank Architecture
-- 4 separate banks, with up to two simultaneous operations
per device
-- Bank A: 8 Mbit (4 Kw x 8 and 32Kw x 15)
-- Bank B: 24 Mbit (32 Kw x 48)
-- Bank C: 24 Mbit (32 Kw x 48)
-- Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
Enhanced VersatileI/O
TM
(V
IO
) Control
-- Output voltage generated and input voltages tolerated on all
control inputs and I/Os is determined by the voltage on the
V
IO
pin
SecSi
TM
(Secured Silicon) Sector region
-- Up to 128 words accessible through a command sequence
Both top and bottom boot blocks in one device
Manufactured on 0.17 m process technology
20-year data retention at 125C
Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
High Performance
-- Page access times as fast as 25 ns
-- Random access times as fast as 65 ns
Power consumption (typical values at 10 MHz)
-- 25 mA active read current
-- 15 mA program/erase current
-- 0.2 A typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4
standard
-- Backward compatible with Am29F and Am29LV families
CFI (Common Flash Interface) complaint
-- Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Erase Suspend / Erase Resume
-- Suspends an erase operation to allow read or program
operations in other sectors of same bank
Unlock Bypass Program command
-- Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting program or erase
cycle completion
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading array data
WP#/ACC (Write Protect/Accelerate) input
-- At V
IL
, protects the first and last two 4K word sectors,
regardless of sector protect/unprotect status
-- At V
IH
, allows removal of sector protection
-- At V
HH
, provides faster programming times in a factory
setting
Persistent Sector Protection
-- A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
-- Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
-- A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
Package options
-- 63-ball Fine-pitch BGA
-- 80-ball Fine-pitch BGA
2
Am29PDL640G
February 26, 2003
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 4 Mwords. The device is offered in 63- or 80-ball
Fine-pitch BGA packages. The word-wide data (x16) ap-
pears on DQ15-DQ0. This device can be programmed
in-system or in standard EPROM programmers. A 12.0 V
V
PP
is not required for write or erase operations.
The device offers fast page access times of 25, 30, and 45
ns, with corresponding random access times of 65, 70, 85,
and 90 ns, respectively, allowing high speed microproces-
sors to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
Page Mode Features
The device is AC timing, input/output, and package compat-
ible with 4 Mbit x16 page mode mask ROM. The page size
is 8 words.
After initial page access is accomplished, the page mode op-
eration provides fast read access speed of random locations
within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V
to 3.1 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combi-
nation of sectors of memory. This can be achieved in-system
or via programming equipment.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD's Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Bank
Sectors
A
8 Mbit (4 Kw x 8 and 32 Kw x 15)
B
24 Mbit (32 Kw x 48)
C
24 Mbit (32 Kw x 48)
D
8 Mbit (4 Kw x 8 and 32 Kw x 15)
February 26, 2003
Am29PDL640G
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simultaneous READ/Write Block Diagram . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11
Table 1. Am29PDL640G Device Bus Operations ...........................11
Requirements for Reading Array Data ................................... 11
Random Read (Non-Page Read) ........................................... 11
Page Mode Read .................................................................... 11
Table 2. Page Select .......................................................................12
Simultaneous Operation ......................................................... 12
Table 3. Bank Select .......................................................................12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation ............................................. 12
Autoselect Functions .............................................................. 12
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Table 4. Am29PDL640G Sector Architecture .................................13
Table 5. Bank Address ....................................................................15
Table 6. SecSi
TM
Sector Addresses ...............................................15
Table 7. Autoselect Codes (High Voltage Method) ........................16
Table 8. Am29PDL640G Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................16
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 17
Persistent Sector Protection ................................................... 17
Persistent Protection Bit (PPB) ............................................... 17
Persistent Protection Bit Lock (PPB Lock) ............................. 17
Dynamic Protection Bit (DYB) ................................................ 17
Table 9. Sector Protection Schemes ...............................................18
Persistent Sector Protection Mode Locking Bit ...................... 18
Password Protection Mode ..................................................... 18
Password and Password Mode Locking Bit ........................... 19
64-bit Password ...................................................................... 19
Write Protect (WP#) ................................................................ 19
Persistent Protection Bit Lock ................................................. 19
High Voltage Sector Protection .............................................. 20
Figure 1. In-System Sector Protection/
Sector Unprotection Algorithms ...................................................... 21
Temporary Sector Unprotect .................................................. 22
Figure 2. Temporary Sector Unprotect Operation........................... 22
SecSiTM (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
SecSi Sector Protection Bit .................................................... 23
Figure 3. SecSi Sector Protect Verify.............................................. 23
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ............................................................ 23
Write Pulse "Glitch" Protection ............................................... 23
Logical Inhibit .......................................................................... 23
Power-Up Write Inhibit ............................................................ 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . 28
Reading Array Data ................................................................ 28
Reset Command ..................................................................... 28
Autoselect Command Sequence ............................................ 28
Enter SecSiTM Sector/Exit SecSi Sector
Command Sequence .............................................................. 29
Word Program Command Sequence ...................................... 29
Unlock Bypass Command Sequence ..................................... 29
Figure 4. Program Operation ......................................................... 30
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Erase Suspend/Erase Resume Commands ........................... 31
Figure 5. Erase Operation.............................................................. 31
Password Program Command ................................................ 31
Password Verify Command .................................................... 32
Password Protection Mode Locking Bit Program Command .. 32
Persistent Sector Protection Mode Locking Bit Program
Command ............................................................................... 32
SecSi Sector Protection Bit Program Command .................... 32
PPB Lock Bit Set Command ................................................... 32
DYB Write Command ............................................................. 32
Password Unlock Command .................................................. 33
PPB Program Command ........................................................ 33
All PPB Erase Command ........................................................ 33
DYB Write Command ............................................................. 33
PPB Lock Bit Set Command ................................................... 33
PPB Status Command ............................................................ 33
PPB Lock Bit Status Command .............................................. 33
Sector Protection Status Command ....................................... 33
Table 14. Memory Array Command Definitions ............................. 34
Table 15. Sector Protection Command Definitions ........................ 35
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 36
DQ7: Data# Polling ................................................................. 36
Figure 6. Data# Polling Algorithm .................................................. 36
DQ6: Toggle Bit I .................................................................... 37
Figure 7. Toggle Bit Algorithm........................................................ 37
DQ2: Toggle Bit II ................................................................... 38
Reading Toggle Bits DQ6/DQ2 ............................................... 38
DQ5: Exceeded Timing Limits ................................................ 38
DQ3: Sector Erase Timer ....................................................... 38
Table 16. Write Operation Status ................................................... 39
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 40
Figure 8. Maximum Negative Overshoot Waveform ...................... 40
Figure 9. Maximum Positive Overshoot Waveform........................ 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. Test Setup.................................................................... 42
Figure 11. Input Waveforms and Measurement Levels ................. 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
Read-Only Operations ........................................................... 43
Figure 12. Read Operation Timings ............................................... 43
Figure 13. Page Read Operation Timings...................................... 44
Hardware Reset (RESET#) .................................................... 45
Figure 14. Reset Timings ............................................................... 45
Erase and Program Operations .............................................. 46
Figure 15. Program Operation Timings.......................................... 47
Figure 16. Accelerated Program Timing Diagram.......................... 47
Figure 17. Chip/Sector Erase Operation Timings .......................... 48
Figure 18. Back-to-back Read/Write Cycle Timings ...................... 49
Figure 19. Data# Polling Timings (During Embedded Algorithms). 49
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 50
Figure 21. DQ2 vs. DQ6................................................................. 50
Temporary Sector Unprotect .................................................. 51
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 51
4
Am29PDL640G
February 26, 2003
P R E L I M I N A R Y
Figure 23. Sector/Sector Block Protect and
Unprotect Timing Diagram .............................................................. 52
Alternate CE# Controlled Erase and Program Operations ..... 53
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings........................................................................... 54
Erase And Programming Performance . . . . . . . 55
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 55
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 55
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56
FBE080--80-Ball Fine-pitch Ball Grid Array
12 x 11 mm package .............................................................. 56
FBE063--63-Ball Fine-pitch Ball Grid Array
12 x 11 mm package .............................................................. 57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
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