PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Publication# 26090

Rev: A Amendment/0

Issue Date: March 8, 2002

Refer to AMD's Website (www.amd.com) for the latest information.

Am49DL640BG

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operation Flash Memory and 32 Mbit (512 K x 16-Bit) Pseudo Static RAM with Page Mode

DISTINCTIVE CHARACTERISTICS

MCP Features

Power supply voltage of 2.7 to 3.3 volt

High performance

-- Access time as fast as 70 ns

Package

-- 73-Ball FBGA

Operating Temperature

-- 40°C to +85°C

Flash Memory Features

ARCHITECTURAL ADVANTAGES

Simultaneous Read/Write operations

-- Data can be continuously read from one bank while

executing erase/program functions in another bank.

-- Zero latency between read and write operations

Flexible Bank

architecture

-- Read may occur in any of the three banks not being written

or erased.

-- Four banks may be grouped by customer to achieve desired

bank divisions.

Manufactured on 0.17 µm process technology

SecSiTM (Secured Silicon) Sector: Extra 256 Byte sector

-- Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data

-- Customer lockable: Sector is one-time programmable. Once

sector is locked, data cannot be changed.

Zero Power Operation

-- Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.

Boot sectors

-- Top and bottom boot sectors in the same device

Compatible with JEDEC standards

-- Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

High performance

-- Access time as fast as 70 ns
-- Program time: 4 µs/word typical utilizing Accelerate function

Ultra low power consumption (typical values)

-- 2 mA active read current at 1 MHz
-- 10 mA active read current at 5 MHz
-- 200 nA in standby or automatic sleep mode

Minimum 1 million write cycles guaranteed per sector

20 year data retention at 125

-- Reliable operation for the life of the system

SOFTWARE FEATURES

Data Management Software (DMS)

-- AMD-supplied software manages data programming,

enabling EEPROM emulation

-- Eases historical sector erase flash limitations

Supports Common Flash Memory Interface (CFI)

Program/Erase Suspend/Erase Resume

-- Suspends program/erase operations to allow

programming/erasing in same bank

Data# Polling and Toggle Bits

-- Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

-- Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

Any combination of sectors can be erased

Ready/Busy# output (RY/BY#)

-- Hardware method for detecting program or erase cycle

completion

Hardware reset pin (RESET#)

-- Hardware method of resetting the internal state machine to

the read mode

WP#/ACC input pin

-- Write protect (WP#) function protects sectors 0, 1, 140, and

141, regardless of sector protect status

-- Acceleration (ACC) function accelerates program timing

Sector protection

-- Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or
erase operation within that sector

-- Temporary Sector Unprotect allows changing data in

protected sectors in-system

pSRAM Features

Power dissipation

-- Operating: 40 mA maximum
-- Standby: 70 µA maximum
-- Deep power-down standby: 5 µA

CE1s# and CE2s Chip Select

Power down features using CE1s# and CE2s

Data retention supply voltage: 2.7 to 3.3 volt

Byte data control: LB#s (DQ7DQ0), UB#s (DQ15DQ8)

8-word page mode access

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

GENERAL DESCRIPTION

Am29DL640G Features

The Am29DL640G is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words of 16
bits each or 8,388,608 bytes of 8 bits each. Word
mode data appears on DQ15DQ0; byte mode data
appears on DQ7DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V

supply, and can also be programmed in standard
EPROM programmers.

The device is available with an access time of 70 or 85
ns and is offered in a 73-ball FBGA package. Standard
control pins--chip enable (CE#f), write enable (WE#),
and output enable (OE#)--control normal read and
write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.

Simultaneous Read/Write Operations with
Zero Latency

The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into four banks, two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors
only. Sector addresses are fixed, system software can
be used to form user-defined bank groups.

During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
sys tem t o program or er ase in one bank , t hen
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.

The Am29DL640G can be organized as both a top
and bottom boot sector configuration.

The SecSiTM (Secured Silicon) Sector is an extra
256 byte sector capable of being permanently locked
by AMD or customers. The SecSi Indicator Bit (DQ7)
is permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.

Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD's ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as a one-time programmable area.

DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s an a dv a n t a g e c o m p a r e d t o s y s t e m s w he r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.

The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.

The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.

The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.

The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
T he sys tem can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.

Bank

Megabits

Sector Sizes

Bank 1

8 Mb

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 2

24 Mb

Forty-eight 64 Kbyte/32 Kword

Bank 3

24 Mb

Forty-eight 64 Kbyte/32 Kword

Bank 4

8 Mb

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

March 8, 2002

Am49DL640BG

P R E L I M I N A R Y

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations--Flash Word Mode, CIOf = V

... 10

Table 2. Device Bus Operations--Flash Byte Mode, CIOf = V

..... 11

Flash Device Bus Operations . . . . . . . . . . . . . . . 12

Word/Byte Configuration ........................................................ 12
Requirements for Reading Array Data ................................... 12
Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12

Simultaneous Read/Write Operations with Zero Latency ....... 12
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13

Table 3. Am29DL640G Sector Architecture ....................................14
Table 4. Bank Address ....................................................................17
Table 5. SecSi

Sector Addresses ...............................................17

Sector/Sector Block Protection and Unprotection .................. 18

Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................18

Write Protect (WP#) ................................................................ 19

Table 7. WP#/ACC Modes ..............................................................19

Temporary Sector Unprotect .................................................. 19

Figure 1. Temporary Sector Unprotect Operation........................... 19
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 20

SecSiTM (Secured Silicon) Sector
Flash Memory Region ............................................................ 21
Hardware Data Protection ...................................................... 21

Low V

Write Inhibit ........................................................... 21

Write Pulse "Glitch" Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 8. CFI Query Identification String .......................................... 22
System Interface String................................................................... 23
Table 10. Device Geometry Definition ............................................ 23
Table 11. Primary Vendor-Specific Extended Query ...................... 24

Flash Command Definitions . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSiTM Sector/Exit SecSi Sector
Command Sequence .............................................................. 25
Byte/Word Program Command Sequence ............................. 26

Unlock Bypass Command Sequence .................................. 26

Figure 3. Program Operation .......................................................... 27

Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 27
Erase Suspend/Erase Resume Commands ........................... 28

Figure 4. Erase Operation.............................................................. 28
Table 12. Am29DL640G Command Definitions .............................. 29

Flash Write Operation Status . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ................................................................. 30

Figure 5. Data# Polling Algorithm .................................................. 30

RY/BY#: Ready/Busy# ............................................................ 31
DQ6: Toggle Bit I .................................................................... 31

Figure 6. Toggle Bit Algorithm........................................................ 31

DQ2: Toggle Bit II ................................................................... 32
Reading Toggle Bits DQ6/DQ2 ............................................... 32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32

Table 13. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform ...................... 34
Figure 8. Maximum Positive Overshoot Waveform........................ 34

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 35

CMOS Compatible .................................................................. 35

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 37
Figure 10. Typical I

CC1

vs. Frequency ............................................ 37

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. Test Setup.................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38

pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 39

CE#s Timing ........................................................................... 39

Figure 13. Timing Diagram for Alternating
Between Pseudo SRAM to Flash................................................... 39

Read-Only Operations ........................................................... 40

Figure 14. Read Operation Timings ............................................... 40

Hardware Reset (RESET#) .................................................... 41

Figure 15. Reset Timings ............................................................... 41

Word/Byte Configuration (CIOf) .............................................. 42

Figure 16. CIOf Timings for Read Operations................................ 42
Figure 17. CIOf Timings for Write Operations................................ 42

Erase and Program Operations .............................................. 43

Figure 18. Program Operation Timings.......................................... 44
Figure 19. Accelerated Program Timing Diagram.......................... 44
Figure 20. Chip/Sector Erase Operation Timings .......................... 45
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 46
Figure 22. Data# Polling Timings (During Embedded Algorithms). 46
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 47
Figure 24. DQ2 vs. DQ6................................................................. 47

Temporary Sector Unprotect .................................................. 48

Figure 25. Temporary Sector Unprotect Timing Diagram .............. 48
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 49

Alternate CE#f Controlled Erase and Program Operations .... 50

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 51

Read Cycle ............................................................................. 52

Figure 28. Psuedo SRAM Read Cycle........................................... 52
Figure 29. Page Read Timing ........................................................ 53

Write Cycle ............................................................................. 54

Figure 30. Pseudo SRAM Write Cycle--WE# Control ................... 54
Figure 31. Pseudo SRAM Write Cycle--CE1#s Control ................ 55
Figure 32. Pseudo SRAM Write Cycle--
UB#s and LB#s Control.................................................................. 56

Flash Erase And Programming Performance . . 57

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AM49DL640BG40IS