September 2003
This document specifies SPANSION
memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
memory
solutions.
TM
TM
TM
SPANSION MCP
Data Sheet
TM
DS05-50222-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (
16) FLASH MEMORY &
8M (
16) SRAM
MB84SD23280FA/MB84SD23280FE
-70
s
s
s
s
FEATURES
Power supply voltage of 1.65 V to 1.95 V
High performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
Operating Temperature
30
C to +85
C
Package 73-ball FBGA
(Continued)
s
s
s
s
PRODUCT LINEUP
*: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
s
s
s
PACKAGE
Flash Memory
SRAM
Supply Voltage (V)
V
CC
f* = 1.8 V
V
CC
s* = 1.8 V
Max Address Access Time (ns)
70
70
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
20
35
73-ball plastic FBGA
(BGA-73P-M03)
+0.15V
0.15 V
+0.15V
0.15 V
MB84SD23280FA/MB84SD23280FE
-70
2
(Continued)
FLASH MEMORY
0.17
m process technology
Simultaneous Read/Write operation (Dual Bank)
FlexBank
TM
*
1
Bank A: 16M bit (16KB
4 and 64KB
31)
Bank B: 16M bit (64KB
32)
Bank C: 16M bit (64KB
32)
Bank D: 16M bit (16KB
4 and 64KB
31)
Minimum 100,000 program/erase cycles
Sector Erase Architecture
Four 8K words, a hundred twenty-eight 32K words sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
WP Input Pin
At V
IL
, allows protection of all sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of sector protection
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Automatic sleep mode
When address remain stable, the device automatically switches itself to low power mode
Low V
CC
write inhibit
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
resumes the erase operation
Sector Protection
Software command sector locking
Please Refer to "MBM29BS64LF" Datasheet in Detailed Function
SRAM
Power Dissipation
Operating : 50 mA Max
Standby :15
A Max
Power Down Features using CE1s and CE2s
Data Retention Supply Voltage: 1.0 V to 1.95 V
CE1s and CE2s Chip Select
Byte Data Control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
*1: FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84SD23280FA/MB84SD23280FE
-70
4
s
s
s
s
PIN DESCRIPTION
Pin Configuration
s
s
s
s
BLOCK DIAGRAM
Pin Name
Function
Input/Output
A
18
to A
0
Address Inputs (Common)
I
A
21
, A
20
, A
19
Address Inputs (Flash)
I
DQ
15
to DQ
0
Data Inputs/Outputs (Common)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write
Enable
(Common) I
RDY
Ready Outputs (Flash) Open Drain Output
O
UB
Upper Byte Control (SRAM)
I
LB
Lower Byte Control (SRAM)
I
RESET
Hardware Reset Pin (Flash)
I
WP
Write Protect (Flash)
I
N.C.
No Internal Connection
V
SS
Device Ground (Common)
Power
V
CC
f
Device Power Supply (Flash)
Power
V
CC
s
Device Power Supply (SRAM)
Power
V
SS
V
CC
s
64 M bit
RESET
Flash Memory
WE
8 M bit
SRAM
CEf
A
21
to A
0
OE
CE1s
V
SS
V
CC
f
A
21
to A
0
A
18
to A
0
DQ
15
to DQ
0
RDY
LB
UB
WP
CE2s
DQ
15
to DQ
0
DQ
15
to DQ
0
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