September 2003
This document specifies SPANSION
memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
memory
solutions.
TM
TM
TM
SPANSION MCP
Data Sheet
TM
DS05-50221-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (
8/
16) FLASH MEMORY &
8M (
8/
16) STATIC RAM
MB84VD23280FA
-70
s
s
s
s
FEATURES
Power supply voltage of 2.7 V to 3.1 V
High performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
Operating Temperature
40
C to +85
C
Package 65-ball FBGA
(Continued)
s
s
s
s
PRODUCT LINEUP
*: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
s
s
s
PACKAGE
Flash Memory
SRAM
Supply Voltage (V)
V
CC
r* = 3.0 V
V
CC
s* = 3.0 V
Max Address Access Time (ns)
70
70
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
30
35
65-pin plastic FBGA
(BGA-65P-M01)
+0.1V
0.3 V
+0.1V
0.3 V
MB84VD23280FA
-70
2
(Continued)
FLASH MEMORY
0.16
m Process Technology
Simultaneous Read/Write operations (Dual Bank)
FlexBank
TM
*
1
Bank A : 8 Mbit (8 KB
8 and 64 KB
15)
Bank B : 24 Mbit (64 KB
48)
Bank C : 24 Mbit (64 KB
48)
Bank D : 8 Mbit (8 KB
8 and 64 KB
15)
Two virtual Banks are chosen from the combination of four physical banks
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
Single 3.0 V read, program, and erase
Minimized system level power requirements
Minimum 100,000 program/erase cycles
Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
HiddenROM region
256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC input pin
At V
IL
, allows protection of "outermost" 2
8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
Low V
CC
f write inhibit
2.5 V
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
Please refer to "MBM29DL64DF" data sheet in detailed function
(Continued)
MB84VD23280FA
-70
3
(Continued)
SRAM
Power dissipation
Operating: 50 mA Max
Standby: 15
A Max
Power down features using CE1s and CE2s
Data retention supply voltage: 1.5 V to 3.1 V
CE1s and CE2s Chip Select
Byte data control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
*1 : FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2 : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VD23280FA
-70
4
s
s
s
s
PIN ASSIGNMENT
D8
A
13
D7
A
9
D6
A
20
D5
RY/BY
D4
A
18
D3
A
5
D2
A
2
D9
A21
F8
SA
F7
DQ
6
DQ
1
F3
V
SS
F2
A
0
F9
A
16
G8
DQ
15
/A
-1
G7
DQ
13
G6
DQ
4
G5
DQ
3
G4
DQ
9
G3
OE
G2
CEf
G9
CIOf
E8
A
14
E7
A
10
E4
A
17
E3
A
4
E2
A
1
E9
N.C.
H8
DQ
7
H7
DQ
12
H6
Vccs
H5
Vccf
H4
DQ
10
H3
DQ
0
H2
CE1s
H9
Vss
J8
DQ
14
J7
DQ
5
J6
CIOs
J5
DQ
11
J4
DQ
2
J3
DQ
8
K9
N.C.
K2
N.C.
K1
N.C.
K10
N.C.
C8
A
12
C7
A
19
C6
CE2s
C5
RESET
C4
UB
C3
A
6
C2
A
3
C9
A
15
B8
A
11
B7
A
8
B6
WE
B5
WP/ACC
B4
LB
B3
A
7
A9
N.C.
B1
N.C.
A10
N.C.
A2
N.C.
A1
N.C.
F4
(BGA-65P-M01)
(Top View)
Marking side
MB84VD23280FA
-70
5
s
s
s
s
PIN DESCRIPTION
Pin name
Input/
Output
Description
A
18
to A
0
I
Address Inputs (Common)
A
21
to A
19
, A
1
I
Address Inputs (Flash)
SA
I
Address Input (SRAM)
DQ
15
to DQ
0
I/O
Data Inputs/Outputs (Common)
CEf
I
Chip Enable (Flash)
CE1s
I
Chip Enable (SRAM)
CE2s
I
Chip Enable (SRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready/Busy Output (Flash) Open Drain Output
UB
I
Upper Byte Control (SRAM)
LB
I
Lower Byte Control (SRAM)
CIOf
I
I/O Configuration (Flash)
CIOf = V
CC
f is Word mode (16), CIOf = V
SS
is Byte mode (8)
CIOs
I
I/O Configuration (SRAM)
CIOs = V
CC
s is Word mode (16), CIOs = V
SS
is Byte mode (8)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
I
Write Protect / Acceleration (Flash)
N.C.
--
No Internal Connection
V
SS
Power
Device Ground (Common)
V
CC
f
Power
Device Power Supply (Flash)
V
CC
s
Power
Device Power Supply (SRAM)
MB84VD23280FA
-70
6
s
s
s
s
BLOCK DIAGRAM
V
SS
V
CC
s
64 M bit
RESET
Flash Memory
WE
8 M bit
Static RAM
CEf
A
21
to A
0
OE
CE1s
V
SS
V
CC
f
A
21
to A
0
A
18
to A
0
DQ
15
/A
1
to DQ
0
RY/BY
LB
UB
CIOf
WP/ACC
CE2s
DQ
15
/A
1
to DQ
0
DQ
15
to DQ
0
A
1
SA
CIOs
MB84VD23280FA
-70
7
s
s
s
s
DEVICE BUS OPERATIONS
User Bus Operations (Flash = Word mode; CIOf = V
CC
f, SRAM = Word mode; CIOs = V
CC
s)
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
*3 : Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
*4 : Also used for the extended sector group protections.
*5 : Protects of "outermost" 2 x 4 Kwords on both ends of each boot block sector.
Operation *
1,
*
3
CEf CE1s CE2s OE
WE
SA
LB
UB
DQ
7
to DQ
0
DQ
15
to DQ
8
RESET
WP/
ACC
*
5
Full Standby
H
H
X
X
X
X
X
X
High-Z
High-Z
H
X
X
L
Output Disable
H
L
H
H
H
X
X
X
High-Z
High-Z
H
X
X
X
X
H
H
High-Z
High-Z
L
H
X
H
H
X
X
X
High-Z
High-Z
X
L
Read from Flash *
2
L
H
X
L
H
X
X
X
D
OUT
D
OUT
H
X
X
L
Write to Flash
L
H
X
H
L
X
X
X
D
IN
D
IN
H
X
X
L
Read from SRAM
H
L
H
L
H
X
L
L
D
OUT
D
OUT
H
X
H
L
High-Z
D
OUT
L
H
D
OUT
High-Z
Write to SRAM
H
L
H
X
L
X
L
L
D
IN
D
IN
H
X
H
L
High-Z
D
IN
L
H
D
IN
High-Z
Temporary Sector
Group Unprotec-
tion *
4
X
X
X
X
X
X
X
X
X
X
V
ID
X
Flash Hardware
Reset
X
H
X
X
X
X
X
X
High-Z
High-Z
L
X
X
L
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
L
MB84VD23280FA
-70
8
User Bus Operations (Flash = Word mode; CIOf = V
CC
f, SRAM = Byte mode; CIOs = V
SS
)
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
*3 : Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
*4 : It is also used for the extended sector group protections.
*5 : Protect of "outermost" 2 x 4 Kwords on both ends of each boot block sector.
Operation *
1,
*
3
CEf CE1s CE2s OE
WE
SA
LB
UB
DQ
7
to DQ
0
DQ
15
to DQ
8
RESET
WP/
ACC
*
5
Full Standby
H
H
X
X
X
X
X
X
High-Z
High-Z
H
X
X
L
Output Disable
H
L
H
H
H
X
X
X
High-Z
High-Z
H
X
X
X
X
H
H
High-Z
High-Z
L
H
X
H
H
X
X
X
High-Z
High-Z
X
L
Read from Flash*
2
L
H
X
L
H
X
X
X
D
OUT
D
OUT
H
X
X
L
Write to Flash
L
H
X
H
L
X
X
X
D
IN
D
IN
H
X
X
L
Read from SRAM
H
L
H
L
H
SA
X
X
D
OUT
High-Z
H
X
Write to SRAM
H
L
H
X
L
SA
X
X
D
IN
High-Z
H
X
Temporary Sector
Group Unprotec-
tion*
4
X
X
X
X
X
X
X
X
X
X
V
ID
X
Flash Hardware
Reset
X
H
X
X
X
X
X
X
High-Z
High-Z
L
X
X
L
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
L
MB84VD23280FA
-70
9
User Bus Operations (Flash = Byte mode; CIOf = V
SS
, SRAM = Byte mode; CIOs = V
SS
)
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
*3 : Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
*4 : It is also used for the extended sector group protections.
*5 : Protect of "outermost" 2 x 8 Kbytes on both ends of each boot block sector.
Operation *
1,
*
3
CEf CE1s CE2s DQ
15
/A
1
OE WE SA
LB
UB
DQ
7
to
DQ
0
DQ
14
to
DQ
8
RESET
WP/
ACC
*
5
Full Standby
H
H
X
X
X
X
X
X
X
High-Z
High-Z
H
X
X
L
Output Disable
H
L
H
X
H
H
X
X
X
High-Z
High-Z
H
X
X
X
X
X
H
H
High-Z
High-Z
L
H
X
A
1
H
H
X
X
X
High-Z
High-Z
X
L
Read from Flash*
2
L
H
X
A
1
L
H
X
X
X
D
OUT
X
H
X
X
L
Write to Flash
L
H
X
A
1
H
L
X
X
X
D
IN
X
H
X
X
L
Read from SRAM
H
L
H
X
L
H
SA
X
X
D
OUT
High-Z
H
X
Write to SRAM
H
L
H
X
X
L
SA
X
X
D
IN
High-Z
H
X
Temporary Sector
Group
Unprotection *
4
X
X
X
X
X
X
X
X
X
X
X
V
ID
X
Flash Hardware
Reset
X
H
X
X
X
X
X
X
X
High-Z
High-Z
L
X
X
L
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
X
L
MB84VD23280FA
-70
10
s
s
s
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
Sixteen 4K words, and one hundred twenty-six 32 K words.
Individual-sector, multiple-sector, or bulk-erase capability.
Sector Architecture
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA70 : 64KB (32KW)
SA69 : 64KB (32KW)
SA68 : 64KB (32KW)
SA67 : 64KB (32KW)
SA66 : 64KB (32KW)
SA65 : 64KB (32KW)
SA64 : 64KB (32KW)
SA63 : 64KB (32KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
Bank A
Bank B
070000h
078000h
060000h
068000h
050000h
058000h
040000h
048000h
030000h
038000h
020000h
028000h
010000h
018000h
007000h
008000h
005000h
006000h
003000h
004000h
001000h
002000h
000000h
SA102 : 64KB (32KW)
SA101 : 64KB (32KW)
SA100 : 64KB (32KW)
SA99 : 64KB (32KW)
SA98 : 64KB (32KW)
SA97 : 64KB (32KW)
SA96 : 64KB (32KW)
SA95 : 64KB (32KW)
SA94 : 64KB (32KW)
SA93 : 64KB (32KW)
SA92 : 64KB (32KW)
SA91 : 64KB (32KW)
SA90 : 64KB (32KW)
SA89 : 64KB (32KW)
SA88 : 64KB (32KW)
SA87 : 64KB (32KW)
SA86 : 64KB (32KW)
SA85 : 64KB (32KW)
SA84 : 64KB (32KW)
SA83 : 64KB (32KW)
SA82 : 64KB (32KW)
SA81 : 64KB (32KW)
SA80 : 64KB (32KW)
SA79 : 64KB (32KW)
SA78 : 64KB (32KW)
SA77 : 64KB (32KW)
SA76 : 64KB (32KW)
SA75 : 64KB (32KW)
SA74 : 64KB (32KW)
SA73 : 64KB (32KW)
3FFFFFh
SA141 : 8KB (4KW)
SA140 : 8KB (4KW)
SA139 : 8KB (4KW)
SA138 : 8KB (4KW)
SA137 : 8KB (4KW)
SA136 : 8KB (4KW)
SA135 : 8KB (4KW)
SA134 : 8KB (4KW)
SA133 : 64KB (32KW)
SA132 : 64KB (32KW)
SA131 : 64KB (32KW)
SA130 : 64KB (32KW)
SA129 : 64KB (32KW)
SA128 : 64KB (32KW)
SA127 : 64KB (32KW)
SA126 : 64KB (32KW)
SA125 : 64KB (32KW)
SA124 : 64KB (32KW)
SA123 : 64KB (32KW)
SA122 : 64KB (32KW)
SA121 : 64KB (32KW)
SA120 : 64KB (32KW)
SA119 : 64KB (32KW)
SA118 : 64KB (32KW)
SA117 : 64KB (32KW)
SA116 : 64KB (32KW)
SA115 : 64KB (32KW)
SA114 : 64KB (32KW)
SA113 : 64KB (32KW)
SA112 : 64KB (32KW)
SA111 : 64KB (32KW)
SA110 : 64KB (32KW)
SA109 : 64KB (32KW)
SA108 : 64KB (32KW)
SA107 : 64KB (32KW)
SA106 : 64KB (32KW)
SA105 : 64KB (32KW)
SA104 : 64KB (32KW)
SA103 : 64KB (32KW)
SA72 : 64KB (32KW)
SA71 : 64KB (32KW)
Bank C
Bank D
3FF000h
3FE000h
3FD000h
3FC000h
3FB000h
3FA000h
3F9000h
0F0000h
0F8000h
0E0000h
0E8000h
0D0000h
0D8000h
0C0000h
0C8000h
0B0000h
0B8000h
0A0000h
0A8000h
090000h
098000h
088000h
080000h
170000h
178000h
160000h
168000h
150000h
158000h
140000h
148000h
130000h
138000h
120000h
128000h
110000h
118000h
100000h
108000h
1F0000h
1F8000h
1E0000h
1E8000h
1D0000h
1D8000h
1C0000h
1C8000h
1B0000h
1B8000h
1A0000h
1A8000h
190000h
198000h
188000h
180000h
270000h
278000h
260000h
268000h
250000h
258000h
240000h
248000h
230000h
238000h
220000h
228000h
210000h
218000h
208000h
2F0000h
2F8000h
2E0000h
2E8000h
2D0000h
2D8000h
2C0000h
2C8000h
2B0000h
2B8000h
2A0000h
2A8000h
290000h
298000h
288000h
280000h
370000h
378000h
360000h
368000h
350000h
358000h
340000h
348000h
330000h
338000h
320000h
328000h
310000h
318000h
300000h
308000h
3F0000h
3F8000h
3E0000h
3E8000h
3D0000h
3D8000h
3C0000h
3C8000h
3B0000h
3B8000h
3A0000h
3A8000h
390000h
398000h
388000h
380000h
200000h
1FFFFFh
0E0000h
0F0000h
0C0000h
0D0000h
0A0000h
0B0000h
080000h
090000h
060000h
070000h
040000h
050000h
020000h
030000h
00E000h
010000h
00A000h
00C000h
006000h
008000h
002000h
004000h
000000h
1E0000h
1F0000h
1C0000h
1D0000h
1A0000h
1B0000h
180000h
190000h
160000h
170000h
140000h
158000h
120000h
130000h
110000h
100000h
2E0000h
2F0000h
2C0000h
2D0000h
2A0000h
2B0000h
280000h
290000h
260000h
270000h
240000h
250000h
220000h
230000h
200000h
210000h
3E0000h
3F0000h
3C0000h
3D0000h
3A0000h
3B0000h
380000h
390000h
360000h
370000h
340000h
350000h
320000h
330000h
310000h
300000h
3FFFFFh
Word Mode Byte Mode
Word Mode
Byte Mode
7FFFFFh
7FE000h
7FC000h
7FA000h
7F8000h
7F6000h
7F4000h
7F2000h
4E0000h
4F0000h
4C0000h
4D0000h
4A0000h
4B0000h
480000h
490000h
460000h
470000h
440000h
450000h
420000h
430000h
410000h
5E0000h
5F0000h
5C0000h
5D0000h
5A0000h
5B0000h
580000h
590000h
560000h
570000h
540000h
550000h
520000h
530000h
510000h
500000h
6E0000h
6F0000h
6C0000h
6D0000h
6A0000h
6B0000h
680000h
690000h
660000h
670000h
640000h
650000h
620000h
630000h
600000h
610000h
7E0000h
7F0000h
7C0000h
7D0000h
7A0000h
7B0000h
780000h
790000h
760000h
770000h
740000h
750000h
720000h
730000h
710000h
700000h
400000h
MB84VD23280FA
-70
11
FlexBank
TM
Architecture
Example of Virtual Banks Combination
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which
a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,
neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)
Meanwhile the system would get to read from either Bank C or Bank D.
Simultaneous Operation
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets
suspended so that it enables reading from or programming the remaining sectors.
Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank
consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the
Banks.
Bank
Splits
Bank 1
Bank 2
Volume
Combination
Volume
Combination
1
8 Mbit
Bank A
56 Mbit
Remainder (Bank B, C, D)
2
24 Mbit
Bank B
40 Mbit
Remainder (Bank A, C, D)
3
24 Mbit
Bank C
40 Mbit
Remainder (Bank A, B, D)
4
8 Mbit
Bank D
56 Mbit
Remainder (Bank A, B, C)
Bank
Splits
Bank 1
Bank 2
Volume Combination
Sector Size
Volume Combination
Sector Size
1
8 Mbit
Bank A
8
8 Kbyte/4 Kword
+
15
64 Kbyte/32 Kword
56 Mbit
Bank B
+
Bank C
+
Bank D
8
8 Kbyte/4 Kword
+
111
64 Kbyte/32 Kword
2
16 Mbit
Bank A
+
Bank D
16
8 Kbyte/4 Kword
+
30
64 Kbyte/32 Kword
48 Mbit
Bank B
+
Bank C
96
64 Kbyte/32 Kword
3
24 Mbit
Bank B
48
64 Kbyte/32 Kword 40 Mbit
Bank A
+
Bank C
+
Bank D
16
8 Kbyte/4 Kword
+
78
64 Kbyte/32 Kword
4
32 Mbit
Bank A
+
Bank B
8
8 Kbyte/4 Kword
+
63
64 Kbyte/32 Kword
32 Mbit
Bank C
+
Bank D
8
8 Kbyte/4 Kword
+
63
64 Kbyte/32 Kword
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode *
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode *
Read mode
MB84VD23280FA
-70
12
Sector Address Tables
(Continued)
Bank
Sector
Sector Address
Address Range
Bank Address
Byte Mode
Word Mode
A
21
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Bank A
SA0
0
0
0
0
0
0
0
0
0
0
000000h to 001FFFh
000000h to 000FFFh
SA1
0
0
0
0
0
0
0
0
0
1
002000h to 003FFFh
001000h to 001FFFh
SA2
0
0
0
0
0
0
0
0
1
0
004000h to 005FFFh
002000h to 002FFFh
SA3
0
0
0
0
0
0
0
0
1
1
006000h to 007FFFh
003000h to 003FFFh
SA4
0
0
0
0
0
0
0
1
0
0
008000h to 009FFFh
004000h to 004FFFh
SA5
0
0
0
0
0
0
0
1
0
1
00A000h to 00BFFFh
005000h to 005FFFh
SA6
0
0
0
0
0
0
0
1
1
0
00C000h to 00DFFFh
006000h to 006FFFh
SA7
0
0
0
0
0
0
0
1
1
1
00E000h to 00FFFFh
007000h to 007FFFh
SA8
0
0
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA9
0
0
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA10
0
0
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA11
0
0
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA12
0
0
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA13
0
0
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA14
0
0
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA15
0
0
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA16
0
0
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA17
0
0
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA18
0
0
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA19
0
0
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh
060000h to 067FFFh
SA20
0
0
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh
068000h to 06FFFFh
SA21
0
0
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA22
0
0
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
MB84VD23280FA
-70
13
(Continued)
(Continued)
Bank
Sector
Sector Address
Address Range
Bank Address
Byte Mode
Word Mode
A
21
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Bank B
SA23
0
0
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA24
0
0
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA25
0
0
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA26
0
0
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA27
0
0
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA28
0
0
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA29
0
0
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA30
0
0
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA31
0
0
1
1
0
0
0
X
X
X
180000h to 18FFFFh
0C0000h to 0C7FFFh
SA32
0
0
1
1
0
0
1
X
X
X
190000h to 19FFFFh
0C8000h to 0CFFFFh
SA33
0
0
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh
0D0000h to 0D7FFFh
SA34
0
0
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh
0D8000h to 0DFFFFh
SA35
0
0
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh
0E0000h to 0E7FFFh
SA36
0
0
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh
0E8000h to 0EFFFFh
SA37
0
0
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh
0F0000h to 0F7FFFh
SA38
0
0
1
1
1
1
1
X
X
X
1F0000h to 1FFFFFh
0F8000h to 0FFFFFh
SA39
0
1
0
0
0
0
0
X
X
X
200000h to 20FFFFh
100000h to 107FFFh
SA40
0
1
0
0
0
0
1
X
X
X
210000h to 21FFFFh
108000h to 10FFFFh
SA41
0
1
0
0
0
1
0
X
X
X
220000h to 22FFFFh
110000h to 117FFFh
SA42
0
1
0
0
0
1
1
X
X
X
230000h to 23FFFFh
118000h to 11FFFFh
SA43
0
1
0
0
1
0
0
X
X
X
240000h to 24FFFFh
120000h to 127FFFh
SA44
0
1
0
0
1
0
1
X
X
X
250000h to 25FFFFh
128000h to 12FFFFh
SA45
0
1
0
0
1
1
0
X
X
X
260000h to 26FFFFh
130000h to 137FFFh
SA46
0
1
0
0
1
1
1
X
X
X
270000h to 27FFFFh
138000h to 13FFFFh
SA47
0
1
0
1
0
0
0
X
X
X
280000h to 28FFFFh
140000h to 147FFFh
SA48
0
1
0
1
0
0
1
X
X
X
290000h to 29FFFFh
148000h to 14FFFFh
SA49
0
1
0
1
0
1
0
X
X
X
2A0000h to 2AFFFFh
150000h to 157FFFh
SA50
0
1
0
1
0
1
1
X
X
X
2B0000h to 2BFFFFh
158000h to 15FFFFh
SA51
0
1
0
1
1
0
0
X
X
X
2C0000h to 2CFFFFh
160000h to 167FFFh
SA52
0
1
0
1
1
0
1
X
X
X
2D0000h to 2DFFFFh
168000h to 16FFFFh
SA53
0
1
0
1
1
1
0
X
X
X
2E0000h to 2EFFFFh
170000h to 177FFFh
SA54
0
1
0
1
1
1
1
X
X
X
2F0000h to 2FFFFFh
178000h to 17FFFFh
SA55
0
1
1
0
0
0
0
X
X
X
300000h to 30FFFFh
180000h to 187FFFh
SA56
0
1
1
0
0
0
1
X
X
X
310000h to 31FFFFh
188000h to 18FFFFh
SA57
0
1
1
0
0
1
0
X
X
X
320000h to 32FFFFh
190000h to 197FFFh
SA58
0
1
1
0
0
1
1
X
X
X
330000h to 33FFFFh
198000h to 19FFFFh
SA59
0
1
1
0
1
0
0
X
X
X
340000h to 34FFFFh
1A0000h to 1A7FFFh
SA60
0
1
1
0
1
0
1
X
X
X
350000h to 35FFFFh
1A8000h to 1AFFFFh
SA61
0
1
1
0
1
1
0
X
X
X
360000h to 36FFFFh
1B0000h to 1B7FFFh
SA62
0
1
1
0
1
1
1
X
X
X
370000h to 37FFFFh
1B8000h to 1BFFFFh
SA63
0
1
1
1
0
0
0
X
X
X
380000h to 38FFFFh
1C0000h to 1C7FFFh
SA64
0
1
1
1
0
0
1
X
X
X
390000h to 39FFFFh
1C8000h to 1CFFFFh
SA65
0
1
1
1
0
1
0
X
X
X
3A0000h to 3AFFFFh
1D0000h to 1D7FFFh
SA66
0
1
1
1
0
1
1
X
X
X
3B0000h to 3BFFFFh
1D8000h to 1DFFFFh
SA67
0
1
1
1
1
0
0
X
X
X
3C0000h to 3CFFFFh
1E0000h to 1E7FFFh
SA68
0
1
1
1
1
0
1
X
X
X
3D0000h to 3DFFFFh
1E8000h to 1EFFFFh
SA69
0
1
1
1
1
1
0
X
X
X
3E0000h to 3EFFFFh
1F0000h to 1F7FFFh
SA70
0
1
1
1
1
1
1
X
X
X
3F0000h to 3FFFFFh
1F8000h to 1FFFFFh
MB84VD23280FA
-70
14
(Continued)
(Continued)
Bank
Sector
Sector Address
Address Range
Bank Address
Byte Mode
Word Mode
A
21
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Bank C
SA71
1
0
0
0
0
0
0
X
X
X
400000h to 40FFFFh
200000h to 207FFFh
SA72
1
0
0
0
0
0
1
X
X
X
410000h to 41FFFFh
208000h to 20FFFFh
SA73
1
0
0
0
0
1
0
X
X
X
420000h to 42FFFFh
210000h to 217FFFh
SA74
1
0
0
0
0
1
1
X
X
X
430000h to 43FFFFh
218000h to 21FFFFh
SA75
1
0
0
0
1
0
0
X
X
X
440000h to 44FFFFh
220000h to 227FFFh
SA76
1
0
0
0
1
0
1
X
X
X
450000h to 45FFFFh
228000h to 22FFFFh
SA77
1
0
0
0
1
1
0
X
X
X
460000h to 46FFFFh
230000h to 237FFFh
SA78
1
0
0
0
1
1
1
X
X
X
470000h to 47FFFFh
238000h to 23FFFFh
SA79
1
0
0
1
0
0
0
X
X
X
480000h to 48FFFFh
240000h to 247FFFh
SA80
1
0
0
1
0
0
1
X
X
X
490000h to 49FFFFh
248000h to 24FFFFh
SA81
1
0
0
1
0
1
0
X
X
X
4A0000h to 4AFFFFh
250000h to 257FFFh
SA82
1
0
0
1
0
1
1
X
X
X
4B0000h to 4BFFFFh
258000h to 25FFFFh
SA83
1
0
0
1
1
0
0
X
X
X
4C0000h to 4CFFFFh
260000h to 267FFFh
SA84
1
0
0
1
1
0
1
X
X
X
4D0000h to 4DFFFFh
268000h to 26FFFFh
SA85
1
0
0
1
1
1
0
X
X
X
4E0000h to 4EFFFFh
270000h to 277FFFh
SA86
1
0
0
1
1
1
1
X
X
X
4F0000h to 4FFFFFh
278000h to 27FFFFh
SA87
1
0
1
0
0
0
0
X
X
X
500000h to 50FFFFh
280000h to 287FFFh
SA88
1
0
1
0
0
0
1
X
X
X
510000h to 51FFFFh
288000h to 28FFFFh
SA89
1
0
1
0
0
1
0
X
X
X
520000h to 52FFFFh
290000h to 297FFFh
SA90
1
0
1
0
0
1
1
X
X
X
530000h to 53FFFFh
298000h to 29FFFFh
SA91
1
0
1
0
1
0
0
X
X
X
540000h to 54FFFFh
2A0000h to 2A7FFFh
SA92
1
0
1
0
1
0
1
X
X
X
550000h to 55FFFFh
2A8000h to 2AFFFFh
SA93
1
0
1
0
1
1
0
X
X
X
560000h to 56FFFFh
2B0000h to 2B7FFFh
SA94
1
0
1
0
1
1
1
X
X
X
570000h to 57FFFFh
2B8000h to 2BFFFFh
SA95
1
0
1
1
0
0
0
X
X
X
580000h to 58FFFFh
2C0000h to 2C7FFFh
SA96
1
0
1
1
0
0
1
X
X
X
590000h to 59FFFFh
2C8000h to 2CFFFFh
SA97
1
0
1
1
0
1
0
X
X
X
5A0000h to 5AFFFFh
2D0000h to 2D7FFFh
SA98
1
0
1
1
0
1
1
X
X
X
5B0000h to 5BFFFFh
2D8000h to 2DFFFFh
SA99
1
0
1
1
1
0
0
X
X
X
5C0000h to 5CFFFFh
2E0000h to 2E7FFFh
SA100
1
0
1
1
1
0
1
X
X
X
5D0000h to 5DFFFFh
2E8000h to 2EFFFFh
SA101
1
0
1
1
1
1
0
X
X
X
5E0000h to 5EFFFFh
2F0000h to 2F7FFFh
SA102
1
0
1
1
1
1
1
X
X
X
5F0000h to 5FFFFFh
2F8000h to 2FFFFFh
SA103
1
1
0
0
0
0
0
X
X
X
600000h to 60FFFFh
300000h to 307FFFh
SA104
1
1
0
0
0
0
1
X
X
X
610000h to 61FFFFh
308000h to 30FFFFh
SA105
1
1
0
0
0
1
0
X
X
X
620000h to 62FFFFh
310000h to 317FFFh
SA106
1
1
0
0
0
1
1
X
X
X
630000h to 63FFFFh
318000h to 31FFFFh
SA107
1
1
0
0
1
0
0
X
X
X
640000h to 64FFFFh
320000h to 327FFFh
SA108
1
1
0
0
1
0
1
X
X
X
650000h to 65FFFFh
328000h to 32FFFFh
SA109
1
1
0
0
1
1
0
X
X
X
660000h to 66FFFFh
330000h to 337FFFh
SA110
1
1
0
0
1
1
1
X
X
X
670000h to 67FFFFh
338000h to 33FFFFh
SA111
1
1
0
1
0
0
0
X
X
X
680000h to 68FFFFh
340000h to 347FFFh
SA112
1
1
0
1
0
0
1
X
X
X
690000h to 69FFFFh
348000h to 34FFFFh
SA113
1
1
0
1
0
1
0
X
X
X
6A0000h to 6AFFFFh
350000h to 357FFFh
SA114
1
1
0
1
0
1
1
X
X
X
6B0000h to 6BFFFFh
358000h to 35FFFFh
SA115
1
1
0
1
1
0
0
X
X
X
6C0000h to 6CFFFFh
360000h to 367FFFh
SA116
1
1
0
1
1
0
1
X
X
X
6D0000h to 6DFFFFh
368000h to 36FFFFh
SA117
1
1
0
1
1
1
0
X
X
X
6E0000h to 6EFFFFh
370000h to 377FFFh
SA118
1
1
0
1
1
1
1
X
X
X
6F0000h to 6FFFFFh
378000h to 37FFFFh
MB84VD23280FA
-70
15
(Continued)
Bank
Sector
Sector Address
Address Range
Bank Address
Byte Mode
Word Mode
A
21
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Bank D
SA119
1
1
1
0
0
0
0
X
X
X
700000h to 70FFFFh
380000h to 387FFFh
SA120
1
1
1
0
0
0
1
X
X
X
710000h to 71FFFFh
388000h to 38FFFFh
SA121
1
1
1
0
0
1
0
X
X
X
720000h to 72FFFFh
390000h to 397FFFh
SA122
1
1
1
0
0
1
1
X
X
X
730000h to 73FFFFh
398000h to 39FFFFh
SA123
1
1
1
0
1
0
0
X
X
X
740000h to 74FFFFh
3A0000h to 3A7FFFh
SA124
1
1
1
0
1
0
1
X
X
X
750000h to 75FFFFh
3A8000h to 3AFFFFh
SA125
1
1
1
0
1
1
0
X
X
X
760000h to 76FFFFh
3B0000h to 3B7FFFh
SA126
1
1
1
0
1
1
1
X
X
X
770000h to 77FFFFh
3B8000h to 3BFFFFh
SA127
1
1
1
1
0
0
0
X
X
X
780000h to 78FFFFh
3C0000h to 3C7FFFh
SA128
1
1
1
1
0
0
1
X
X
X
790000h to 79FFFFh
3C8000h to 3CFFFFh
SA129
1
1
1
1
0
1
0
X
X
X
7A0000h to 7AFFFFh
3D0000h to 3D7FFFh
SA130
1
1
1
1
0
1
1
X
X
X
7B0000h to 7BFFFFh
3D8000h to 3DFFFFh
SA131
1
1
1
1
1
0
0
X
X
X
7C0000h to 7CFFFFh
3E0000h to 3E7FFFh
SA132
1
1
1
1
1
0
1
X
X
X
7D0000h to 7DFFFFh
3E8000h to 3EFFFFh
SA133
1
1
1
1
1
1
0
X
X
X
7E0000h to 7EFFFFh
3F0000h to 3F7FFFh
SA134
1
1
1
1
1
1
1
0
0
0
7F0000h to 7F1FFFh
3F8000h to 3F8FFFh
SA135
1
1
1
1
1
1
1
0
0
1
7F2000h to 7F3FFFh
3F9000h to 3F9FFFh
SA136
1
1
1
1
1
1
1
0
1
0
7F4000h to 7F5FFFh
3FA000h to 3FAFFFh
SA137
1
1
1
1
1
1
1
0
1
1
7F6000h to 7F7FFFh
3FB000h to 3FBFFFh
SA138
1
1
1
1
1
1
1
1
0
0
7F8000h to 7F9FFFh
3FC000h to 3FCFFFh
SA139
1
1
1
1
1
1
1
1
0
1
7FA000h to 7FBFFFh
3FD000h to 3FDFFFh
SA140
1
1
1
1
1
1
1
1
1
0
7FC000h to 7FDFFFh
3FE000h to 3FEFFFh
SA141
1
1
1
1
1
1
1
1
1
1
7FE000h to 7FFFFFh
3FF000h to 3FFFFFh
MB84VD23280FA
-70
16
Sector Group Addresses
Sector Group
A
21
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
0
1
1
1
SA7
SGA8
0
0
0
0
0
0
1
X
X
X
SA8 to SA10
1
0
0
1
SGA9
0
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
0
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
0
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
0
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
0
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
0
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
0
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
0
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA23
0
1
1
1
1
X
X
X
X
X
SA67 to SA70
SGA24
1
0
0
0
0
X
X
X
X
X
SA71 to SA74
SGA25
1
0
0
0
1
X
X
X
X
X
SA75 to SA78
SGA26
1
0
0
1
0
X
X
X
X
X
SA79 to SA82
SGA27
1
0
0
1
1
X
X
X
X
X
SA83 to SA86
SGA28
1
0
1
0
0
X
X
X
X
X
SA87 to SA90
SGA29
1
0
1
0
1
X
X
X
X
X
SA91 to SA94
SGA30
1
0
1
1
0
X
X
X
X
X
SA95 to SA98
SGA31
1
0
1
1
1
X
X
X
X
X
SA99 to SA102
SGA32
1
1
0
0
0
X
X
X
X
X
SA103 to SA106
SGA33
1
1
0
0
1
X
X
X
X
X
SA107 to SA110
SGA34
1
1
0
1
0
X
X
X
X
X
SA111 to SA114
SGA35
1
1
0
1
1
X
X
X
X
X
SA115 to SA118
SGA36
1
1
1
0
0
X
X
X
X
X
SA119 to SA122
SGA37
1
1
1
0
1
X
X
X
X
X
SA123 to SA126
SGA38
1
1
1
1
0
X
X
X
X
X
SA127 to SA130
SGA39
1
1
1
1
1
0
0
X
X
X
SA131 to SA133
0
1
1
0
SGA40
1
1
1
1
1
1
1
0
0
0
SA134
SGA41
1
1
1
1
1
1
1
0
0
1
SA135
SGA42
1
1
1
1
1
1
1
0
1
0
SA136
SGA43
1
1
1
1
1
1
1
0
1
1
SA137
SGA44
1
1
1
1
1
1
1
1
0
0
SA138
SGA45
1
1
1
1
1
1
1
1
0
1
SA139
SGA46
1
1
1
1
1
1
1
1
1
0
SA140
SGA47
1
1
1
1
1
1
1
1
1
1
SA141
MB84VD23280FA
-70
17
Flash Memory Autoselect Codes
Legend: L = V
IL
, H = V
IH
. See DC Characteristics for voltage levels.
*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will
require two additional codes, called Extended Device Codes. Therefore the system may continue reading out
these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
Type
A
21
to A
12
A
6
A
3
A
2
A
1
A
0
Code (HEX)
Manufacture's Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
227Eh
Extended Device
Code *
2
BA
L
H
H
H
L
2202h
BA
L
H
H
H
H
2201h
Sector Group Protec-
tion
Sector Group
Addresses
L
L
L
H
L
01h*
1
MB84VD23280FA
-70
18
Flash Memory Command Definitions
(Continued)
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset
Word
1
XXXh
F0h
--
--
--
--
--
--
--
--
--
--
Byte
Read/Reset
Word
3
555h
AAh
2AAh
55h
555h
F0h
RA
RD
--
--
--
--
Byte
AAAh
555h
AAAh
Autoselect
Word
3
555h
AAh
2AAh
55h
(BA)
555h
90h
--
--
--
--
--
--
Byte
AAAh
555h
(BA)
AAAh
Program
Word
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
--
--
--
--
Byte
AAAh
555h
AAAh
Program Suspend
1
BA
B0h
--
--
--
--
--
--
--
--
--
--
Program Resume
1
BA
30h
--
--
--
--
--
--
--
--
--
--
Chip Erase
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Byte
AAAh
555h
AAAh
AAAh
555h
AAAh
Sector
Erase
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
SA
30h
Byte
AAAh
555h
AAAh
AAAh
555h
Erase Suspend
1
BA
B0h
--
--
--
--
--
--
--
--
--
--
Erase Resume
1
BA
30h
--
--
--
--
--
--
--
--
--
--
Extended
Sector
Group
Protection *
2
Word
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
--
--
--
--
Byte
Set to
Fast Mode
Word
3
555h
AAh
2AAh
55h
555h
20h
--
--
--
--
--
--
Byte
AAAh
555h
AAAh
Fast
Program *
1
Word
2
XXXh
A0h
PA
PD
--
--
--
--
--
--
--
--
Byte
XXXh
Reset from
Fast Mode *
1
Word
2
BA
90h
XXXh
*
4
F0h
--
--
--
--
--
--
--
--
Byte
BA
XXXh
Query
Word
1
(BA)
55h
98h
--
--
--
--
--
--
--
--
--
--
Byte
(BA)
AAh
HiddenROM
Entry
Word
3
555h
AAh
2AAh
55h
555h
88h
--
--
--
--
--
--
Byte
AAAh
555h
AAAh
HiddenROM
Program *
3
Word
4
555h
AAh
2AAh
55h
555h
A0h
(HRA)
PA
PD
--
--
--
--
Byte
AAAh
555h
AAAh
HiddenROM
Exit *
3
Word
4
555h
AAh
2AAh
55h
(HRBA)
555h
90h
XXXh
00h
--
--
--
--
Byte
AAAh
555h
(HRBA)
AAAh
MB84VD23280FA
-70
19
(Continued)
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET = V
ID
.
*3: This command is valid while HiddenROM mode.
*4: The data "00h" is also acceptable.
Notes :
Address bits A
21
to A
11
= X = "H" or "L" for all address commands except or Program Address (PA),
Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).
Bus operations are defined.
RA
=
Address of the memory location to be read
PA
=
Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA
=
Address of the sector to be erased. The combination of A
21
, A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and
A
12
will uniquely select any sector.
BA
=
Bank Address (A
21
, A
20
, A
19
)
RD
=
Data read from location RA during read operation.
PD
=
Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SPA
=
Sector group address to be protected. Set sector group address and (A
6
, A
3
, A
2
, A
1
, A
0
) =
(0, 0, 0, 1, 0).
SD
=
Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
HRA
=
Address of the HiddenROM area Word Mode : 000000h to 00007Fh
Byte Mode : 000000h to 0000FFh
HRBA
=
Bank Address of the HiddenROM area (A
21
= A
20
= A
19
= V
IL
)
The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A
10
to A
0
Byte Mode: AAAh or 555h to addresses A
10
to A
0
, and A
-1
Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
MB84VD23280FA
-70
20
s
s
s
s
ABSOLUTE MAXIMUM RATINGS
*1 Minimum DC voltage on input or I/O pins is 0.3 V. During voltage transitions, input or I/O pins may undershoot
V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V
CC
f + 0.3 V or V
CC
s + 0.3
V. During voltage transitions, input or I/O pins may overshoot to V
CC
f + 2.0 V or V
CC
s + 2.0 V for periods of up to
20 ns.
*2: Minimum DC input voltage on RESET pin is 0.5 V. During voltage transitions, RESET pins may undershoot V
SS
to 2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (V
IN
-V
CC
f or V
CC
s) does
not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for
periods of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is 0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when V
CC
f is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s
s
s
s
RECOMMENDED OPERATING CONDITIONS
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Min
Max
Storage Temperature
Tstg
55
+125
C
Ambient Temperature with Power Applied
Ta
40
+85
C
Voltage with Respect to Ground All pins
except RESET,WP/ACC *
1
V
IN
, V
OUT
0.3
V
CC
f +0.3
V
V
CC
s +0.3
V
V
CC
f/V
CC
s Supply *
1
V
CC
f, V
CC
s
0.3 +3.3
V
RESET *
2
V
IN
0.5
+ 13.0
V
WP/ACC *
3
V
IN
0.5
+10.5
V
Parameter
Symbol
Value
Unit
Min
Max
Ambient Temperature
Ta
40
+85
C
V
CC
f/V
CC
s Supply Voltages
V
CC
f, V
CC
s
+2.7
+3.1
V
MB84VD23280FA
-70
21
s
s
s
s
ELECTRICAL CHARACTERISTICS
1.
DC Characteristics
(Continued)
Parameter
Symbol
Conditions
Value
Unit
Min
Typ
Max
Input Leakage Current
I
LI
V
IN
= V
SS
to V
CC
f, V
CC
s
1.0
--
+1.0
A
Output Leakage Current
I
LO
V
OUT
= V
SS
to V
CC
f, V
CC
s
1.0
--
+1.0
A
RESET Inputs Leakage
Current
I
LIT
V
CC
f
= V
CC
f Max, V
CC
s
= V
CC
s Max,
RESET = 12.5 V
--
--
35
A
A
CC
Input Leakage Current
I
LIA
V
CC
f
= V
CC
f Max, V
CC
s
= V
CC
s Max,
WP/ACC = V
ACC
Max
--
--
20
mA
Flash V
CC
Active Current
(Read) *
1
I
CC1
f
CEf = V
IL
,
OE = V
IH
t
CYCLE
= 5 MHz Byte
--
--
16
mA
t
CYCLE
= 5 MHz Word
--
--
18
t
CYCLE
= 1 MHz Byte
--
--
4
mA
t
CYCLE
= 1 MHz Word
--
--
4
Flash V
CC
Active Current*
2
I
CC2
f
CEf = V
IL
, OE = V
IH
--
--
30
mA
Flash V
CC
Active Current
(Read-While-Program) *
5
I
CC3
f
CEf = V
IL
, OE = V
IH
Byte
--
--
46
mA
Word
--
--
48
Flash V
CC
Active Current
(Read-While-Erase) *
5
I
CC4
f
CEf = V
IL
, OE = V
IH
Byte
--
--
46
mA
Word
--
--
48
Flash V
CC
Active Current
(Erase-Suspend-Program)
I
CC5
f
CEf = V
IL
, OE = V
IH
--
--
30
mA
SRAM V
CC
Active Current
I
CC1
s
V
CC
s = V
CC
s Max,
CE1s = V
IL
,
CE2s = V
IH
t
CYCLE
= 10 MHz
--
--
50
mA
SRAM V
CC
Active Current
I
CC2
s
CE1s = 0.2 V,
CE2s =
V
CC
s 0.2 V
t
CYCLE
= 10 MHz
--
--
50
mA
t
CYCLE
= 1 MHz
--
--
10
mA
Flash V
CC
Standby Current
I
SB1
f
V
CC
f = V
CC
f Max, CEf = V
CC
f 0.3 V
RESET = V
CC
f 0.3 V,
WP/ACC = V
CC
f 0.3 V
--
1
5
A
Flash V
CC
Standby Current
(RESET)
I
SB2
f
V
CC
f = V
CC
f Max, RESET = V
SS
0.3 V,
WP/ACC = V
CC
f 0.3 V
--
1
5
A
Flash V
CC
Current
(Automatic Sleep Mode) *
3
I
SB3
f
V
CC
f = V
CC
f Max, CEf = V
SS
0.3 V
RESET = V
CC
f 0.3 V,
WP/ACC = V
CC
f 0.3 V,
V
IN
= V
CC
f 0.3 V or V
SS
0.3 V
--
1
5
A
SRAM V
CC
Standby
Current
I
SB1
s
CE1s > V
CC
s 0.2 V, CE2s > V
CC
s 0.2 V
--
--
15
A
SRAM V
CC
Standby
Current
I
SB2
s
CE2s < 0.2V
--
--
15
A
MB84VD23280FA
-70
22
(Continued)
*1: The I
CC
current listed includes both the DC operating current and the frequency dependent component.
*2: I
CC
active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only V
CC
f applying.
*5: Embedded Alogorithm (program or erase) is in progress. (@5 MHz)
*6: V
CC
indicates lower of V
CC
f or V
CC
s.
Parameter
Symbol
Conditions
Value
Unit
Min
Typ
Max
Input Low Level
V
IL
--
0.3
--
0.5
V
Input High Level
V
IH
--
2.4
--
V
CC
+0.3
*
6
V
Voltage for Sector Protection,
and Temporary Sector Unpro-
tection (RESET) *
4
V
ID
--
11.5
12
12.5
V
Voltage for Program
Acceleration (WP/ACC) *
4
V
ACC
--
8.5
9.0
9.5
V
Output Low Voltage Level
V
OL
V
CC
f = V
CC
f Min, I
OL
= 4.0 mA
Flash
--
--
0.45
V
V
CC
s = V
CC
s Min, I
OL
= 1.0 mA SRAM
--
--
0.4
V
Output High Voltage Level
V
OH
V
CC
f = V
CC
f Min, I
OH
= 0.1 mA Flash
0.85
V
CC
f
--
--
V
V
CC
s = V
CC
s Min, I
OH
= 0.5 mA
SRAM
2.2
--
--
V
Flash Low V
CC
f Lock-Out
Voltage
V
LKO
--
2.3
2.4
2.5
V
MB84VD23280FA
-70
23
2.
AC Characteristics
CE Timing
Timing Diagram for alternating SRAM to Flash
Parameter
Symbol
Condition
Value
Unit
JEDEC
Standard
Min
Max
CE Recover Time
--
t
CCR
--
0
--
ns
CE Hold Time
--
t
CHOLD
--
3
--
ns
CEf
t
CCR
t
CCR
CE1s
CE2s
t
CCR
t
CCR
WE
t
CHOLD
t
CHOLD
MB84VD23280FA
-70
24
Read Only Operations Characteristics (Flash)
*: Test Conditions Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to V
CC
f
Timing measurement reference level
Input: 0.5V
CC
f
Output: 0.5V
CC
f
Parameter
Symbol
Condition
Value*
Unit
JEDEC
Standard
Min
Max
Read Cycle Time
t
AVAV
t
RC
--
70
--
ns
Address to Output Delay
t
AVQV
t
ACC
CEf = V
IL
OE = V
IL
--
70
ns
Chip Enable to Output Delay
t
ELQV
t
CE
f
OE = V
IL
--
70
ns
Output Enable to Output Delay
t
GLQV
t
OE
--
--
30
ns
Chip Enable to Output High-Z
t
EHQZ
t
DF
--
--
25
ns
Output Enable to Output High-Z
t
GHQZ
t
DF
--
--
25
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
t
AXQX
t
OH
--
0
--
ns
RESET Pin Low to Read Mode
--
t
READY
--
--
20
s
MB84VD23280FA
-70
25
Read Cycle (Flash)
WE
OE
CEf
t
CE
f
t
OE
DQ
Addresses Stable
High-Z
Output Valid
High-Z
t
OEH
t
ACC
t
RC
RESET
t
ACC
t
OH
DQ
t
RC
Addresses Stable
High-Z
Output Valid
t
RH
t
DF
Address
Address
t
RH
t
CE
f
t
RP
CEf
MB84VD23280FA
-70
26
Write/Erase/Program Operations
(Continued)
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
Write Cycle Time
t
AVAV
t
WC
70
ns
Address Setup Time
t
AVWL
t
AS
0
ns
Address Setup Time to OE Low During Toggle Bit
Polling
t
ASO
12
ns
Address Hold Time
t
WLAX
t
AH
45
ns
Address Hold Time from CE or OE High During
Toggle Bit Polling
t
AHT
0
ns
Data Setup Time
t
DVWH
t
DS
30
ns
Data Hold Time
t
WHDX
t
DH
0
ns
Output
Enable Hold
Time
Read
t
OEH
0
ns
Toggle and Data
Polling
10
ns
CE High During Toggle Bit Polling
t
CEPH
20
ns
OE High During Toggle Bit Polling
t
OEPH
20
ns
Read Recover Time Before Write
t
GHWL
t
GHWL
0
ns
Read Recover Time Before Write
t
GHEL
t
GHEL
0
ns
CE Setup Time
t
ELWL
t
CS
0
ns
WE Setup Time
t
WLEL
t
WS
0
ns
CE Hold Time
t
WHEH
t
CH
0
ns
WE Hold Time
t
EHWH
t
WH
0
ns
Write Pulse Width
t
WLWH
t
WP
35
ns
CE Pulse Width
t
ELEH
t
CP
35
ns
Write Pulse Width High
t
WHWL
t
WPH
25
ns
CE Pulse Width High
t
EHEL
t
CPH
25
ns
Programming Operation
Byte
t
WHWH1
t
WHWH1
4
s
Word
6
s
Sector Erase Operation *
1
t
WHWH2
t
WHWH2
0.5
s
V
CC
Setup Time
t
VCS
50
s
Rise Time to V
ID
*
2
t
VIDR
500
ns
Rise Time to V
ACC
*
3
t
VACCR
500
ns
Voltage Transition Time *
2
t
VLHT
4
s
Write Pulse Width *
2
t
WPP
100
s
MB84VD23280FA
-70
27
(Continued)
*1: This does not include preprogramming time.
*2: This timing is for Sector Group Protection operation.
*3: This timing is for Accelerated Program operation.
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
OE Setup Time to WE Active *
2
t
OESP
4
s
CE Setup Time to WE Active *
2
t
CSP
4
s
Recover Time from RY/BY
t
RB
0
ns
RESET Pulse Width
t
RP
500
ns
RESET High Level Period Before Read
t
RH
200
ns
BYTE Switching Low to Output High-Z
t
FLQZ
30
ns
BYTE Switching High to Output Active
t
FHQV
70
ns
Program/Erase Valid to RY/BY Delay
t
BUSY
90
ns
Delay Time from Embedded
Output Enable
t
EOE
70
ns
Erase Time-out Time
t
TOW
50
s
Erase Suspend Transition Time
t
SPD
20
s
MB84VD23280FA
-70
28
Write Cycle (WE control) (Flash)
t
CH
t
WP
t
WHWH1
t
WC
t
AH
CEf
OE
t
RC
DQ
t
AS
t
OE
t
WPH
t
GHWL
t
DH
DQ
7
PD
A0h
D
OUT
WE
555h
PA
PA
t
OH
Data Polling
3rd Bus Cycle
t
CS
t
CE
f
t
DS
D
OUT
Address
Notes :
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the
16 mode. (The addresses differ from
8
mode.)
MB84VD23280FA
-70
29
Write Cycle (CEf control) (Flash)
Notes :
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the
16 mode. (The addresses differ from
8
mode.)
t
CP
t
DS
t
WHWH1
t
WC
t
AH
WE
OE
DQ
t
AS
t
CPH
t
DH
DQ
7
A0h
D
OUT
CEf
555h
PA
PA
Data Polling
3rd Bus Cycle
t
WS
t
WH
t
GHEL
PD
Address
MB84VD23280FA
-70
30
AC Waveforms Chip/Sector Erase Operations (Flash)
Address
V
CC
f
CEf
OE
DQ
WE
555h
2AAh
555h
555h
2AAh
SA*
t
DS
t
CH
t
AS
t
AH
t
CS
t
WPH
t
DH
t
GHWL
t
VCS
t
WC
t
WP
AAh
55h
80h
AAh
55h
10h/
30h for Sector Erase
30h
*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
Note: These waveforms are for the
16 mode. (The addresses differ from
8
mode.)
MB84VD23280FA
-70
31
AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
*: DQ
7
= Valid Data (The device has completed the Embedded operation.)
t
OEH
t
OE
CEf
OE
WE
DQ
7
t
DF
t
CH
t
CE
f
DQ
7
=
Valid Data
DQ
7
*
DQ
6
to DQ
0
= Output Flag
t
EOE
DQ
6
to DQ
0
Valid Data
High-Z
High-Z
DQ
6
to DQ
0
Data In
Data In
t
BUSY
RY/BY
t
WHWH1 or
t
WHWH2
MB84VD23280FA
-70
32
AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
*: DQ
6
stops toggling (The device has completed the Embedded operation).
Address
RY/BY
CEf
WE
DQ
6
/DQ
2
OE
t
AS
t
BUSY
Toggle
t
AHT
t
AHT
t
ASO
t
OEH
t
OEH
t
OE
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Data
t
CE
f
*
Output
Valid
t
DH
t
CEPH
t
OEPH
MB84VD23280FA
-70
33
Bank-to-bank Read/Write Timing Diagram (Flash)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
CEf
DQ
WE
Address
BA1
BA1
BA1
BA2
(555h)
BA2
(PA)
OE
Valid
Output
Valid
Output
Valid
Output
Status
Valid
Intput
Valid
Intput
t
RC
t
RC
t
RC
t
RC
t
WC
t
WC
t
AHT
t
AS
t
AS
t
AH
t
ACC
t
CE
t
OE
t
OEH
t
WP
t
GHWL
t
DS
t
DF
t
DH
t
DF
t
CEPH
Read
Command
Command
Read
Read
Read
(A0h)
(PD)
BA2
(PA)
MB84VD23280FA
-70
34
RY/BY Timing Diagram during Write/Erase Operations (Flash)
RESET, RY/BY Timing Diagram (Flash)
Rising edge of the last write pulse
CEf
RY/BY
WE
t
BUSY
Entire programming
or erase operations
t
RP
RESET
t
READY
RY/BY
WE
t
RB
MB84VD23280FA
-70
35
Temporary Sector Unprotection (Flash)
Acceleration Mode Timing Diagram (Flash)
V
CC
f
V
ID
RESET
V
IH
CEf
WE
RY/BY
Program or Erase Command Sequence
t
VIDR
t
VLHT
t
VCS
t
VLHT
t
VLHT
Unprotection Period
3V
V
CC
f
V
ACC
WP/ACC
V
CC
CEf
WE
RY/BY
t
VACCR
t
VLHT
t
VCS
t
VLHT
t
VLHT
Acceleration Mode Period
MB84VD23280FA
-70
36
Extended Sector Group Protection (Flash)
SPAX: Sector Group Address to be protected
SPAY : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250
s (Min)
SPAY
RESET
OE
WE
CEf
Data
A
1
V
CC
f
A
6
, A
3
, A
2
, A
0
Address
SPAX
SPAX
60h
01h
40h
60h
60h
TIME-OUT
t
VCS
t
VLHT
t
VIDR
t
OE
t
WP
t
WC
t
WC
MB84VD23280FA
-70
37
s
s
s
s
8M SRAM CHARACTERISTICS for MCP
Read Cycle (SRAM)
Note: Test ConditionsOutput Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 0.5
V
CC
s
Output: 0.5
V
CC
s
Parameter
Symbol
Value
Unit
Min
Max
Read Cycle Time
t
RC
70
--
ns
Address Access Time
t
AA
--
70
ns
Chip Enable (CE1s) Access Time
t
CO1
--
70
ns
Chip Enable (CE2s) Access Time
t
CO2
--
70
ns
Output Enable Access Time
t
OE
--
35
ns
LB, UB to Output Valid
t
BA
--
70
ns
Chip Enable (CE1s Low and CE2s High) to Output Active
t
COE
5
--
ns
Output Enable Low to Output Active
t
OEE
0
--
ns
LB, UB Enable Low to Output Active
t
BE
0
--
ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z
t
OD
--
25
ns
Output Enable High to Output High-Z
t
ODO
--
25
ns
LB, UB Output Enable to Output High-Z
t
BD
--
25
ns
Output Data Hold Time
t
OH
10
--
ns
MB84VD23280FA
-70
38
Read Cycle (SRAM)
t
RC
t
AA
t
OH
t
CO1
t
OD
t
ODO
t
OEE
t
COE
Valid Data Out
Address
CE1s
OE
DQ
CE2s
t
COE
t
OE
t
CO2
t
OD
LB, UB
t
BA
t
BD
t
BE
Note: WE remains HIGH for the read cycle.
MB84VD23280FA
-70
39
Write Cycle (SRAM)
Parameter
Symbol
Value
Unit
Min
Max
Write Cycle Time
t
WC
70
--
ns
Write Pulse Width
t
WP
50
--
ns
Chip Enable to End of Write
t
CW
55
--
ns
Address valid to End of Write
t
AW
55
--
ns
LB, UB to End of Write
t
BW
55
--
ns
Address Setup Time
t
AS
0
--
ns
Write Recovery Time
t
WR
0
--
ns
WE Low to Output High-Z
t
ODW
--
25
ns
WE High to Output Active
t
OEW
0
--
ns
Data Setup Time
t
DS
30
--
ns
Data Hold Time
t
DH
0
--
ns
MB84VD23280FA
-70
40
Write Cycle *
3
(WE control) (SRAM)
t
WC
t
AS
t
WP
t
WR
t
CW
t
ODW
t
OEW
t
DS
t
DH
Valid Data In
Address
WE
CE1s
D
OUT
D
IN
CE2s
t
CW
*1 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain
at high impedance.
*2 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain
at high impedance.
*3 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not
be applied.
*1
*4
*2
*4
t
BW
LB, UB
t
AW
MB84VD23280FA
-70
41
Write Cycle *
1
(CE1s control) (SRAM)
t
WC
t
AS
t
WP
t
WR
t
CW
t
ODW
t
COE
t
DS
t
DH
Valid Data In
Address
WE
CE1s
D
OUT
D
IN
CE2s
t
CW
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
*2
LB, UB
t
BW
t
BE
t
AW
MB84VD23280FA
-70
42
Write Cycle *
1
(CE2s Control) (SRAM)
t
WC
t
AS
t
WP
t
WR
t
CW
t
ODW
t
COE
t
DS
t
DH
Valid Data In
Address
WE
CE1s
D
OUT
D
IN
CE2s
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
*2
t
CW
LB, UB
t
BW
t
BE
t
AW
MB84VD23280FA
-70
43
Write Cycle *
1
(LB, UB Control) (SRAM)
t
WC
t
DS
t
DH
Address
LB, UB
WE
D
IN
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
t
WP
CE2s
t
CW
CE1s
t
AS
t
WR
t
BW
t
ODW
t
COE
D
OUT
t
BE
Valid Data In
*2
t
CW
t
AW
MB84VD23280FA
-70
44
s
s
s
s
ERASE AND PROGRAMMING PERFORMANCE (Flash)
Note : Typical Erase conditions T
A
=
+
25C, VCCf_1 & VCCf_2 = 2.9 V
Typical Program conditions T
A
=
+
25C, VCCf_1 & VCCf_2 = 2.9 V Data= Checker
s
s
s
s
DATA RETENTION CHARACTERISTICS
(SRAM)
Note : t
RC
: Read cycle time
CE1s Controlled Data Retention Mode *
1
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to V
CC
s0.2 V or V
SS
to
0.2 V during data retention mode. Other input and input/output pins can be used between 0.3 V to V
CC
s+0.3 V.
*2 : When CE1s is operating at the V
IH
Min level, the standby current is given by I
SB1
s during the transition
of V
CC
s from Vccs Max to V
IH
Min level.
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector Erase Time
--
0.5
2
s
Excludes programming time
prior to erasure
Word Programming Time
--
6
100
s
Excludes system-level
overhead
Byte Programming Time
--
4
80
s
Excludes system-level
overhead
Chip Programming Time
--
25.2
95
s
Excludes system-level
overhead
Erase/Program Cycle
100,000
--
--
cycle
Parameter
Symbol
Value
Unit
Min
Typ
Max
Data Retention Supply Voltage
V
DH
1.5
--
3.1
V
Standby Current
V
DH
= 3.0 V
I
DDS2
--
--
15
A
Chip Deselect to Data Retention Mode Time
t
CDR
0
--
--
ns
Recovery Time
t
R
t
RC
--
--
ns
V
CC
s
2.7 V
V
IH
V
SS
DATA RETENTION MODE
*2
t
CDR
CE1s
V
CCS
0.2 V
*2
t
R
V
DH
MB84VD23280FA
-70
45
CE2s Controlled Data Retention Mode *
* : In CE2s controlled data retention mode, input and input/output pins can be used between
0.3 V to Vccs+0.3V.
s
s
s
s
PIN CAPACITANCE
Note: Test conditions Ta =
+
25C, f = 1.0 MHz
s
s
s
s
HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
s
s
s
s
CAUTION
(1) The high voltage (V
ID
) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (V
ID
) to specific pins.
(2) For the sector protection, since the high voltage (V
ID
) can be applied to the RESET, it can be protected the
sector useing "Extended sector protect" command.
Parameter
Symbol
Test Setup
Value
Unit
Typ
Max
Input Capacitance
C
IN
V
IN
= 0
11
14
pF
Output Capacitance
C
OUT
V
OUT
= 0
12
16
pF
Control Pin Capacitance
C
IN2
V
IN
= 0
14
16
pF
WP/ACC Pin Capacitance
C
IN3
V
IN
= 0
21.5
26
pF
V
CC
s
2.7 V
V
SS
DATA RETENTION MODE
V
IH
V
IL
CE2s
t
CDR
t
R
0.2 V
V
DH
MB84VD23280FA
-70
46
s
s
s
s
ORDERING INFORMATION
MB84VD23280 FA -70 PBS
DEVICE NUMBER/DESCRIPTION
64 Mega-bit (8M
16-bit or 4M
16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
8 Mega-bit(1M
8-bit or 512K
16-bit) SRAM
PACKAGE TYPE
PBS = 65-ball FBGA
SPEED OPTION
See Product Selector Guide
Device Revision
MB84VD23280FA
-70
47
s
s
s
s
PACKAGE DIMENSION
65-pin plastic FBGA
(BGA-65P-M01)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2001 FUJITSU LIMITED B65001S-c-1-2
9.000.10(.354.004)
9.000.10
(.354.004)
INDEX-MARK AREA
0.10(.004)
0.390.10
(.015.004)
(Stand off)
.047
.004
+.006
0.10
+0.15
1.19
(Seated height)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
7
8
9
10
65-
.018
.002
+.004
0.05
+0.10
65-
0.45
M
0.08(.003)
0.20(.008) S A
S
S
0.80(.031)
0.40(.016)
REF
REF
0.80(.031)
REF
REF
0.40(.016)
A
B
S A
S
0.10(.004)
B
S
0.20(.008)
B
INDEX BALL
MB84VD23280FA
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