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Publication Number S25FL004A_00 Revision A Amendment 1 Issue Date March 28, 2005
ADVANCE
INFORMATION
S25FL Family (Serial Peripheral Interface)
S25FL004A
4-Megabit CMOS 3.0 Volt Flash Memory
with 50 Mhz SPI Bus Interface
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
-- Full voltage range: 2.7 to 3.6 V read and program
operations
Memory Architecture
-- Eight sectors with 512 Kb each
Program
-- Page Program (up to 256 bytes) in 1.5 ms (typical)
-- Program cycles are on a page by page basis
Erase
-- 1.5 s typical sector erase time
-- 12 s typical bulk erase time
Cycling Endurance
-- 100,000 cycles per sector typical
Data Retention
-- 20 years typical
Device ID
-- JEDEC standard two-byte electronic signature
-- RES instruction one-byte electronic signature for
backward compatibility
Process Technology
-- Manufactured on 0.20 m MirrorBit
TM
process
technology
Package Option
-- Industry Standard Pinouts
-- 8-pin SO package (208 mils)
-- 8-Contact USON Package (5 x 6 mm), Pb-Free
Performance Characteristics
Speed
-- 50 MHz clock rate (maximum)
Power Saving Standby Mode
-- Standby Mode 50 A (max)
-- Deep Power Down Mode 1 A (typical)
Memory Protection Features
Memory Protection
-- W# pin works in conjunction with Status Register Bits
to protect specified memory areas
-- Status Register Block Protection bits (BP2, BP1, BP0)
in status register configure parts of memory as read-
only
Software Features
SPI Bus Compatible Serial Interface
3
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. S25FL Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Description .....................................................................................8
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1. Bus Master and Memory Devices on the SPI Bus........................................... 9
Figure 2. SPI Modes Supported............................................................................................. 9
Operating Features . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Programming..................................................................................10
Sector Erase, or Bulk Erase .................................................................10
Polling During a Write, Program, or Erase Cycle ........................10
Status Register .........................................................................................10
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Protected Area Sizes (S25FL004A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Hold Condition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Hold Condition Activation................................................................................... 12
Memory Organization . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Sector Address Table S25FL004A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. Write Enable (WREN) Instruction Sequence................................................ 15
Write Disable (WRDI)...........................................................................16
Figure 5. Write Disable (WRDI) Instruction Sequence................................................ 16
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 6. Read Status Register (RDSR) Instruction Sequence.................................... 17
Figure 7. Status Register Format.......................................................................................... 17
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Write Status Register (WRSR) Instruction Sequence ................................ 18
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Read Data Bytes (READ) Instruction Sequence.......................................... 20
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . 20
Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence 21
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
21
Table 6. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . .22
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12. Page Program (PP) Instruction Sequence ..................................................... 23
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 13. Sector Erase (SE) Instruction Sequence ........................................................ 24
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 14. Bulk Erase (BE) Instruction Sequence............................................................ 25
Deep Power Down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 15. Deep Power Down (DP) Instruction Sequence ......................................... 26
Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . .26
Figure 16. Release from Deep Power Down Instruction Sequence......................... 27
Release from Deep Power Down and Read Electronic Signature
(RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) In-
struction Sequence.................................................................................................................. 28
Power-up and Power-down . . . . . . . . . . . . . . . . . . 28
Figure 18. Power-Up Timing................................................................................................. 29
Table 7. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . 29
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 29
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 19. AC Measurements I/O Waveform .................................................................. 31
Table 9. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 20. SPI Mode 0 (0,0) Input Timing......................................................................... 33
Figure 21. SPI Mode 0 (0,0) Output Timing...................................................................... 33
Figure 22. HOLD# Timing.................................................................................................... 34
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 34
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 35
S08 wide--8-pin Plastic Small Outline 208 mils Body Width Pack-
age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
USON 8L (5x6mm) No-Lead Package . . . . . . . . . . . . . . . . . . .36
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 37
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