Swindon Silicon Systems Limited
August 95
- 1 -
SSSB153
STM16 - STM1 DeMultiplexer
SDH Product Range
16 bit parallel STM16 input
ECL 100k compatible STM16 interface
Interfaces with SSSB149
Four 75
differential STM1 outputs
155.52MBit/s NRZ or 311.04 MBaud CMI
serial data output format
Built in scrambling and parity circuits
TTL I/O for control interface
High performance Silicon Bipolar process
Twin power supply (-5V & +5V)
Low dissipation (2.5W)
68 pin J-leaded ceramic package with heat sink
Meets ITU-T Recommendations
STM16 - STM1 DEMULTIPLEXER
FEATURES
The SSSB153 accepts data as STM16 frames in 16 bit parallel form at a clock speed of 155MHz, and has 4 differential
75
output channels. The output channels carry STM1 frames in bit serial form in either 155MBit/s NRZ or 311 MBaud
CMI format. Each output channel can be any one of the 16 STM1 frames contained in the STM16 input frame.
The device includes circuits to monitor frame detect failure and control the SSSB149 synchronisation logic, circuits to
perform parity checking and descrambling of the STM16 input frames, and circuits for parity generation, scrambling
and CMI code conversion of the STM1 serial output frames
The SSSB153 has a TTL compatible control interface which is used for STM1 frame selection to the 4 output channels,
and for access to the parity checking circuit.
FUNCTIONAL OVERVIEW
SSSB153
DATE CODE
GND
VEE
CMIB
SCROB
POUT
DATAIO(0)
DATAIO(1)
VEE
DATAIO(2)
DATAIO(3)
GND
VCC
RDB
ALE
WRB
VEE
GND
GND
CMI1B
GND
CMI1
VEE
CMI2
GND
CMI2B
VEE
CMI3B
GND
CMI3
VEE
CMI4
GND
CMI4B
GND
STM16(1)
RSET
GND
CK
CKB
VEE
GND
STM16(0)
STM16(2)
STM16(3)
STM16(4)
STM16(5)
STM16(6)
STM16(7)
VEE
GND
VEE
GND
STM16(9)
STM16(10)
STM16(11)
STM16(12)
STM16(13)
STM16(14)
STM16(15)
VEE
OHW
GND
FP
B1ENB
SCRIB
N/C
GND
STM16(8)
The SSSB153 receives STM16 frames in 2 byte parallel form, and sends out selected STM1 frames in bit serial form.
Each SSSB153 selects up to four STM1 frames out of the incoming STM16 frame. Up to four SSSB153 devices,
together with an SSSB149, are used to form a complete 2.5 GHz STM16 to STM1 demultiplexer for SDH
communication applications.
SSSB153
STM16 - STM1 DeMultiplexer
- 2 -
Swindon Silicon Systems Limited
August 95
Block Diagram
STM16
(0:7)
CK
CKB
TIMING GENERATOR AND
FRAME PERSISTENCE COUNTER
INPUT REGISTERS
OHW
FUNCTIONAL DESCRIPTION
STM16 Interface
The SSSB153 accepts data as STM16 frames in 16 bit parallel form at a clock speed of 155MHz. The STM16
interface into the SSSB153 is designed to work with the Swindon Silicon Systems SSSB149 16 : 1 bit demultiplexer
device. Data is clocked into the SSSB153 Input Register from the 155MHz differential clock inputs CK and CKB.
Data is clocked in on the rising edge of CK, the falling edge of CKB.
The S4 and S4B outputs from the SSSB149 are suitable for driving the CK and CKB inputs of the SSSB153
respectively. Note that each SSSB149 can drive up to 4 SSSB153 devices.
DESCRAMBLER
BYTE REORDER
16 : 4
CR
OSSPOINT SWITCH
PARITY
PARITY
PARITY
PARITY
CMI
CMI
CMI
CMI
CMI1B
CMI1
CMI2B
CMI2
CMI3B
CMI3
CMI4
CMI4B
FP
STM16
(8:15)
SCRAMBLER
SCRIB B1ENB POUT
ALE
WRB
DATAIO
(3:0)
RDB
SCROB
CMIB
PARITY
CHECKER
CONTROL
REGISTERS
SSSB153
STM16 - STM1 DeMultiplexer
- 3 -
Swindon Silicon Systems Limited
August 95
Input Timing Diagram
CK
CKB
FP
STM16
STM1
OUTPUTS
SSSB153
SSSB153
SSSB149
Clock
Data
2.5 GHz
CLOCK
RECOVERY
2.5GHz
STM16
OHW
Full STM16 - STM1 DeMultiplexer
t
ds
t
dh
t
fh
t
fs
CK
CKB
FP
STM16
S4
S4B
D(15:0)
CK
CKB
STM16
FP
FP
SSSB153
CK
CKB
STM16
FP
SSSB153
CK
CKB
STM16
FP
(15:0)
(15:0)
(15:0)
(15:0)
Application
SSSB153
STM16 - STM1 DeMultiplexer
- 4 -
Swindon Silicon Systems Limited
August 95
The SSSB153 timing circuit includes a Frame Persistence Counter. The purpose of this counter is to determine
whether the devices are correctly synchronised to the serial data stream at the SSSB149 input. The Frame
Persistence Counter is a 3 bit counter, i.e. it stores count values of 0 to 7.
When the Frame Persistence Counter is at 0, the SSSB149 and SSSB153 devices are assumed to be not synchronised
to the serial data stream. In this condition, the OverHead Window (OHW) signal is held continuously high. With
OHW high, the SSSB149 will search its input serial data stream, and generate a frame pulse (FP) whenever a
synchronisation pattern occurs in the data stream. When the SSSB153 receives a frame pulse, the Frame Persistence
counter will increment to '1', the OHW output will be reset low, and the internal timing generator will be reset.
Frame Pulse and Overhead Window Timing
STM16 Frame
SERIAL
DATA
FP from
SSSB149
FPC
Frame synchronisation
Frame synchronisation, i.e. the alignment of the parallel STM16 frame to the high speed serial input data stream, is
achieved by the SSSB149. In ITU-T applications, the SSSB149 will synchronise onto the A1A2 word in the serial
input data stream whenever the OHW signal is high. As the SSSB149 achieves synchronisation, it generates a frame
pulse (FP) which is sent to each SSSB153. Upon receipt of the frame pulse, the SSSB153 drives the OHW signal
low for almost one complete STM16 frame. This puts the SSSB149 into locked mode for most of the STM16 frame
and prevents the SSSB149 from attempting to synchronise onto A1A2 words elsewhere in the STM16 frame. Note
that in applications with multiple SSSB153 devices driven by a single SSSB149 device, only one SSSB153 OHW
output is used to drive the SSSB149 OHW input.
OHW from
SSSB153
1
2
3
7
SSSB153
STM16 - STM1 DeMultiplexer
- 5 -
Swindon Silicon Systems Limited
August 95
Frame Persistence Counter Sequence
When the Frame Persistence Counter value is between 1 and 7, the internal timing generator will generate a narrow
high going pulse on the OHW output once every STM16 frame. (An STM16 frame length is 16x2430 bytes, or
19,440 cycles of the 155MHz clock, or 125
s.) If the devices are correctly synchronised, OHW will pulse high for
eight cycles of the 155MHz clock, starting three cycles before the expected position of the A1A2 word in the serial
data stream. This timing of the OHW pulse will allow the SSSB149 to recognise and lock on to the sync word. If
the sync word is recognised during an OHW pulse, the SSSB149 sends further Frame Pulses back to the SSSB153.
Each frame pulse received by the SSSB153 during the OHW pulse will increment the Frame Persistence Counter
in the sequence 0 - 1 - 2 - 3, then one more FP causes the counter to jump to 7. If a frame pulse is not received
during the OHW pulse, the SSSB153 continues as if it were still synchronised, i.e. the OHW output is still pulsed
high once per STM16 frame, but the Frame Persistence Counter decrements in the sequence 7 - 6 - 5 - 4 - 3 - 2 - 1
- 0 (no jumps). When the counter reaches the value 0, a frame sync loss is recognised, and the OHW output is held
continuously high, allowing the SSSB149 to resume the search for the sync word in the serial data stream.
If the Frame Persistence Counter value is between 1 and 7 but the devices are not correctly synchronised, either
because the serial data stream or its timing was changed or corrupted, or because the SSSB149 generated a spurious
frame pulse, then the OHW pulse will not be at the start of the incoming serial STM16 frame. The A1A2 sync word
will occur only occasionally during these incorrectly timed OHW pulses, so few frame pulses will be generated and
the Frame Persistence Counter will quickly decrement to zero, thus allowing the SSSB149 to resume the search
until it captures the sync word at the start of the STM16 frame. In practice, the search will quickly move through
the payload section of the STM16 frame, and home in on the correct position at the start of the STM16 frame.
0
1
2
3
4
5
6
7
Increment Sequence
Decrement Sequence
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