6/01

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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

FEATURES:

Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

Single Voltage Read and Write Operations

3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040

Superior Reliability

Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 10 mA (typical)
Standby Current: 1 µA (typical)

Sector-Erase Capability

Uniform 4 KByte sectors

Fast Read Access Time:

45 ns for SST39LF512/010/020/040
55 ns for SST39LF020/040
70 and 90 ns for SST39VF512/010/020/040

Latched Address and Data

Fast Erase and Byte-Program:

Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:

1 second

(typical) for SST39LF/VF512

2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040

Automatic Write Timing

Internal V

Generation

End-of-Write Detection

Toggle Bit
Data# Polling

CMOS I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-lead PLCC
32-lead TSOP (8mm x 14mm)
48-ball TFBGA (6mm x 8mm) for 1 Mbit

PRODUCT DESCRIPTION

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8
CMOS Multi-Purpose Flash (MPF) manufactured with
SST's proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF512/
010/020/040 devices write (Program or Erase) with a 3.0-
3.6V power supply. The SST39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the
SST39LF512/010/020/040 and SST39VF512/010/020/
040 devices provide a maximum Byte-Program time of 20
µsec. These devices use Toggle Bit or Data# Polling to indi-
cate the completion of Program operation. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, they
are offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices are suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. For all system applications, they

significantly improves performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program oper-
ation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.

To meet surface mount requirements, the SST39LF512/
010/020/040 and SST39VF512/010/020/040 devices are
offered in 32-lead PLCC and 32-lead TSOP packages. The
39LF/VF010 is also offered in a 48-ball TFBGA package.
See Figures 1 and 2 for pinouts.

SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

S71150-03-000

6/01

395

Device Operation

Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39LF512/010/020/040 and
SST39VF512/010/020/040 device is controlled by CE#
and OE#, both have to be low for the system to obtain data
from the outputs. CE# is used for device selection. When
CE# is high, the chip is deselected and only standby power
is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. Refer to the
Read cycle timing diagram for further details (Figure 4).

Byte-Program Operation

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are programmed on a byte-by-byte basis. Before
programming, one must ensure that the sector, in which
the byte which is being programmed exists, is fully erased.
The Program operation consists of three steps. The first
step is the three-byte-load sequence for Software Data
Protection. The second step is to load byte address and
byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. See Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 15 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte-com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#

pulse, while the command (30H) is latched on the rising
edge of the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase can be
determined using either Data# Polling or Toggle Bit meth-
ods. See Figure 9 for timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.

Chip-Erase Operation

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the "1s"
state. This is useful when the entire device must be quickly
erased.

The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, and Figure 18 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.

Write Operation Status Detection

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide two software means to detect the
completion of a Write (Program or Erase) cycle, in order to
optimize the system write cycle time. The software detec-
tion includes two status bits: Data# Polling (DQ

) and Tog-

gle Bit (DQ

). The End-of-Write detection mode is enabled

after the rising edge of WE# which initiates the internal Pro-
gram or Erase operation.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ

or DQ

. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

S71150-03-000

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395

Data# Polling (DQ

)

When the SST39LF512/010/020/040 and SST39VF512/
010/020/040 are in the internal Program operation, any
attempt to read DQ

will produce the complement of the

true data. Once the Program operation is completed, DQ

will produce true data. The device is then ready for the next
operation. During internal Erase operation, any attempt to
read DQ

will produce a `0'. Once the internal Erase opera-

tion is completed, DQ

will produce a `1'. The Data# Polling

is valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 7 for Data# Polling timing diagram
and Figure 16 for a flowchart.

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-
gram and Figure 16 for a flowchart.

Data Protection

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide both hardware and software features to
protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide the JEDEC approved Software Data Pro-
tection scheme for all data alteration operation, i.e., Pro-
gram and Erase. Any Program operation requires the
inclusion of a series of three byte sequence. The three
byte-load sequence is used to initiate the Program opera-
tion, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six
byte load sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode, within T

Product Identification

The Product Identification mode identifies the devices as
the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020
and SST39LF/VF040 and manufacturer as SST. This
mode may be accessed by software operations. Users
may use the Software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Table 4 for software operation, Figure 11 for the Software
ID Entry and Read timing diagram, and Figure 17 for the
Software ID entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form, and Figure 17 for a flowchart.

TABLE

1: P

RODUCT

DENTIFICATION

Address

Data

Manufacturer's ID

0000H

BFH

Device ID

SST39LF/VF512

0001H

D4H

SST39LF/VF010

0001H

D5H

SST39LF/VF020

0001H

D6H

SST39LF/VF040

0001H

D7H

T1.1 395

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

S71150-03-000

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395

FIGURE 1: P

SSIGNMENTS

FOR

32-

LEAD

PLCC

Y-Decoder

I/O Buffers and Data Latches

395 ILL B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

UNCTIONAL

LOCK

IAGRAM

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

WE#

A12

A15

A16

WE#

A12

A15

A16

WE#

A17

A12

A15

A16

A18

WE#

A17

32-lead PLCC

Top View

395 ILL F02b.3

14 15 16 17 18 19 20

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

SST39LF/VF512

SST39LF/VF010

SST39LF/VF020

SST39LF/VF040

SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

SST39LF/VF512

SST39LF/VF010

SST39LF/VF020

SST39LF/VF040

SST39LF/VF010

SST39LF/VF020

SST39LF/VF040

SST39LF/VF512

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

S71150-03-000

6/01

395

FIGURE 2: P

SSIGNMENTS

FOR

32-

LEAD

TSOP (8

)

FIGURE 3: P

SSIGNMENT

FOR

48-

BALL

TFBGA (6

)

FOR

1 M

BIT

A11

A9
A8

A13
A14

WE#

VDD

NC
NC

A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14
A17

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14
A17

WE#

VDD

A18
A16
A15
A12

A7
A6
A5
A4

SST39LF/VF512

SST39LF/VF010

SST39LF/VF020

SST39LF/VF040

SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

SST39LF/VF512

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

395 ILL F01.0

Standard Pinout

Top View

Die Up

395 ILL F01a.0.eps

A B C D E F G H

S S T 3 9 L F / V F 0 1 0

TOP VIEW (balls facing down)

A14

WE#

A13

A15

A11

A16

A12

DQ5

DQ2

DQ0

A10

DQ3

CE#

DQ6

VDD

OE#

VSS

DQ7

DQ4

DQ1

VSS

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 39LF020