6/01

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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit (64K x8) Page-Mode EEPROM

SST29EE512 / SST29LE512 / SST29VE512

FEATURES:

Single Voltage Read and Write Operations

5.0V-only for SST29EE512
3.0-3.6V for SST29LE512
2.7-3.6V for SST29VE512

Superior Reliability

Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption

Active Current: 20 mA (typical) for 5V and 10 mA

(typical) for 3.0/2.7V

Standby Current: 10 µA (typical)

Fast Page-Write Operation

128 Bytes per Page, 512 Pages
Page-Write Cycle: 5 ms (typical)
Complete Memory Rewrite: 2.5 sec (typical)
Effective Byte-Write Cycle Time: 39 µs (typical)

Fast Read Access Time

5.0V-only operation: 70 and 90 ns
3.0-3.6V operation: 150 and 200 ns
2.7-3.6V operation: 200 and 250 ns

Latched Address and Data

Automatic Write Timing

Internal V

Generation

End of Write Detection

Toggle Bit
Data# Polling

Hardware and Software Data Protection

Product Identification can be accessed via
Software Operation

TTL I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-lead PLCC
32-lead TSOP (8mm x 14mm, 8mm x 20mm)
32-pin PDIP

PRODUCT DESCRIPTION

The SST29EE/LE/VE512 are 64K x8 CMOS, Page-Write
EEPROMs manufactured with SST's proprietary, high
performance CMOS SuperFlash technology. The split-
gate cell design and thick oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches. The SST29EE/LE/VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE/LE/VE512 con-
form to JEDEC standard pinouts for byte-wide memories.

Featuring high performance Page-Write, the SST29EE/
LE/VE512 provide a typical Byte-Write time of 39 µsec.
The entire memory, i.e., 64 KBytes, can be written page-
by-page in as little as 2.5 seconds, when using interface
features such as Toggle Bit or Data# Polling to indicate
the completion of a Write cycle. To protect against inad-
vertent write, the SST29EE/LE/VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum
of applications, the SST29EE/LE/VE512 are offered with
a guaranteed Page-Write endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.

The SST29EE/LE/VE512 are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applica-
tions, the SST29EE/LE/VE512 significantly improve per-
formance and reliability, while lowering power
consumption. The SST29EE/LE/VE512 improve flexibil-
ity while lowering the cost for program, data, and configu-
ration storage applications.

To meet high density, surface mount requirements, the
SST29EE/LE/VE512 are offered in 32-lead PLCC and 32-
lead TSOP packages. A 600-mil, 32-pin PDIP package is
also available. See Figures 1, 2, and 3 for pinouts.

Device Operation

The SST Page-Mode EEPROM offers in-circuit electrical
write capability. The SST29EE/LE/VE512 do not require
separate Erase and Program operations. The internally
timed Write cycle executes both erase and program trans-
parently to the user. The SST29EE/LE/VE512 have indus-
try standard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE/LE/
VE512 are compatible with industry standard EEPROM
pinouts and functionality.

SST29EE512 / SST29LE512 / SST29VE512512Kb Page-Mode flash memories

Data Sheet

512 Kbit Page-Mode EEPROM

SST29EE512 / SST29LE512 / SST29VE512

S71060-06-000

6/01

301

Read

The Read operations of the SST29EE/LE/VE512 are con-
trolled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the read cycle timing diagram for further details
(Figure 4).

Write

The Page-Write to the SST29EE/LE/VE512 should always
use the JEDEC Standard Software Data Protection (SDP)
three-byte command sequence. The SST29EE/LE/VE512
contain the optional JEDEC approved Software Data Pro-
tection scheme. SST recommends that SDP always be
enabled, thus, the description of the Write operations will
be given using the SDP enabled format. The three-byte
SDP Enable and SDP Write commands are identical;
therefore, any time a SDP Write command is issued,
Software Data Protection is automatically assured. The
first time the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the same
command bypasses the data protection for the page being
written. At the end of the desired Page-Write, the entire
device remains protected. For additional descriptions,
please see the application notes The Proper Use of
JEDEC Standard Software Data Protection and Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories.

The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE/LE/VE512. Steps 1 and 2 use the same timing
for both operations. Step 3 is an internally controlled write
cycle for writing the data loaded in the page buffer into the
memory array for nonvolatile storage. During both the SDP
three-byte load sequence and the byte-load cycle, the
addresses are latched by the falling edge of either CE# or
WE#, whichever occurs last. The data is latched by the ris-
ing edge of either CE# or WE#, whichever occurs first. The
internal write cycle is initiated by the T

BLCO

timer after the

rising edge of WE# or CE#, whichever occurs first. The
Write cycle, once initiated, will continue to completion, typi-
cally within 5 ms. See Figures 5 and 6 for WE# and CE#
controlled Page-Write cycle timing diagrams and Figures
15 and 17 for flowcharts.

The Write operation has three functional cycles: the Soft-
ware Data Protection load sequence, the page load cycle,
and the internal Write cycle. The Software Data Protection

consists of a specific three byte-load sequence that allows
writing to the selected page and will leave the SST29EE/
LE/VE512 protected at the end of the Page-Write. The
page load cycle consists of loading 1 to 128 Bytes of data
into the page buffer. The internal Write cycle consists of the
T

BLCO

time-out and the write timer operation. During the

Write operation, the only valid reads are Data# Polling and
Toggle Bit.

The Page-Write operation allows the loading of up to 128
Bytes of data into the page buffer of the SST29EE/LE/
VE512 before the initiation of the internal Write cycle. Dur-
ing the internal Write cycle, all the data in the page buffer is
written simultaneously into the memory array. Hence, the
Page-Write feature of SST29EE/LE/VE512 allows the
entire memory to be written in as little as 2.5 seconds. Dur-
ing the internal Write cycle, the host is free to perform addi-
tional tasks, such as to fetch data from other locations in
the system to set up the write to the next page. In each
Page-Write operation, all the bytes that are loaded into the
page buffer must have the same page address, i.e. A

through A

. Any byte not loaded with user data will be writ-

ten to FFH.

See Figures 5 and 6 for the Page-Write cycle timing dia-
grams. If after the completion of the three-byte SDP load
sequence or the initial byte-load cycle, the host loads a sec-
ond byte into the page buffer within a byte-load cycle time
(T

BLC

) of 100 µs, the SST29EE/LE/VE512 will stay in the

page load cycle. Additional bytes are then loaded consecu-
tively. The page load cycle will be terminated if no addi-
tional byte is loaded into the page buffer within 200 µs
(T

BLCO

) from the last byte-load cycle, i.e., no subsequent

WE# or CE# high-to-low transition after the last rising edge
of WE# or CE#. Data in the page buffer can be changed by
a subsequent byte-load cycle. The page load period can
continue indefinitely, as long as the host continues to load
the device within the byte-load cycle time of 100 µs. The
page to be loaded is determined by the page address of
the last byte loaded.

Software Chip-Erase

The SST29EE/LE/VE512 provide a Chip-Erase operation,
which allows the user to simultaneously clear the entire
memory array to the "1" state. This is useful when the entire
device must be quickly erased.

The Software Chip-Erase operation is initiated by using a
specific six-byte load sequence. After the load sequence,
the device enters into an internally timed cycle similar to the
Write cycle. During the Erase operation, the only valid read
is Toggle Bit. See Table 4 for the load sequence, Figure 10
for timing diagram, and Figure 19 for the flowchart.

Data Sheet

512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512

S71060-06-000

6/01

301

Write Operation Status Detection

The SST29EE/LE/VE512 provide two software means to
detect the completion of a Write cycle, in order to optimize
the system write cycle time. The software detection
includes two status bits: Data# Polling (DQ

) and Toggle Bit

(DQ

). The end of write detection mode is enabled after the

rising WE# or CE# whichever occurs first, which initiates
the internal Write cycle.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ

or DQ

. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.

Data# Polling (DQ

)

When the SST29EE/LE/VE512 are in the internal Write
cycle, any attempt to read DQ

of the last byte loaded dur-

ing the byte-load cycle will receive the complement of the
true data. Once the Write cycle is completed, DQ

will

show true data. The device is then ready for the next opera-
tion. See Figure 7 for Data# Polling timing diagram and Fig-
ure 16 for a flowchart.

Toggle Bit (DQ

)

During the internal Write cycle, any consecutive attempts to
read DQ

will produce alternating 0s and 1s, i.e., toggling

between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 8 for Toggle Bit timing diagram and
Figure 16 for a flowchart. The initial read of the Toggle Bit
will typically be a "1".

Data Protection

The SST29EE/LE/VE512 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST29EE/LE/VE512 provide the JEDEC approved
optional Software Data Protection scheme for all data alter-
ation operations, i.e., Write and Chip-Erase. With this
scheme, any Write operation requires the inclusion of a
series of three byte-load operations to precede the data
loading operation. The three byte-load sequence is used to
initiate the Write cycle, providing optimal protection from
inadvertent write operations, e.g., during the system power-
up or power-down. The SST29EE/LE/VE512 are shipped
with the Software Data Protection disabled.

The software protection scheme can be enabled by apply-
ing a three-byte sequence to the device, during a page-
load cycle (Figures 5 and 6). The device will then be auto-
matically set into the data protect mode. Any subsequent
write operation will require the preceding three-byte
sequence. See Table 4 for the specific software command
codes and Figures 5 and 6 for the timing diagrams. To set
the device into the unprotected mode, a six-byte sequence
is required. See Table 4 for the specific codes and Figure 9
for the timing diagram. If a write is attempted while SDP is
enabled the device will be in a non-accessible state for ~
300 µs. SST recommends Software Data Protection
always be enabled. See Figure 17 for flowcharts.

The SST29EE/LE/VE512 Software Data Protection is a
global command, protecting (or unprotecting) all pages in
the entire memory array once enabled (or disabled). There-
fore using SDP for a single Page-Write will enable SDP for
the entire array. Single pages by themselves cannot be
SDP enabled or disabled, although the page addressed
during the SDP write will be written.

Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE/LE/VE512 should be programmed
using the SDP command sequence. SST recommends the
SDP Disable Command Sequence not be issued to the
device prior to writing.

Please refer to the following Application Notes for more
information on using SDP:

Protecting Against Unintentional Writes When
Using Single Power Supply Flash Memories

The Proper Use of JEDEC Standard Software
Data Protection

Data Sheet

512 Kbit Page-Mode EEPROM

SST29EE512 / SST29LE512 / SST29VE512

S71060-06-000

6/01

301

Product Identification

The product identification mode identifies the device as the
SST29EE/LE/VE512 and manufacturer as SST. This mode
is accessed via software. For details, see Table 4, Figure
11 for the software ID entry, and read timing diagram and
Figure 18 for the ID entry command sequence flowchart.

Product Identification Mode Exit

In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Software ID Exit (reset) opera-
tion, which returns the device to the Read operation. The
Reset operation may also be used to reset the device to the
Read mode after an inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. See Table 4 for software command
codes, Figure 12 for timing waveform, and Figure 18 for a
flowchart.

FIGURE 1: P

SSIGNMENTS

FOR

32-

LEAD

PLCC

TABLE

1: P

RODUCT

DENTIFICATION

Address

Data

Manufacturer's ID

0000H

BFH

Device ID

SST29EE512

0001H

5DH

SST29LE512

0001H

3DH

SST29VE512

0001H

3DH

T1.2 301

Y-Decoder and Page Latches

I/O Buffers and Data Latches

301 ILL B1.1

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

A15 - A0

WE#

OE#

CE#

SuperFlash

Memory

Control Logic

UNCTIONAL

LOCK

IAGRAM

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

WE#

32-lead PLCC

Top View

301 ILL F19.1

14 15 16 17 18 19 20

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

Data Sheet

512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512

S71060-06-000

6/01

301

FIGURE 2: P

SSIGNMENTS

FOR

32-

LEAD

TSOP

FIGURE 3: P

SSIGNMENTS

FOR

32-

PIN

PDIP

301 ILL F01.2

A11

A9
A8

A13
A14

WE#

VDD

NC
NC

A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

Standard Pinout

Top View

Die Up

32-pin

PDIP

Top View

301 ILL F02.2

A15

A12

DQ0

DQ1

DQ2

VSS

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

TABLE

2: P

ESCRIPTION

Symbol

Pin Name

Functions

-A

Row Address Inputs

To provide memory addresses. Row addresses define a page for a Write cycle.

-A

Column Address Inputs

Column Addresses are toggled to load page data

-DQ

Data Input/output

To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers.

WE#

Write Enable

To control the Write operations.

Power Supply

To provide:

5.0V supply (±10%) for SST29EE512
3.0V supply (3.0-3.6V) for SST29LE512
2.7V supply (2.7-3.6V) for SST29VE512

Ground

No Connection

Unconnected pins.

T2.1 301

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