6/01

360

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

FEATURES:

Organized as 128K x16 / 256K x16 / 512K x16

Single Voltage Read and Write Operations

3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A

Superior Reliability

Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption

Active Current: 20 mA (typical)
Standby Current: 3 µA (typical)

Sector-Erase Capability

Uniform 2 KWord sectors

Block-Erase Capability

Uniform 32 KWord blocks

Fast Read Access Time

45 and 55 ns for SST39LF200A/400A
55 ns for SST39LF800A
70 and 90 ns for SST39VF200A/400A/800A

Latched Address and Data

Fast Erase and Word-Program

Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Word-Program Time: 14 µs (typical)
Chip Rewrite Time:

2 seconds (typical) for SST39LF/VF200A
4 seconds (typical) for SST39LF/VF400A
8 seconds (typical) for SST39LF/VF800A

Automatic Write Timing

Internal V

Generation

End-of-Write Detection

Toggle Bit
Data# Polling

CMOS I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

48-lead TSOP (12mm x 20mm)
48-ball TFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are 128K x16 / 256K x16 / 512K x16 CMOS
Multi-Purpose Flash (MPF) manufactured with SST's pro-
prietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply. The
SST39VF200A/400A/800A write (Program or Erase) with a
2.7-3.6V power supply. These devices conform to JEDEC
standard pinouts for x16 memories.

Featuring high performance Word-Program, the
SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices provide a typical Word-Program time of 14
µsec. The devices use Toggle Bit or Data# Polling to detect
the completion of the Program or Erase operation. To pro-
tect against inadvertent write, they have on-chip hardware
and software data protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed endurance of
10,000 cycles. Data retention is rated at greater than 100
years.

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are suited for applications that require conve-
nient and economical updating of program, configuration,
or data memory. For all system applications, they signifi-

cantly improve performance and reliability, while lowering
power consumption. They inherently use less energy dur-
ing Erase and Program than alternative flash technologies.
When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configuration
storage applications.

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.

To meet surface mount requirements, the SST39LF200A/
400A/800A and SST39VF200A/400A/800A are offered in
both 48-lead TSOP packages and 48-ball TFBGA pack-
ages. See Figures 1 and 2 for pinouts.

2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

Device Operation

Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39LF200A/400A/800A and
SST39VF200A/400A/800A is controlled by CE# and OE#,
both have to be low for the system to obtain data from the
outputs. CE# is used for device selection. When CE# is
high, the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 3).

Word-Program Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A are programmed on a word-by-word basis. Before
programming, one must ensure that the sector, in which
the word which is being programmed exists, is fully erased.
The Program operation consists of three steps. The first
step is the three-byte load sequence for Software Data Pro-
tection. The second step is to load word address and word
data. During the Word-Program operation, the addresses
are latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the rising
edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed within 20 µs. See Figures 4 and 5 for WE#
and CE# controlled Program operation timing diagrams
and Figure 16 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands issued during the
internal Program operation are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39LF200A/400A/800A and
SST39VF200A/400A/800A offers both Sector-Erase and
Block-Erase mode. The sector architecture is based on
uniform sector size of 2 KWord. The Block-Erase mode is
based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the "1" state. This
is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide two software means to detect the completion
of a write (Program or Erase) cycle, in order to optimize the
system write cycle time. The software detection includes
two status bits: Data# Polling (DQ

) and Toggle Bit (DQ

The End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ

or DQ

. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

Data# Polling (DQ

)

When the SST39LF200A/400A/800A and SST39VF200A/
400A/800A are in the internal Program operation, any
attempt to read DQ

will produce the complement of the

true data. Once the Program operation is completed, DQ

will produce true data. The device is then ready for the next
operation. During internal Erase operation, any attempt to
read DQ

will produce a `0'. Once the internal Erase opera-

tion is completed, DQ

will produce a `1'. The Data# Polling

is valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector-, Block- or Chip-Erase,
the Data# Polling is valid after the rising edge of sixth WE#
(or CE#) pulse. See Figure 6 for Data# Polling timing dia-
gram and Figure 17 for a flowchart.

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ

bit will

stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.

Data Protection

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide both hardware and software features to pro-
tect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide the JEDEC approved Software Data Protec-
tion scheme for all data alteration operations, i.e., Program
and Erase. Any Program operation requires the inclusion of
the three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte sequence. This group of
devices are shipped with the Software Data Protection per-
manently enabled. See Table 4 for the specific software
command codes. During SDP command sequence, invalid
commands will abort the device to Read mode within TRC.
The contents of DQ

-DQ

can be V

or V

, but no other

value, during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39LF200A/400A/800A and SST39VF200A/400A/
800A also contain the CFI information to describe the char-
acteristics of the device. In order to enter the CFI Query
mode, the system must write three-byte sequence, same
as Software ID Entry command with 98H (CFI Query com-
mand) to address 5555H in the last byte sequence. Once
the device enters the CFI Query mode, the system can
read CFI data at the addresses given in Tables 5 through 9.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

Product Identification

The Product Identification mode identifies the devices as
the SST39LF/VF200A, SST39LF/VF400A and SST39LF/
VF800A and manufacturer as SST. This mode may be
accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple
manufacturers in the same socket. For details, see Table 4
for software operation, Figure 11 for the Software ID Entry
and Read timing diagram, and Figure 18 for the Software
ID Entry command sequence flowchart.

Product Identification Mode Exit/
CFI Mode Exit

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform and Figure 18 for a
flowchart.

TABLE

1: P

RODUCT

DENTIFICATION

ABLE

Address

Data

Manufacturer's ID

0000H

00BFH

Device ID

SST39LF/VF200A

0001H

2789H

SST39LF/VF400A

0001H

2780H

SST39LF/VF800A

0001H

2781H

T1.3 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

FIGURE 1: P

SSIGNMENTS

FOR

48-

LEAD

TSOP

Y-Decoder

I/O Buffers and Data Latches

360 ILL B1.2

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

UNCTIONAL

LOCK

IAGRAM

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

WE#

NC
NC
NC
NC
NC
NC

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

360 ILL F01.2

Standard Pinout

Top View

Die Up

SST39LF200A/400A/800A

SST39VF200A/400A/800A

SST39LF/VF200A

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

WE#

NC
NC
NC
NC
NC

A17

A7
A6
A5
A4
A3
A2
A1

SST39LF/VF400A

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

WE#

NC
NC
NC
NC

A18
A17

A7
A6
A5
A4
A3
A2
A1

SST39LF/VF800A

SST39LF/VF200A

A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0

SST39LF/VF400A

A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0

SST39LF/VF800A

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

FIGURE 2: P

SSIGNMENTS

FOR

48-

BALL

TFBGA

A13

WE#

A12

A14

A10

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

360 ILL F02_2.0

SST39LF/VF200A

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

A12

A17

A14

A10

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

360 ILL F02_4.0

SST39LF/VF400A

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

A12

A17

A14

A10

A18

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

360 ILL F02_8.0

SST39LF/VF800A

TOP VIEW (balls facing down)

A B C D E F G H

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

TABLE

2: P

ESCRIPTION

Symbol

Pin Name

Functions

-A

Address Inputs

To provide memory addresses. During Sector-Erase A

-A

address lines will select the

sector. During Block-Erase A

-A

address lines will select the block.

-DQ

Data Input/output

To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers.

WE#

Write Enable

To control the Write operations.

Power Supply

To provide power supply voltage:

3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A

Ground

No Connection

Unconnected pins.

T2.2 360

1. A

= Most significant address

= A

for SST39LF/VF200A, A

for SST39LF/VF400A, and A

for SST39LF/VF800A

TABLE

3: O

PERATION

ODES

ELECTION

Mode

CE#

OE#

WE#

Address

Read

OUT

Program

Erase

1. X can be V

or V

, but no other value.

Sector or Block address,
XXH for Chip-Erase

Standby

High Z

Write Inhibit

High Z/ D

OUT

High Z/ D

OUT

Product Identification

Software Mode

See Table 4

T3.4 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

TABLE

4: S

OFTWARE

OMMAND

EQUENCE

Command
Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Word-Program

5555H

AAH

2AAAH

55H

5555H

A0H

Data

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

30H

Block-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

50H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Software ID Entry

5,6

5555H

AAH

2AAAH

55H

5555H

90H

CFI Query Entry

5555H

AAH

2AAAH

55H

5555H

98H

Software ID Exit

CFI Exit

XXH

F0H

Software ID Exit

CFI Exit

5555H

AAH

2AAAH

55H

5555H

F0H

T4.2 360

1. Address format A

-A

(Hex),

Addresses A

and A

can be V

or V

, but no other value, for the Command sequence for SST39LF/VF200A.

Addresses A

, A

, and A

can be V

or V

, but no other value, for the Command sequence for SST39LF/VF400A.

Addresses A

, A

, and A

can be V

or V

, but no other value, for the Command sequence for SST39LF/VF800A.

2. DQ

- DQ

can be V

or V

, but no other value, for the Command sequence

3. WA = Program word address
4. SA

for Sector-Erase; uses A

-A

address lines

, for Block-Erase; uses A

-A

address lines

= Most significant address

= A

for SST39LF/VF200A, A

for SST39LF/VF400A and A

for SST39LF/VF800A

5. The device does not remain in Software Product ID Mode if powered down.
6. With A

-A

=0; SST Manufacturer's ID= 00BFH, is read with A

= 0,

SST39LF/VF200A Device ID = 2789H, is read with A

= 1.

SST39LF/VF400A Device ID = 2780H, is read with A

= 1.

SST39LF/VF800A Device ID = 2781H, is read with A

= 1.

7. Both Software ID Exit operations are equivalent

TABLE

5: CFI Q

UERY

DENTIFICATION

TRING1

FOR

SST39LF200A/400A/800A

AND

SST39VF200A/400A/800A

1. Refer to CFI publication 100 for more details.

Address

Data

10H

0051H

Query Unique ASCII string "QRY"

11H

0052H

12H

0059H

13H

0001H

Primary OEM command set

14H

0007H

15H

0000H

Address for Primary Extended Table

16H

0000H

17H

0000H

Alternate OEM command set (00H = none exists)

18H

0000H

19H

0000H

Address for Alternate OEM extended Table (00H = none exits)

1AH

0000H

T5.0 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

TABLE

6: S

YSTEM

NTERFACE

NFORMATION

FOR

SST39LF200A/400A/800A

AND

SST39VF200A/400A/800A

Address

Data

1BH

0027H

Min. (Program/Erase)

0030H

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1CH

0036H

Max. (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1DH

0000H

min. (00H = no V

pin)

1EH

0000H

max. (00H = no V

pin)

1FH

0004H

Typical time out for Word-Program 2

µs (2

= 16 µs)

20H

0000H

Typical time out for min. size buffer program 2

µs (00H = not supported)

21H

0004H

Typical time out for individual Sector/Block-Erase 2

ms (2

= 16 ms)

22H

0006H

Typical time out for Chip-Erase 2

ms (2

= 64 ms)

23H

0001H

Maximum time out for Word-Program 2

times typical (2

x 2

= 32 µs)

24H

0000H

Maximum time out for buffer program 2

times typical

25H

0001H

Maximum time out for individual Sector/Block-Erase 2

times typical (2

x 2

= 32 ms)

26H

0001H

Maximum time out for Chip-Erase 2

times typical (2

x 2

= 128 ms)

T6.2 360

1. 0030H for SST39LF200A/400A/800A and 0027H for SST39VF200A/400A/800A

TABLE

7: D

EVICE

EOMETRY

NFORMATION

FOR

SST39LF/VF200A

Address

Data

27H

0012H

Device size = 2

Byte (12H = 18; 2

= 256 KBytes)

28H

0001H

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

0000H

2AH

0000H

Maximum number of byte in multi-byte write = 2

(00H = not supported)

2BH
2CH

0002H

Number of Erase Sector/Block sizes supported by device

2DH

003FH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

0000H

y = 63 + 1 = 64 sectors (003FH = 63)

2FH

0010H

30H

0000H

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H

0003H

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

0000H

y = 3 + 1 = 4 blocks (0003H = 3)

33H

0000H

34H

0001H

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

T7.2 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

TABLE

8: D

EVICE

EOMETRY

NFORMATION

FOR

SST39LF/VF400A

Address

Data

27H

0013H

Device size = 2

Byte (13H = 19; 2

= 512 KBytes)

28H

0001H

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

0000H

2AH

0000H

Maximum number of byte in multi-byte write = 2

(00H = not supported)

2BH

0000H

2CH

0002H

Number of Erase Sector/Block sizes supported by device

2DH

007FH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

0000H

y = 127 + 1 = 128 sectors (007FH = 127)

2FH

0010H

30H

0000H

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H

0007H

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

0000H

y = 7 + 1 = 8 blocks (0007H = 7)

33H

0000H

34H

0001H

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

T8.1 360

TABLE

9: D

EVICE

EOMETRY

NFORMATION

FOR

SST39LF/VF800A

Address

Data

27H

0014H

Device size = 2

Byte (14H = 20; 2

= 1 MByte)

28H

0001H

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

0000H

2AH

0000H

Maximum number of byte in multi-byte write = 2

(00H = not supported)

2BH

0000H

2CH

0002H

Number of Erase Sector/Block sizes supported by device

2DH

00FFH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

0000H

y = 255 + 1 = 256 sectors (00FFH = 255)

2FH

0010H

30H

0000H

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H

000FH

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

0000H

y = 15 + 1 = 16 blocks (000FH = 15)

33H

0000H

34H

0001H

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

T9.0 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V

+ 1.0V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

PERATING

ANGE

: SST39LF200A/400A/800A

Range

Ambient Temp

Commercial

0°C to +70°C

3.0-3.6V

PERATING

ANGE

: SST39VF200A/400A/800A

Range

Ambient Temp

Commercial

0°C to +70°C

2.7-3.6V

Extended

-20°C to +85°C

2.7-3.6V

Industrial

-40°C to +85°C

2.7-3.6V

AC C

ONDITIONS

EST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

= 30 pF for SST39LF200A/400A/800A

Output Load . . . . . . . . . . . . . . . . . . . . C

= 100 pF for SST39VF200A/400A/800A

See Figures 14 and 15

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

TABLE 10: DC O

PERATING

HARACTERISTICS

= 3.0-3.6V

FOR

SST39LF200A/400A/800A

AND

2.7-3.6V

FOR

SST39VF200A/400A/800A

Symbol

Parameter

Limits

Test Conditions

Min

Max

Units

Power Supply Current

Address input = V

, at f=1/T

Min.,

Max.

Read

CE#=OE#=V

,WE#=V

, all I/Os open

Program and Erase

CE#=WE#=V

, OE#=V

Standby V

Current

µA

CE#=V

IHC

, V

= V

Max.

Input Leakage Current

µA

=GND to V

, V

= V

Max.

Output Leakage Current

µA

OUT

=GND to V

, V

= V

Max.

Input Low Voltage

0.8

= V

Min.

Input High Voltage

0.7V

= V

Max.

IHC

Input High Voltage (CMOS)

-0.3

= V

Max.

Output Low Voltage

0.2

= 100 µA, V

= V

Min.

Output High Voltage

-0.2

= -100 µA, V

= V

Min.

T10.5 360

TABLE 11: R

ECOMMENDED

YSTEM

OWER

IMINGS

Symbol

Parameter

Minimum

Units

PU-READ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation

100

µs

PU-WRITE

Power-up to Program/Erase Operation

100

µs

T11.0 360

TABLE 12: C

APACITANCE

(Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

I/O

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance

I/O

= 0V

12 pF

Input Capacitance

= 0V

6 pF

T12.0 360

TABLE 13: R

ELIABILITY

HARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

END

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance

10,000

Cycles

JEDEC Standard A117

Data Retention

100

Years

JEDEC Standard A103

LTH

Latch Up

100 + I

JEDEC Standard 78

T13.1 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

AC CHARACTERISTICS

TABLE 14: R

EAD

YCLE

IMING

ARAMETERS

= 3.0-3.6V

Symbol

Parameter

SST39LF200A/400A-45

SST39LF200A/400A/800A-55

Units

Min

Max

Min

Max

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

CLZ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output

OLZ

OE# Low to Active Output

CHZ

CE# High to High-Z Output

OHZ

OE# High to High-Z Output

Output Hold from Address Change

T14.7 360

TABLE 15: R

EAD

YCLE

IMING

ARAMETERS

= 2.7-3.6V

Symbol

Parameter

SST39VF200A/400A/800A-70

SST39VF200A/400A/800A-90

Units

Min

Max

Min

Max

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

CLZ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output

OLZ

OE# Low to Active Output

CHZ

CE# High to High-Z Output

OHZ

OE# High to High-Z Output

Output Hold from Address Change

T15.6 360

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

TABLE 16: P

ROGRAM

RASE

YCLE

IMING

ARAMETERS

Symbol

Parameter

Min

Max

Units

Word-Program Time

µs

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OES

OE# High Setup Time

OEH

OE# High Hold Time

CE# Pulse Width

WE# Pulse Width

WPH

WE# Pulse Width High

CPH

CE# Pulse Width High

Data Setup Time

Data Hold Time

IDA

Software ID Access and Exit Time

150

Sector-Erase

Block-Erase

SCE

Chip-Erase

100

T16.0 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

FIGURE 7: T

OGGLE

IMING

IAGRAM

FIGURE 8: WE# C

ONTROLLED

HIP

-E

RASE

IMING

IAGRAM

360 ILL F07.3

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note:

AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

360 ILL F08.7

ADDRESS AMS-0

DQ15-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

5555

2AAA

5555

XX55

XX10

XX55

XXAA

XX80

XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

FIGURE 9: WE# C

ONTROLLED

LOCK

-E

RASE

IMING

IAGRAM

FIGURE 10: WE# C

ONTROLLED

ECTOR

-E

RASE

IMING

IAGRAM

360 ILL F17.9

ADDRESS AMS-0

DQ15-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

5555

2AAA

5555

XX55

XX50

XX55

XXAA

XX80

XXAA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)
BAX = Block Address
AMS = Most significant address

AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.

360 ILL F18.8

ADDRESS AMS-0

DQ15-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

5555

2AAA

5555

XX55

XX30

XX55

XXAA

XX80

XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)
SAX = Sector Address
AMS = Most significant address

AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

FIGURE 19: E

RASE

OMMAND

EQUENCE

360 ILL F16.5

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

Note:

X can be VIL or VIH, but no other value.

Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A

S71117-04-000

6/01

360

Valid combinations for SST39LF200A

SST39LF200A-45-4C-EK

SST39LF200A-45-4C-B3K

SST39LF200A-55-4C-EK

SST39LF200A-55-4C-B3K

Valid combinations for SST39VF200A

SST39VF200A-70-4C-EK

SST39VF200A-70-4C-B3K

SST39VF200A-90-4C-EK

SST39VF200A-90-4C-B3K

SST39VF200A-90-4C-U1

SST39VF200A-70-4I-EK

SST39VF200A-70-4I-B3K

SST39VF200A-90-4I-EK

SST39VF200A-90-4I-B3K

Valid combinations for SST39LF400A

SST39LF400A-45-4C-EK

SST39LF400A-45-4C-B3K

SST39LF400A-55-4C-EK

SST39LF400A-55-4C-B3K

Valid combinations for SST39VF400A

SST39VF400A-70-4C-EK

SST39VF400A-70-4C-B3K

SST39VF400A-90-4C-EK

SST39VF400A-90-4C-B3K

SST39VF400A-90-4C-U1

SST39VF400A-70-4I-EK

SST39VF400A-70-4I-B3K

SST39VF400A-90-4I-EK

SST39VF400A-90-4I-B3K

Valid combinations for SST39LF800A

SST39LF800A-55-4C-EK

SST39LF800A-55-4C-B3K

Valid combinations for SST39VF800A

SST39VF800A-70-4C-EK

SST39VF800A-70-4C-B3K

SST39VF800A-90-4C-EK

SST39VF800A-90-4C-B3K

SST39VF800A-90-4C-U1

SST39VF800A-70-4I-EK

SST39VF800A-70-4I-B3K

SST39VF800A-90-4I-EK

SST39VF800A-90-4I-B3K

Note:

Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

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