Syntek Semiconductor Co., Ltd.
LCD Controller 1 / 1 ISSUE DATE Date : 15 September, 1999:
STK55C1042
STK55C1042 Specification
1. CHIP FEATURES :
* Operating voltage : 2.5V-6.5V
* Operating current : under 5mA at 5V.
* Dual frequency
- 32.768 KHz for LCD & 0.5 second timer interrupt.
- Crystal or RC oscillator for system clock.
- CPU clock is half of system clock.
* Built-in 2K bytes RAM, (1st 144 bytes for LCD, the rest 1904 bytes for program & stack).
* Built-in 32K bytes ROM with 16K per bank.
* Two chip enable signals for external memory. Each one can be expanded to 512K bytes with 16K bytes
per bank.
* One 0.5 second pre-divider timer interrupt with start/stop control.
* 2 output ports for key matrices
- 14 pins for port 1, also used as address pins.
- 4 input pins with wake-up interrupt for port 2.
- Built-in pull-up resistors for port 2.
* 8-bit timer with 8-bit prescale counter, both are auto-reloadable.
* 65 segments and 16 commons output pins for LCD driver.
- 1/5 bias, 1/16 duty and 64 Hz frame frequency.
* Selectable 64 Hz Interrupt by NMI.
* Timers and port 2 enable IRQ Interrupt.
* Timer range is programmable.
* 8-bit sound generator with 8-bit prescaler, both are auto-reloadable.
* One output for the speaker.
- 2 KHz or 4 KHz signal with two different envelopes are selectable for sound output.
* One UART serial port with even parity check bit added after MSB for error detecting.
* The internal ROM can be disabled and the corresponding memory area are mapped to the highest banks of
external ROM.
System
clock
1/2
8-bit counter
(prescaler)
8-bit counter
(timer)
IRQ1
CPU clock
Syntek Semiconductor Co., Ltd.
LCD Controller 2 / 2 ISSUE DATE Date : 15 September, 1999:
STK55C1042
* Sleep mode : LCD off , crystal & system oscillator stop, Vdd=3V, Idd < 1 uA.
Stand-by mode : LCD on and system oscillator stop, Vdd=3V, Idd < 80 uA. LCD off and system oscillator
stop, Vdd=3V, Idd < 8 uA.
2. APPLICATION:
l
Data Bank
l
Translator
l
Organizer
l
Hand-held game
Syntek Semiconductor Co., Ltd.
LCD Controller 3 / 3 ISSUE DATE Date : 15 September, 1999:
STK55C1042
3. BLOCK DIAGRAM:
A0-A15
D0-D7
A0-A13
P20-P23
D0-D7
8-bit CPU
Address decoder
ROM
32Kx8
RAM
2Kx8
Clock Generator
LCD driver
Sound generator
Port 1
Port 2
RC oscillator
SOUND
32768Hz
C1-C16
S1-S65
OSC1
OSC2
UART
MUX
16-bit Timer
TX
RX
Bank control
B0-B6
Syntek Semiconductor Co., Ltd.
LCD Controller 4 / 4 ISSUE DATE Date : 15 September, 1999:
STK55C1042
4. PIN DESCRIPTION :
(Total 131 pads)
Pin name
I/O
Description
COM1-COM16
O
Output pins for driving the commons of LCD panel
SEG1-SEG65
O
Output pins for driving the segments of LCD panel
SOUND
O
Output pin for speaker
A0-A13
O
Address bus outputs share with port 1 output
L0-L3
IU
4 input pins for key matrix with wake-up interrupt
D0-D7
I/O
Data pins
OSC1
I
RC/Crystal Oscillator input pin for system clock
OSC2
O
RC/Crystal Oscillator output pin for system clock
( Note: CPU clock = system clock/2 )
OSC3
I/O
RC Oscillator bi-directional pin for system clock
/RES
IU
Chip reset
VDD
I
Power input
VSS
I
Signal ground
LOSC1
I
Crystal oscillator input pin
LOSC2
O
Crystal oscillator output pin
BANK0-BANK4
O
To select external memory banks. The data on $1209 will be
output in these pins except during /CE2 read/write cycle. At
that time these pins will output the data on $120A
/CE1
O
External chip Enable 1. This pin will be forced to high during
sleep mode.
/CE2
O
External chip enable 2. This pin will be forced to high during
sleep mode.
/TEST
IU
Test pin. Keep floating or connect to VDD
RWB
O
Read/Write signal output
VLCD
I
Power supply for LCD driver
VR
I
Contrast control for LCD
CLKOUT
O
512 Hz output clock for voltage doubler. This clock will be
stopped if 32.768K Hz crystal is stopped
/DIROM
IU
Internal ROM control pin.
=0 Disable internal ROM
=1 Enable internal ROM
TX
O
Transmit data pin
RX
IU
Receive data pin
Syntek Semiconductor Co., Ltd.
LCD Controller 5 / 5 ISSUE DATE Date : 15 September, 1999:
STK55C1042
Note : IU -- Input pin with pull-up resistor.
5. ADDRESS ARRANGEMENT :
1) RAM
0000-008F : for LCD output data storage.
SEG1-SEG8
SEG9-SEG16
SEG57-SEG64
SEG65
COM1
0000
0010
0070
0080
COM2
0001
0011
0071
0081
COM16
000F
001F
007F
008F
* The LSB of low byte - SEG1
The LSB of high byte - SEG65
Middle bits are in order.
0090-00FF : for zero page area
0100-01FF : for stack area
0200-07FF : for data area.
4000-7FFF : for external chip enable 1. While this area is accessed, /CE1 will be low and the data in
$1209 will be output on BANK0-BANK4. If bit 0 of $121A is set to one, then this area
can not be accessed.
2) ROM
8000-BFFF : for external chip 2 or internal ROM banks.
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