ST24/25C02, ST24C02R
ST24/25W02
SERIAL 2K (256 x 8) EEPROM
NOT FOR NEW DESIGN
November 1997
1/16
This is information on a product still in production but not recommended for new design
AI00788D
3
E0-E2
SDA
VCC
ST24x02
ST25x02
ST24C02R
MODE/WC*
SCL
VSS
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
3V to 5.5V for ST24x02 versions
2.5V to 5.5V for ST25x02 versions
1.8V to 5.5V for ST24C02R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W02 and ST25W02
TWO WIRE SERIAL INTERFACE, FULLY I
2
C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH-UP
PERFORMANCES
ST24C/W02 are replaced by the M24C02
ST25C/W02 are replaced by the M24C02-W
ST24C02R is replaced by the M24C02-R
DESCRIPTION
This specification covers a range of 2K bits I
2
C bus
EEPROM produc ts, t he ST24/25C02, the
ST24C02R and ST24/25W02. In the text, products
are referred to as ST24/25x02, where "x" is: "C" for
Standard version and "W" for hardware Write Con-
trol version.
E0-E2
Chip Enable Inputs
SDA
Serial Data Address Input/Output
SCL
Serial Clock
MODE
Multibyte/Page Write Mode
(C version)
WC
Write Control (W version)
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
8
1
SO8 (M)
150mil Width
8
1
PSDIP8 (B)
0.25mm Frame
Note: WC signal is only available for ST24/25W02 products.
The ST24/25x02 are 2K bit electrically erasable
programmable memories (EEPROM), organized
as 256 x 8 bits. They are manufactured in SGS-
THOMSON's Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C02R only.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I
2
C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I
2
C bus defini-
tion. This is used together with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 2K devices may be
attached to the I
2
C bus and selected individually.
The memories behave as a slave device in the I
2
C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
SDA
VSS
SCL
MODE/WC
E1
E0
VCC
E2
AI00789D
ST24x02
ST25x02
ST24C02R
1
2
3
4
8
7
6
5
Figure 2A. DIP Pin Connections
1
AI00790E
2
3
4
8
7
6
5
SDA
VSS
SCL
MODE/WC
E1
E0
VCC
E2
ST24x02
ST25x02
ST24C02R
Figure 2B. SO Pin Connections
DESCRIPTION (cont'd)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 125
C
T
STG
Storage Temperature
65 to 150
C
T
LEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
C
V
IO
Input or Output Voltages
0.6 to 6.5
V
V
CC
Supply Voltage
0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
(2)
4000
V
Electrostatic Discharge Voltage (Machine model)
(3)
500
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
).
3. EIAJ IC-121 (Condition C) (200pF, 0
).
Table 2. Absolute Maximum Ratings
(1)
2/16
ST24/25C02, ST24C02R, ST24/25W02
Mode
RW bit
MODE
Bytes
Initial Sequence
Current Address Read
'1'
X
1
START, Device Select, RW = '1'
Random Address Read
'0'
X
1
START, Device Select, RW = '0', Address,
'1'
reSTART, Device Select, RW = '1'
Sequential Read
'1'
X
1 to 256
Similar to Current or Random Mode
Byte Write
'0'
X
1
START, Device Select, RW = '0'
Multibyte Write
(2)
'0'
V
IH
4
START, Device Select, RW = '0'
Page Write
'0'
V
IL
8
START, Device Select, RW = '0'
Notes: 1. X = V
IH
or V
IL
2. Multibyte Write not available in ST24/25W02 versions.
Table 4. Operating Modes
(1)
Device Code
Chip Enable
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
E2
E1
E0
RW
Note: The MSB b7 is sent first.
Table 3. Device Select Code
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: V
CC
lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
CC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR'ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Chip Enable (E2 - E0). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to V
CC
or V
SS
to
establish the device select code.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at V
IL
or V
IH
for the Byte Write
mode, V
IH
for Multibyte Write mode or V
IL
for Page
Write mode. When unconnected, the MODE input
is internally read as a V
IH
(Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W02 and
ST25W02 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = V
IH
) or disable (WC =
V
IL
) the internal write protection. When uncon-
nected, the WC input is internally read as V
IL
and
the memory area is not write protected.
3/16
ST24/25C02, ST24C02R, ST24/25W02
AI01100
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
200
300
400
0
4
8
12
16
20
CBUS (pF)
R
L
max (k
)
VCC = 5V
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x02 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x02 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x02 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x02
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x02
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x02,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
SIGNAL DESCRIPTIONS (cont'd)
4/16
ST24/25C02, ST24C02R, ST24/25W02
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance (SDA)
8
pF
C
IN
Input Capacitance (other pins)
6
pF
Z
WCL
WC Input Impedance (ST24/25W02)
V
IN
0.3 V
CC
5
20
k
Z
WCH
WC Input Impedance (ST24/25W02)
V
IN
0.7 V
CC
500
k
t
LP
Low-pass filter input time constant
(SDA and SCL)
100
ns
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters
(1)
(T
A
= 25
C, f = 100 kHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
2
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
SDA in Hi-Z
2
A
I
CC
Supply Current (ST24 series)
V
CC
= 5V, f
C
= 100kHz
(Rise/Fall time < 10ns)
2
mA
Supply Current (ST25 series)
V
CC
= 2.5V, f
C
= 100kHz
1
mA
I
CC1
Supply Current (Standby)
(ST24 series)
V
IN
= V
SS
or V
CC
,
V
CC
= 5V
100
A
V
IN
= V
SS
or V
CC
,
V
CC
= 5V, f
C
= 100kHz
300
A
I
CC2
Supply Current (Standby)
(ST25 series)
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V
5
A
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V, f
C
= 100kHz
50
A
I
CC3
Supply Current (Standby)
(ST24C02R)
V
IN
= V
SS
or V
CC
,
V
CC
= 3.6V
20
A
V
IN
= V
SS
or V
CC
,
V
CC
= 3.6V, f
C
= 100kHz
60
A
I
CC4
Supply Current (Standby)
(ST24C02R)
V
IN
= V
SS
or V
CC
,
V
CC
= 1.8V
10
A
V
IN
= V
SS
or V
CC
,
V
CC
= 1.8V, f
C
= 100kHz
20
A
V
IL
Input Low Voltage (SCL, SDA)
0.3
0.3 V
CC
V
V
IH
Input High Voltage (SCL, SDA)
0.7 V
CC
V
CC
+ 1
V
V
IL
Input Low Voltage
(E0-E2, MODE, WC)
0.3
0.5
V
V
IH
Input High Voltage
(E0-E2, MODE, WC)
V
CC
0.5
V
CC
+ 1
V
V
OL
Output Low Voltage (ST24 series)
I
OL
= 3mA, V
CC
= 5V
0.4
V
Output Low Voltage (ST25 series)
I
OL
= 2.1mA, V
CC
= 2.5V
0.4
V
Output Low Voltage
(ST24C02R)
I
OL
= 1mA, V
CC
= 1.8V
0.3
V
Table 6. DC Characteristics
(T
A
= 0 to 70
C, 20 to 85
C or 40 to 85
C; V
CC
= 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
5/16
ST24/25C02, ST24C02R, ST24/25W02
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