M54HC112
M74HC112
October 1992
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
B1R
(Plastic Package)
ORDER CODES :
M54HC112F1R
M74HC112M1R
M74HC112B1R
M74HC112C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
.
HIGH SPEED
f
MAX
= 67 MHz (TYP.) AT V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 2
A AT T
A
= 25
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS112
The M54/74HC112 is a high speed CMOS DUAL J-K
FLIP-FLOP WITH PRESET AND CLEAR fabricated in
silicon gate C
2
MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS
low
power
consumption.
The
M54HC112/M74HC112 dual JK flip-flop features indi-
vidual J,K, clock, and asynchronous set and clear inputs
for each flip-flop. When the clock goes high, the inputs
are enabled and data will be accepted. The logic level
of the J and K inputs may be allowed to change when
the clock pulse is high and the bistable will function as
shown in the truth table. Input data is transferred to the
input on the negative going edge of the clock pulse. All
inputs are equipped withprotection circuits against static
discharge and transient excess voltage.
1/11
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CK, 2CK
Clock Input (HIGH to
LOW edge triggered)
2, 12
1K, 2K
Data Inputs: Flip-Flop 1
and 2
3, 11
1J, 2J
Data Inputs: Flip-Flop 1
and 2
4, 10
1PR, 2PR
Set Inputs
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 7
1Q, 2Q
Complement Flip-Flop
Outputs
15, 14
1CLR,
2CLR
Reset inputs
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
PR
J
K
CK
Q
Q
L
H
X
X
X
L
H
CLEAR
H
L
X
X
X
H
L
PRESET
L
L
X
X
X
H
H
H
H
L
L
Q
n
Q
n
NO CHANGE
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Q
n
Q
n
TOGGLE
H
H
X
X
Q
n
Q
n
NO CHANGE
X: Don't Care
LOGIC DIAGRAM (1/2 Package)
M54/M74HC112
2/11
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o
C
o
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2 V
0 to 1000
ns
V
CC
= 4.5 V
0 to 500
V
CC
= 6 V
0 to 400
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
M54/M74HC112
3/11
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level
Output Voltage
2.0
V
I
=
V
IH
or
V
IL
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
4.4
4.5
4.4
4.4
6.0
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-5.2 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
2.0
V
I
=
V
IH
or
V
IL
I
O
= 20
A
0.0
0.1
0.1
0.1
V
4.5
0.0
0.1
0.1
0.1
6.0
0.0
0.1
0.1
0.1
4.5
I
O
= 4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
= 5.2 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
2
20
40
A
M54/M74HC112
4/11
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
30
75
95
110
ns
4.5
8
15
19
22
6.0
7
13
16
19
t
PLH
t
PHL
Propagation
Delay Time
(CK - Q, Q)
2.0
52
125
155
190
ns
4.5
16
25
31
38
6.0
14
21
26
32
t
PLH
t
PHL
Propagation
Delay Time
(CLR, PR - Q, Q)
2.0
68
135
170
205
ns
4.5
17
27
34
41
6.0
14
23
29
35
f
MAX
Maximum Clock
Frequency
2.0
8
16
6.4
5.4
MHz
4.5
40
68
32
27
6.0
47
79
38
32
t
W(H)
t
W(L)
Minimum Pulse
Width
(CLOCK)
2.0
20
75
95
110
ns
4.5
5
15
19
22
6.0
4
13
16
19
t
W(L)
Minimum Pulse
Width
(CLR, PR)
2.0
20
75
95
110
ns
4.5
5
15
19
22
6.0
4
13
16
19
t
s
Minimum Set-up
Time
2.0
28
75
95
110
ns
4.5
7
15
19
22
6.0
6
13
16
19
t
h
Minimum Hold
Time
2.0
0
0
0
ns
4.5
0
0
0
6.0
0
0
0
t
REM
Minimum
Removal Time
(CLR, PR)
2.0
24
50
60
70
ns
4.5
4
10
12
14
6.0
3
9
10
12
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
(*)
Power Dissipation
Capacitance
33
pF
(*) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/2 (per FLIP/FLOP)
M54/M74HC112
5/11
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