M54HC273
M74HC273
October 1992
OCTAL D TYPE FLIP FLOP WITH CLEAR
B1R
(Plastic Package)
ORDER CODES :
M54HC273F1R
M74HC273M1R
M74HC273B1R
M74HC273C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
.
HIGH SPEED
f
MAX
= 67 MHz (TYP.) AT V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 4
A (MAX.) AT T
A
= 25
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA (MIN.)
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS273
The M54/74HC273 is a high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated in sili-
con gate C
2
MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
Information signals applied to D inputs are trans-
ferred to the Q outputs on the positive-going edge
of the clock pulse.
When the CLEAR input is held low, the Q output are
in the low logic level independent of the other inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
DESCRIPTION
INPUT AND OUTPUT EQUIVALENT CIRCUIT
1/11
TRUTH TABLE
INPUTS
OUTPUS
FUNCTION
CLEAR
CLOCK
D
Q
L
X
X
L
CLEAR
H
L
L
H
H
H
H
X
Qn
NO CHANGE
X: Don't Care
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLEAR
Master Reset Input
(Active LOW)
2, 5, 6, 9,
12, 15, 16,
19
Q0 to Q7
Flip Flop Outputs
3, 4, 7, 8,
13, 14, 17,
18
D0 to D7
Data Inputs
11
CLOCK
Clock Input (LOW to
HIGH, Edge Triggered)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOL
M54/M74HC273
2/11
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o
C
o
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2 V
0 to 1000
ns
V
CC
= 4.5 V
0 to 500
V
CC
= 6 V
0 to 400
M54/M74HC273
3/11
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level
Output Voltage
2.0
V
I
=
V
IH
or
V
IL
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
4.4
4.5
4.4
4.4
6.0
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-5.2 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
2.0
V
I
=
V
IH
or
V
IL
I
O
= 20
A
0.0
0.1
0.1
0.1
V
4.5
0.0
0.1
0.1
0.1
6.0
0.0
0.1
0.1
0.1
4.5
I
O
= 4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
= 5.2 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
4
40
80
A
M54/M74HC273
4/11
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
25
75
95
110
ns
4.5
7
15
19
22
6.0
6
13
16
19
t
PLH
t
PHL
Propagation
Delay Time
(CLOCK - Q)
2.0
54
145
180
220
ns
4.5
18
29
36
44
6.0
15
25
31
37
t
PLH
t
PHL
Propagation
Delay Time
(CLEAR - Q)
2.0
60
160
200
240
ns
4.5
20
32
40
48
6.0
17
27
34
41
f
MAX
Maximum Clock
Frequency
2.0
6
18
4.8
4
MHz
4.5
30
56
24
20
6.0
35
66
28
24
t
W(H)
t
W(L)
Minimum Pulse
Width
(CLOCK)
2.0
28
75
95
110
ns
4.5
7
15
19
22
6.0
6
13
16
19
t
W(L)
Minimum Pulse
Width
(CLEAR)
2.0
28
75
95
110
ns
4.5
7
15
19
22
6.0
6
13
16
19
t
s
Minimum Set-up
Time
2.0
20
75
95
110
ns
4.5
4
15
19
22
6.0
3
13
16
19
t
h
Minimum Hold
Time
2.0
0
0
0
ns
4.5
0
0
0
6.0
0
0
0
t
REM
Minimum
Removal Time
(CLEAR)
2.0
16
50
65
75
ns
4.5
4
10
13
15
6.0
3
9
11
13
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
(*)
Power Dissipation
Capacitance
43
pF
(*) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/8 (per Flip FLop), and the
total CPD when n pcs of Flip Flop operate can be gained by the following equations: CPD (total) = 32 + 11 x n
M54/M74HC273
5/11
PDF 
ZIP