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Электронный компонент: 74AC16373TTR

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1/10
February 2003
s
HIGH SPEED:
t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 8
A(MAX.) at T
A
=25C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
s
50
TRASMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC16373 CMOS 16 BIT D-TYPE LATCH
with 3 STATE OUTPUTS NON INVERTING
fabricated
with
sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC16373
16-BIT D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS (NON INVERTED)
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74AC16373TTR
TSSOP
PIN CONNECTION
74AC16373
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don`t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1LE
Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE *
L
H
L
L
L
H
H
H
74AC16373
3/10
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 30% to 70% of V
CC
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
8
ns/V
74AC16373
4/10
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
3.0
V
O
= 0.1 V or
V
CC
-0.1V
2.1
1.5
2.1
2.1
V
4.5
3.15
2.25
3.15
3.15
5.5
3.85
2.75
3.85
3.85
V
IL
Low Level Input
Voltage
3.0
V
O
= 0.1 V or
V
CC
-0.1V
1.5
0.9
0.9
0.9
V
4.5
2.25
1.35
1.35
1.35
5.5
2.75
1.65
1.65
1.65
V
OH
High Level Output
Voltage
3.0
I
O
=-50
A
2.9
2.99
2.9
2.9
V
4.5
I
O
=-50
A
4.4
4.49
4.4
4.4
5.5
I
O
=-50
A
5.4
5.49
5.4
5.4
3.0
I
O
=-12 mA
2.56
2.46
2.46
4.5
I
O
=-24 mA
3.86
3.76
3.76
5.5
I
O
=-24 mA
4.86
4.76
4.76
V
OL
Low Level Output
Voltage
3.0
I
O
=50
A
0.002
0.1
0.1
0.1
V
4.5
I
O
=50
A
0.001
0.1
0.1
0.1
5.5
I
O
=50
A
0.001
0.1
0.1
0.1
3.0
I
O
=12 mA
0.36
0.44
0.44
4.5
I
O
=24 mA
0.36
0.44
0.44
5.5
I
O
=24 mA
0.36
0.44
0.44
I
I
Input Leakage
Current
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
High Impedance
Output Leakage
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5
5
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
8
80
80
A
I
OLD
Dynamic Output
Current (note 1, 2)
5.5
V
OLD
= 1.65 V max
75
75
mA
I
OHD
V
OHD
= 3.85 V min
-75
-75
mA
74AC16373
5/10
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
0.3V
(**) Voltage range is 5.0V
0.5V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 C
-40 to 85 C -55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
3.3
(*)
8.0
10.0
15.6
15.6
ns
5.0
(**)
6.0
8.0
11.9
11.9
t
PLH
t
PHL
Propagation Delay
Time
D to Q
3.3
(*)
8.3
11.0
15.1
15.1
ns
5.0
(**)
6.0
9.1
10.1
10.1
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
11.8
19.8
22.3
22.3
ns
5.0
(**)
7.4
11.3
12.8
12.8
t
PLZ
t
PHZ
Output Disable
Time
3.3
(*)
7.1
9.5
10.2
10.2
ns
5.0
(**)
5.9
8.0
8.8
8.8
t
W
LE Pulse Width
HIGH
3.3
(*)
4.0
4.0
4.0
ns
5.0
(**)
5.0
5.0
5.0
t
s
Setup Time D to
LE, HIGH or LOW
3.3
(*)
1.5
1.5
1.5
ns
5.0
(**)
1.5
1.5
1.5
t
h
Hold Time D to LE,
HIGH or LOW
3.3
(*)
3
3
3
ns
5.0
(**)
2.5
2.5
2.5
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 C
-40 to 85 C -55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
3.5
pF
C
OUT
Output Capaci-
tance
5.0
15
pF
C
PD
Power Dissipation
Capacitance (note
1)
5.0
f
IN
=10MHz
25
pF
74AC16373
6/10
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES
(f=1MHz; 50% duty cycle)
Test
Switch
t
PLH,
t
PHL
Open
t
PZL,
t
PLZ
2V
CC
t
PZH,
t
PHZ
GND
74AC16373
7/10
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
74AC16373
8/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.2
0.047
A1
0.05
0.15
0.002
0.006
A2
0.9
0.035
b
0.17
0.27
0.0067
0.011
c
0.09
0.20
0.0035
0.0079
D
12.4
12.6
0.488
0.496
E
8.1 BSC
0.318 BSC
E1
6.0
6.2
0.236
0.244
e
0.5 BSC
0.0197 BSC
K
0
8
0
8
L
0.50
0.75
0.020
0.030
TSSOP48 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
7065588C
74AC16373
9/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
330
12.992
C
12.8
13.2
0.504
0.519
D
20.2
0.795
N
60
2.362
T
30.4
1.197
Ao
8.7
8.9
0.343
0.350
Bo
13.1
13.3
0.516
0.524
Ko
1.5
1.7
0.059
0.067
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
Tape & Reel TSSOP48 MECHANICAL DATA
74AC16373
10/10
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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