1/10
February 2002
s
5V TOLERANT INPUTS
s
HIGH SPEED: t
PD
= 6.8ns (MAX.) at V
CC
= 3V
s
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC373A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for 1.65 to 3.6 V
CC
operations and low power and low noise
applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVC373A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVC373AM
74LVC373AMTR
TSSOP
74LVC373ATTR
TSSOP
SOP
74LVC373A
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z :High Impedance
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
Asynchronous Master
Reset (Active LOW)
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7
3-State Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
LE
Latch Enable Input
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO
CHANGE
L
H
L
L
L
H
H
H
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (V
CC
= 0V)
-0.5 to +7.0
V
V
O
DC Output Voltage (High or Low State) (note 1)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 50
mA
I
OK
DC Output Diode Current (note 2)
- 50
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current per Supply Pin
100
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
74LVC373A
3/10
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
DC SPECIFICATIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
1.65 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (V
CC
= 0V)
0 to 5.5
V
V
O
Output Voltage (High or Low State)
0 to V
CC
V
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
24
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 2.7 to 3.0V)
12
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 2.3 to 2.7V)
8
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 1.65 to 2.3V)
4
mA
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2)
0 to 10
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
-40 to 85 C
-55 to 125 C
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
1.65 to 1.95
0.65V
CC
0.65V
CC
V
2.3 to 2.7
1.7
1.7
2.7 to 3.6
2
2
V
IL
Low Level Input
Voltage
1.65 to 1.95
0.35V
CC
0.35V
CC
V
2.3 to 2.7
0.7
0.7
2.7 to 3.6
0.8
0.8
V
OH
High Level Output
Voltage
1.65 to 3.6
I
O
=-100
A
V
CC
-0.2
V
CC
-0.2
V
1.65
I
O
=-4 mA
1.2
1.2
2.3
I
O
=-8 mA
1.7
1.7
2.7
I
O
=-12 mA
2.2
2.2
3.0
I
O
=-18 mA
2.4
2.4
3.0
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
1.65 to 3.6
I
O
=100
A
0.2
0.2
V
1.65
I
O
=4 mA
0.45
0.45
2.3
I
O
=8 mA
0.7
0.7
2.7
I
O
=12 mA
0.4
0.4
3.0
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
3.6
V
I
= 0 to 5.5V
5
5
A
I
off
Power Off Leakage
Current
0
V
I
or V
O
= 5.5V
10
10
A
I
OZ
High Impedance
Output Leakage
Current
3.6
V
I
= V
IH
orV
IL
V
O
= 0 to 5.5V
10
10
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
10
10
A
V
I
or V
O
= 3.6 to
5.5V
10
10
I
CC
I
CC
incr. per Input
2.7 to 3.6
V
IH
= V
CC
-0.6V
500
500
A
74LVC373A
4/10
DYNAMIC SWITCHING CHARACTERISTICS
1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
2) Parameter guaranteed by design
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 C
Min.
Typ.
Max.
V
OLP
Dynamic Low Level Quiet
Output (note 1)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
0.8
V
V
OLV
-0.8
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
= t
r
(ns)
-40 to 85 C
-55 to 125 C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time D to Q
1.65 to 1.95
30
1000
2.0
TBD
TBD
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
1.5
7.8
1.5
9.4
3.0 to 3.6
50
500
2.5
1
6.8
1
8.2
t
PLH
t
PHL
Propagation Delay
Time LE to Q
1.65 to 1.95
30
1000
2.0
TBD
TBD
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
1.5
7.8
1.5
9.4
3.0 to 3.6
50
500
2.5
1
6.8
1
8.2
t
PZL
t
PZH
Output Enable Time
1.65 to 1.95
30
1000
2.0
TBD
TBD
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
1
8.7
1
10.4
3.0 to 3.6
50
500
2.5
1
7.7
1
9.2
t
PLZ
t
PHZ
Output Disable Time 1.65 to 1.95
30
1000
2.0
TBD
TBD
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
2
7.6
2
9.1
3.0 to 3.6
50
500
2.5
2
7.0
2
8.4
t
W
LE Pulse Width
HIGH
1.65 to 1.95
30
1000
2.0
TBD
TBD
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
3.3
3.3
3.0 to 3.6
50
500
2.5
3.3
3.3
t
s
Setup Time D to LE
(HIGH to LOW)
1.65 to 1.95
30
1000
2.0
TBD
TDB
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
2
2
3.0 to 3.6
50
500
2.5
2
2
t
h
Hold Time D to
CLOCK, HIGH or
LOW
1.65 to 1.95
30
1000
2.0
TBD
TBD
ns
2.3 to 2.7
30
500
2.0
TBD
TBD
2.7
50
500
2.5
1.5
1.5
3.0 to 3.6
50
500
2.5
1.5
1.5
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
2.7 to 3.6
1
1
ns
74LVC373A
5/10
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
TEST CIRCUIT
R
T
= Z
OUT
of pulse generator (typically 50
)
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 C
Min.
Typ.
Max.
C
IN
Input Capacitance
4
pF
C
PD
Power Dissipation Capacitance
(note 1)
1.8
f
IN
= 10MHz
28
pF
2.5
30
3.3
34
Symbol
V
CC
1.65 to 1.95V
2.3 to 2.7V
2.7V
3.0 to 3.6V
C
L
30pF
30pF
50pF
50pF
R
L
=
R
1
1000
500
500
500
V
S
2 x V
CC
2 x V
CC
6V
7V
V
IH
V
CC
V
CC
2.7V
3.0V
V
M
V
CC
/2
V
CC
/2
1.5V
1.5V
V
OH
V
CC
V
CC
3.0V
3.5V
V
X
V
OL
+ 0.15V
V
OL
+ 0.15V
V
OL
+ 0.3V
V
OL
+ 0.3V
V
Y
V
OH
- 0.15V
V
OH
- 0.15V
V
OH
- 0.3V
V
OH
- 0.3V
t
r
= t
r
<2.0ns
<2.0ns
<2.5ns
<2.5ns
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