1/12
July 2001
s
HIGH SPEED:
t
PD
= 8.3 ns (TYP.) at V
CC
= 3.3 V
s
COMPATIBLE WITH TTL OUTPUTS
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
= 3.3V
s
75
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ299 is a low voltage CMOS 8 BIT
PIPO SHIFT REGISTER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power and low noise 3.3V applications.
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table.
When one or both enable inputs, (G1, G2) are
high, the eight input/output terminals are in the
high impedance state; however sequential
operation or clearing of the register is not affected.
Clear function is asynchronous to clock.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVQ299M
74LVQ299MTR
TSSOP
74LVQ299TTR
TSSOP
SOP
74LVQ299
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
* When one or both controls are high, the eight input/output terminals are the high impedance state: however sequential operation or cleaning
of the register is not affected.
Z : High Impedance
Qn0 : The level of An before the indicated steady state input conditions were established.
Qnn : The level of Qn before the most recent active transition indicated by OR
a, h : The level of the steady state inputs A, H, respectively.
X : Don't Care
PIN No
SYMBOL
NAME AND FUNCTION
1, 19
S0, S1
Mode Select Inputs
2, 3
G1, G2
3-State Output Enable Inputs (Active LOW)
7, 13, 6, 14, 5, 15, 4, 16
A/QA to H/QH
Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)
8, 17
QA',QH'
Serial Outputs (Standard Output)
9
CLEAR
Asynchronous Master Reset Input (Active LOW)
11
SR
Serial Data Shift Right Input
12
CLOCK
Clock Input (LOW to HIGH, Edge-triggered)
18
SL
Serial Data Shift Left Input
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
MODE
INPUTS
INPUTS/OUTPUTS
OUTPUTS
CLEAR
FUNCTION
SELECTED
OUTPUT
CONTROL
CLOCK
SERIAL
A/QA
H/QH
QA'
QH'
S1
S0
G1*
G2*
SL
SR
Z
L
H
H
X
X
X
X
X
Z
Z
L
L
CLEAR
L
L
X
L
L
X
X
X
L
L
L
L
L
X
L
L
L
X
X
X
L
L
L
L
HOLD
H
L
L
L
L
X
X
X
QA0
QH0
QA0
QH0
SHIFT
RIGHT
H
L
H
L
L
X
H
H
QGn
H
QGn
H
L
H
L
L
X
L
L
QGn
L
QGn
SHIFT
LEFT
H
H
L
L
L
H
X
QBn
H
QBn
H
H
H
L
L
L
L
X
QBn
L
QBn
L
LOAD
H
H
H
X
X
X
X
a
h
a
h
74LVQ299
3/12
LOGIC DIAGRAM
74LVQ299
4/12
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 3.0V (note 2)
0 to 10
ns/V
74LVQ299
5/12
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
3.0 to
3.6
2.0
2.0
2.0
V
V
IL
Low Level Input
Voltage
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
3.0
I
O
=-50
A
2.9
2.99
2.9
2.9
V
I
O
=-12 mA
2.58
2.48
2.48
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
3.0
I
O
=50
A
0.002
0.1
0.1
0.1
V
I
O
=12 mA
0
0.36
0.44
0.44
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
3.6
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
High Impedance
Output Leakage
Current
3.6
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
5.0
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
I
OLD
Dynamic Output
Current (note 1, 2)
3.6
V
OLD
= 0.8 V max
36
25
mA
I
OHD
V
OHD
= 2 V min
-25
-25
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.5
0.8
V
V
OLV
-0.8
-0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
3.3
2
V
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
V
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